GB2243951A - Method of fabricating DRAM - Google Patents

Method of fabricating DRAM Download PDF

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Publication number
GB2243951A
GB2243951A GB9109684A GB9109684A GB2243951A GB 2243951 A GB2243951 A GB 2243951A GB 9109684 A GB9109684 A GB 9109684A GB 9109684 A GB9109684 A GB 9109684A GB 2243951 A GB2243951 A GB 2243951A
Authority
GB
United Kingdom
Prior art keywords
oxide layer
polysilicon
bit line
pad
pad polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9109684A
Other versions
GB2243951B (en
GB9109684D0 (en
Inventor
Young Jun Kwo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Goldstar Electron Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Goldstar Electron Co Ltd filed Critical Goldstar Electron Co Ltd
Publication of GB9109684D0 publication Critical patent/GB9109684D0/en
Publication of GB2243951A publication Critical patent/GB2243951A/en
Application granted granted Critical
Publication of GB2243951B publication Critical patent/GB2243951B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In a method of fabricating a semiconductor device comprising a gate structure, a contact pad 27, 28 and a capacitor 29, 30, 31, the pad polysilicon is formed on one side of the gate structure and extends over it. An oxide layer 28a is formed over the pad polysilicon 27 and at both sides of it. A contact hole is formed on the other side of the gate structure and a first capacitor plate polysilicon 29 is formed extending to the pad oxide layer 28a. In this way the packing density of devices may be increased without lowering the value of the capacitor. The contact area of the contact pad 27 is also increased. <IMAGE>

Description

A METHOD FOR FABRICATING SEMICONDUCTOR DEVICES The present invention relates to a method for fabricating semiconductor devices in which the capacitance of the capacitor and the contact area of the bit lines can be expanded, thereby making it possible to increase the density of the semiconductor device.
As shown in Figures la to 1C, conventional semiconductor devices are manufactured in a manner described below. A gate oxide layer 2 and a gate 3 are formed upon the relevant portions of a semiconductor substrate 1, and then a side wall 4 is formed. Then, a source-drain region 5 is formed by performing an ion-implantation, and then, an oxide layer 6 is deposited on the whole surface thereof. A buried contact is then opened,,ths being for forming a capacitor node, and next, there is formed a capacitor which consists of a storage node polysilicon 7, a dielectric layer 8, and a plate polysilicon 9 as shown in Figures la and lb. Thereafter, an insulating layer 10 is deposited, a bit line contact is opened in order to form a bit line, and then a bit line 11 is formed, thereby completing the formation of the semiconductor device.
However, in such a conventional semiconductor device, i.e. in such a conventional semiconductor capacitor, the stack height is too low, with the undesirable result that the total capacitor area is limited, thereby making it impossible to obtain a large capacitance.
Further, when opening the bit line contact in order to form the bit line, the margin of the bit line contact has to be reduced if a short between the bit line and the gate is to be prevented, and this increases the contact resistance.
Also, the step coverage characteristics becomes aggravated, thereby degrading the device characteristics.
The present invention is intended to overcome the above described disadvantages of the conventional semiconductor devices.
Therefore, it is an object of the present invention to provide a method for fabricating semiconductor devices, in which the effective area of the capacitor is expanded.
It is another object of the present invention to provide a method for fabricating semiconductor devices, in which the bit line contact resistance is decreased.
These and other objects are achieved in a method for fabricating semiconductor devices, comprising the steps of: (a) forming an oxide layer, a gate, a gate side wall and a source-drain region upon the relevant portions of a semiconductor substrate, depositing a first oxide layer on the whole surface thereof, opening a bit line contact, depositing a pad polysilicon and a second oxide layer on the whole surface thereof, removing the pad polysilicon and the second oxide layer except an area extended on the first oxide layer which is deposited on the gates adjacent to the bit line contact; (b) forming an insulating film on both ends of the pad polysilicon; (c) opening a buried contact in order to form a capacitor, and forming a capacitor consisting of a storage polysilicon, a dielectric layer and a plate polysilicon so as to extend to the second oxide layer; and (d) depositing an insulating layer on the whole surface thereof, and exposing the pad polysilicon except desired areas of each sides thereof, forming a bit line thereupon.
The above objects and other advantages of the present invention will become more apparent by describing in detail the preferred embodiment of the present invention with reference to the attached drawings in which: Figures la to lc are sectional views showing the process for formation of the conventional semiconductor device; and Figures 2a to 2e are sectional views showing the process for formation of the semiconductor device according to the present invention.
Referring to Figures 2a to 2e which illustrate the preferred embodiment of the present invention, first a gate oxide layer 22 and a gate 23 are formed on the relevant portions of a semiconductor substrate 21, and side walls 24 are formed. Then a source-drain region 25 is formed by performing an ion-implanation, and then, an oxide layer 26 is deposited on the whole surface therof. Next a bit line contact is opened, and then a pad polysilicon 27 and an oxide layer 28 are successively deposited upon the whole surface thereof.
Then the pad polysilicon 27 and the oxide layer 28 are etched in such a manner that they remain only on the oxide layer 26 which is formed on the gates 23 adjacent to the bit line contact.
Thereafter, as shown in Figure 2b, a heat treatment is performed at a temperature of from 600 to 11000C under an oxidizing atmosphere, so that an oxidation occurs on the exposed portions of the pad polysilicon 27, i.e. its opposite end portions in a predetermined width. Thus an oxide layer 28a is formed in such form that it should cover the pad polysilicon 27. In the preferred embodiment of the present invention, a heat treatment is carried out under an oxidizing atmosphere as described above; in an alternative way, the oxide layer 28a can be formed by applying an oxide side wall forming process so as to cover the pad polysilicon 27.
Then as shown in Figure 2c, the oxide layer 26 is removed on a relevant portion so that a buried contact is opened, and thereupon a capacitor consisting of a storage node polysilicon 29, a dielectric layer 30 and a plate polysilicon 31 is formed and an insulating layer 32 is deposited thereafter. The capacitor can be made to extend to cover the oxide layer 28a and therfore the effective area of the capacitor is increased.
Then, as shown in Figure 2d, the pad polysilicon 27 which is formed on the bit line contact is made to be exposed except the end portions thereof and then an impurity is ion-implanted into the exposed portion of the pad polysilicon 27. In the case where the pad polysilicon 27 is used in a predoped state, that is in the case where an in-situ doping is performed on the pad polysilicon 27, the ion-implanting process can be skipped. Next, a bit line 33 is formed on the structure described above as shown in Figure 2e and a semiconductor device of the present invention is obtained.
According to the present invention as described above, the active region and the bit line can be formed in a straight line and therefore the implementation of the process becomes easier. Further, the bit line can be connected to the bit line contact by forming a pad polysilicon, so that the margin of the bit line contact should be increased to the maximum, that the bit line contact resistance should be decreased, and that the step coverage characteristics should be improved.
Further, the area of the capacitor can be made to extend to cover the oxide layer which is formed on the pad polysilicon and therfore an increased capacitance is obtained. As a result, a significant effect by improving the density of semiconductor device is achieved.
It is to be understood that the invention includes an electronic device incorporating a semiconductor device in accordance with the present invention.

Claims (8)

CLAIMS:
1. A method for fabricating semiconductor devices comprising the steps of: (a) forming an oxide layer, a gate, a gate side wall and a source-drain region upon the relevant portions of a semiconductor substrate, depositing a first oxide layer on the whole surface thereof, opening a bit line contact, depositing a pad polysilicon and a second oxide layer on the whole surface thereof, removing said pad polysilicon and said second oxide layer except an area extended on the first oxide layer which is deposited on the gates adjacent to said bit line contact; (b) forming an insulating film on both ends of said polysilicon; (c) opening a buried contact in order to form a capacitor, and forming a capacitor consisting of a storage polysilicon, a dielectric layer and a plate polysilicon so as to extend to said second oxide layer; and (d) depositing an insulating layer on the whole surface thereof, and exposing said pad polysilicon except desired areas of each sides thereof, forming a bit line thereupon.
2. A method as claimed in claim 1, wherein the step (b) comprises step of depositing another oxide layer on the whole surface thereof, step of reactive ion etching said another oxide layer to form an oxide side wall.
3. A method as claimed in claim 1, wherein the step (b) comprises step of performing a heat treatment at a temperature of 600 to 11000C under an oxidizing atmosphere to oxidize each end of said pad polysilicon in a predetermined width.
4. A method as claimed in any one of the preceding claims wherein an in-situ doping process is applied when said pad polysilicon is deposited in step (a).
5. A method as claimed in any one of the preceding claims wherein the step (d) further comprises the step of doping an impurity into said exposed pad polysilicon.
6. A method as claimed in claim 1 and substantially as hereinbefore described with reference to Figures 2a to 2e.
7. A semiconductor device when made by a method as claimed in any one of the preceding claims.
8. An electronic device incorporating a semiconductor device as claimed in claim 8.
GB9109684A 1990-05-08 1991-05-03 A method for fabricating semiconductor devices Expired - Fee Related GB2243951B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900006472A KR920008294B1 (en) 1990-05-08 1990-05-08 Method of manufacturing for semiconductor device

Publications (3)

Publication Number Publication Date
GB9109684D0 GB9109684D0 (en) 1991-06-26
GB2243951A true GB2243951A (en) 1991-11-13
GB2243951B GB2243951B (en) 1994-03-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB9109684A Expired - Fee Related GB2243951B (en) 1990-05-08 1991-05-03 A method for fabricating semiconductor devices

Country Status (4)

Country Link
JP (1) JPH0719849B2 (en)
KR (1) KR920008294B1 (en)
DE (1) DE4114917A1 (en)
GB (1) GB2243951B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0749156A1 (en) * 1995-05-23 1996-12-18 Siemens Aktiengesellschaft Semiconductor device with self-aligned contacts and method of fabrication

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960004079B1 (en) * 1992-12-19 1996-03-26 Lg Semicon Co Ltd Contact hole forming method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0352893A1 (en) * 1988-06-29 1990-01-31 Fujitsu Limited Metal insulator semiconductor type dynamic random access memory device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183952A (en) * 1985-02-09 1986-08-16 Fujitsu Ltd Semiconductor memory device and manufacture thereof
DE3788107D1 (en) * 1986-10-16 1993-12-16 Siemens Ag Memory cell arrangement for dynamic semiconductor memories.
JPH01129440A (en) * 1987-11-14 1989-05-22 Fujitsu Ltd Semiconductor device
JPH0279462A (en) * 1988-09-14 1990-03-20 Toshiba Corp Semiconductor memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0352893A1 (en) * 1988-06-29 1990-01-31 Fujitsu Limited Metal insulator semiconductor type dynamic random access memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0749156A1 (en) * 1995-05-23 1996-12-18 Siemens Aktiengesellschaft Semiconductor device with self-aligned contacts and method of fabrication
US5864155A (en) * 1995-05-23 1999-01-26 Siemens Aktiengesellschaft Semiconductor array with self-adjusted contacts

Also Published As

Publication number Publication date
KR920008294B1 (en) 1992-09-26
DE4114917A1 (en) 1991-11-21
JPH05343635A (en) 1993-12-24
JPH0719849B2 (en) 1995-03-06
KR910020942A (en) 1991-12-20
GB2243951B (en) 1994-03-02
GB9109684D0 (en) 1991-06-26

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 20060503