KR910019170A - 초전도 집적회로소자의 제조방법 - Google Patents

초전도 집적회로소자의 제조방법 Download PDF

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Publication number
KR910019170A
KR910019170A KR1019900005997A KR900005997A KR910019170A KR 910019170 A KR910019170 A KR 910019170A KR 1019900005997 A KR1019900005997 A KR 1019900005997A KR 900005997 A KR900005997 A KR 900005997A KR 910019170 A KR910019170 A KR 910019170A
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KR
South Korea
Prior art keywords
manufacturing
integrated circuit
circuit device
superconducting integrated
mask layer
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Application number
KR1019900005997A
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English (en)
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KR930004024B1 (ko
Inventor
정주영
Original Assignee
서주인
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 서주인, 삼성전자 주식회사 filed Critical 서주인
Priority to KR1019900005997A priority Critical patent/KR930004024B1/ko
Priority to FR9014863A priority patent/FR2661557B1/fr
Priority to DE4040053A priority patent/DE4040053A1/de
Priority to JP3000763A priority patent/JP2614942B2/ja
Priority to GB9108001A priority patent/GB2244882B/en
Priority to NL9100725A priority patent/NL9100725A/nl
Priority to US07/731,050 priority patent/US5219830A/en
Publication of KR910019170A publication Critical patent/KR910019170A/ko
Application granted granted Critical
Publication of KR930004024B1 publication Critical patent/KR930004024B1/ko

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661—Processes performed after copper oxide formation, e.g. patterning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/85—Superconducting active materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/70—High TC, above 30 k, superconducting device, article, or structured stock
    • Y10S505/701—Coated or thin film device, i.e. active or passive
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/728—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/742—Annealing

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)

Abstract

내용 없음

Description

초전도 집적회로소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 결정구조가 다른 절연성 기판에 초전도 박막을 증착한 종래의 hetero-epitaxy기술의 가공후 단면도, 제 2 도는 본 발명에서의 사방정계의 YBa2Cu3Ox의 기판에 초전도 박막을 증착한 기술 가공후 단면도, 제 3 도는 본 발명에서의 개략 공정도.

Claims (3)

  1. 정방정계상(tetragonal phase)의 YBa2Cu3Ox 기판에 선택적으로산소를 확산시키는 것을 특징으로 하는 초전도 집적회로소자의 제조방법.
  2. 제 1 항에 있어서, 상기 초전도 집적회로의 제조방법이 (1) 정방정계상의 YBa2Cu3O6.5기판을 웨이퍼 형태로 가공하는 공정. (2) 상기 웨이퍼상에 마스크층을 증착한 후 그 위에 포토레지스트(photo resist, PR)을 증착하는 공정, (3) 포토리소그래피(photolithography)공정을 통해 선택된 부분의 PR을 제거하는 공정, (4) 화학 에칭(Chemical etching)으로 소자를 제조할 부분(active region)에 증착된 마스크층을 제거후 포토레지스트를 제거하는 공정 및 (5) 산소를 웨이퍼 표면으로부터 확산시켜 마스크층이 제거된 부분만 표면으로부터 고온 초전도상을 제조하는 공정으로 구성되는 것을 특징으로 하는 초전도 직접회로소자의 제조방법.
  3. 제 1 항 또는 제 2 항에 있어서, 웨이퍼 표면에 확산된 산소의 두께는 10μ m이하인 것을 특징으로 하는 초전도 집적회로소자의 제조방법.
    ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.
KR1019900005997A 1990-04-27 1990-04-27 초전도 집적회로소자의 제조방법 KR930004024B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019900005997A KR930004024B1 (ko) 1990-04-27 1990-04-27 초전도 집적회로소자의 제조방법
FR9014863A FR2661557B1 (fr) 1990-04-27 1990-11-28 Procede pour preparer des circuits integres supraconducteurs.
DE4040053A DE4040053A1 (de) 1990-04-27 1990-12-14 Verfahren zum herstellen von supraleitenden integrierten schaltungen
JP3000763A JP2614942B2 (ja) 1990-04-27 1991-01-08 超伝導集積回路素子の製造方法
GB9108001A GB2244882B (en) 1990-04-27 1991-04-16 A process for preparing superconducting integrated circuits
NL9100725A NL9100725A (nl) 1990-04-27 1991-04-26 Werkwijze ter vervaardiging van supergeleidende geintegreerde schakelingen.
US07/731,050 US5219830A (en) 1990-04-27 1991-07-15 Process for preparing high-Tc superconducting integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900005997A KR930004024B1 (ko) 1990-04-27 1990-04-27 초전도 집적회로소자의 제조방법

Publications (2)

Publication Number Publication Date
KR910019170A true KR910019170A (ko) 1991-11-30
KR930004024B1 KR930004024B1 (ko) 1993-05-19

Family

ID=19298462

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900005997A KR930004024B1 (ko) 1990-04-27 1990-04-27 초전도 집적회로소자의 제조방법

Country Status (7)

Country Link
US (1) US5219830A (ko)
JP (1) JP2614942B2 (ko)
KR (1) KR930004024B1 (ko)
DE (1) DE4040053A1 (ko)
FR (1) FR2661557B1 (ko)
GB (1) GB2244882B (ko)
NL (1) NL9100725A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7483494B2 (en) 2001-08-10 2009-01-27 Interdigital Corporation Dynamic link adaption for time division duplex (TDD)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05251777A (ja) * 1991-12-13 1993-09-28 Sumitomo Electric Ind Ltd 超電導電界効果型素子およびその作製方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3850580T2 (de) * 1987-01-30 1994-10-27 Hitachi Ltd Supraleiteranordnung.
JPH0638525B2 (ja) * 1987-05-06 1994-05-18 株式会社半導体エネルギ−研究所 超電導装置の作製方法
CA1328242C (en) * 1987-05-18 1994-04-05 Nobuhiko Fujita Process for manufacturing a superconductor and a method for producing a superconducting circuit
US5041420A (en) * 1987-06-26 1991-08-20 Hewlett-Packard Company Method for making superconductor films from organometallic precursors
DK160382C (da) * 1987-09-22 1991-08-12 Ib Johannsen Fremgangsmaade til tilvejebringelse af et elektrisk kredsloeb indeholdende josephson dioder
JP2707499B2 (ja) * 1987-11-26 1998-01-28 住友電気工業株式会社 酸化物超電導体の製造方法
JPH01160888A (ja) * 1987-12-15 1989-06-23 Mitsubishi Electric Corp ビームを用いた局部熱処理方法
NL8703039A (nl) * 1987-12-16 1989-07-17 Philips Nv Werkwijze voor het patroonmatig vervaardigen van een dunne laag uit een oxidisch supergeleidend materiaal.
US4939308A (en) * 1988-04-29 1990-07-03 Allied-Signal Inc. Method of forming crystallite-oriented superconducting ceramics by electrodeposition and thin film superconducting ceramic made thereby
JPH0354875A (ja) * 1989-07-24 1991-03-08 Furukawa Electric Co Ltd:The 超電導体回路の形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7483494B2 (en) 2001-08-10 2009-01-27 Interdigital Corporation Dynamic link adaption for time division duplex (TDD)

Also Published As

Publication number Publication date
FR2661557B1 (fr) 1995-10-13
KR930004024B1 (ko) 1993-05-19
GB2244882A (en) 1991-12-11
GB2244882B (en) 1994-12-21
JP2614942B2 (ja) 1997-05-28
GB9108001D0 (en) 1991-06-05
DE4040053A1 (de) 1991-10-31
FR2661557A1 (fr) 1991-10-31
JPH04226089A (ja) 1992-08-14
US5219830A (en) 1993-06-15
NL9100725A (nl) 1991-11-18

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