KR910017636A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

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Publication number
KR910017636A
KR910017636A KR1019910001127A KR910001127A KR910017636A KR 910017636 A KR910017636 A KR 910017636A KR 1019910001127 A KR1019910001127 A KR 1019910001127A KR 910001127 A KR910001127 A KR 910001127A KR 910017636 A KR910017636 A KR 910017636A
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KR
South Korea
Prior art keywords
bit line
source
drain
mos transistor
bit
Prior art date
Application number
KR1019910001127A
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English (en)
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KR0127296B1 (ko
Inventor
다미히로 이시무라
마사후미 미야와끼
산페이 미야모또
히데노리 우에하라
Original Assignee
고스기 노부미쓰
오끼덴끼고오교 가부시끼가이샤
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Application filed by 고스기 노부미쓰, 오끼덴끼고오교 가부시끼가이샤 filed Critical 고스기 노부미쓰
Publication of KR910017636A publication Critical patent/KR910017636A/ko
Application granted granted Critical
Publication of KR0127296B1 publication Critical patent/KR0127296B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065Differential amplifiers of latching type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명의 실시예를 나타낸 반도체 기억장치의 요부의 회로도, 제 6도는 제 1도 중의 B-B선 단면도, 제 7도는 제 1도의 전압 파형도.

Claims (1)

  1. 복수의 워어드선과, 상기 워어드선과 교차하는 제 및 제 2의 비트선으로된 복수쌍의 비트수쌍과, 상기 각 워어드선 및 비트선쌍의 교차개소에 각각 접속된 복수의 메모리 셀과, 상기 각 비트선쌍의 전위차를 각각 검지, 증폭하는 보수의 센스앰프회로를 갖추고, 상기 복수의 센스앰프회로 전부 또는 그 일부가 반도체 기판내의 분리층에 형성된 CMOS 굿의 반도체 기억장치에 있어서, 상기한 분리층에 형성되는 센스임프회로는 게이트가 상기 제 2의 비트선에, 드레인 또는 소오스가 상기 제 1의 비트선에 각각 접속된 제 1의 MOS 트랜지스터와, 게이트가 상기 제 1의 비트선에, 드레인 또는 소오스가 상기 제 2의 비트선에 각각 접속된 제 2의 MOS 트랜지스터를 갖추고, 상기 제 1의 MOS 트랜지스터의 소오스또는 드레인과 상기 제 2의 MOS 트랜지스터의 소소스 또는 드레인을 센스업 구동신호선에 공통접속함과 함께, 상기 제 1 및 제 2의 MOS 트랜지스터의 분리층 바어어스원을 상기 센스엠프구동신호선에 접속한 것을 특징으로 하는 반도체 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910001127A 1990-03-22 1991-01-23 반도체 기억장치 KR0127296B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP02072639A JP3093771B2 (ja) 1990-03-22 1990-03-22 半導体記憶装置
JP02-072639 1990-03-22
JP02-07239 1990-03-22

Publications (2)

Publication Number Publication Date
KR910017636A true KR910017636A (ko) 1991-11-05
KR0127296B1 KR0127296B1 (ko) 1997-12-29

Family

ID=13495158

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910001127A KR0127296B1 (ko) 1990-03-22 1991-01-23 반도체 기억장치

Country Status (5)

Country Link
US (2) US5087957A (ko)
EP (1) EP0449028B1 (ko)
JP (1) JP3093771B2 (ko)
KR (1) KR0127296B1 (ko)
DE (1) DE69119957T2 (ko)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04352467A (ja) * 1991-05-30 1992-12-07 Toshiba Corp Mos型半導体集積回路装置
WO1993005514A1 (en) * 1991-09-04 1993-03-18 Vlsi Technology, Inc. Anti-fuse structures and methods for making same
US5321647A (en) * 1992-05-07 1994-06-14 International Business Machines Corp. Semiconductor memory device and operational method with reduced well noise
US5323044A (en) * 1992-10-02 1994-06-21 Power Integrations, Inc. Bi-directional MOSFET switch
KR0133973B1 (ko) 1993-02-25 1998-04-20 기다오까 다까시 반도체 기억장치
JPH07211510A (ja) * 1994-01-27 1995-08-11 Nippondenso Co Ltd 半導体装置
JP3549602B2 (ja) * 1995-01-12 2004-08-04 株式会社ルネサステクノロジ 半導体記憶装置
JP2751891B2 (ja) * 1995-09-29 1998-05-18 日本電気株式会社 半導体集積回路
JPH09199607A (ja) * 1996-01-18 1997-07-31 Nec Corp Cmos半導体装置
US5973374A (en) * 1997-09-25 1999-10-26 Integrated Silicon Solution, Inc. Flash memory array having well contact structures
KR20000045475A (ko) * 1998-12-30 2000-07-15 김영환 웰 바이어싱 트랜지스터 형성방법
US20050283189A1 (en) * 1999-03-31 2005-12-22 Rosenblatt Peter L Systems and methods for soft tissue reconstruction
US6744301B1 (en) * 2000-11-07 2004-06-01 Intel Corporation System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise
US6445216B1 (en) 2001-05-14 2002-09-03 Intel Corporation Sense amplifier having reduced Vt mismatch in input matched differential pair
US7825488B2 (en) * 2006-05-31 2010-11-02 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuits and modular methods of forming the same
US7667268B2 (en) * 2002-08-14 2010-02-23 Advanced Analogic Technologies, Inc. Isolated transistor
US8089129B2 (en) * 2002-08-14 2012-01-03 Advanced Analogic Technologies, Inc. Isolated CMOS transistors
US8513087B2 (en) * 2002-08-14 2013-08-20 Advanced Analogic Technologies, Incorporated Processes for forming isolation structures for integrated circuit devices
US7330388B1 (en) 2005-09-23 2008-02-12 Cypress Semiconductor Corporation Sense amplifier circuit and method of operation
DE102007007565A1 (de) * 2007-02-15 2008-08-21 Qimonda Ag Halbleiter-Speicherbauelement mit umschaltbarem Substratpotential, und Verfahren zum Betrieb eines Halbleiter-Speicherbauelements
US7795681B2 (en) * 2007-03-28 2010-09-14 Advanced Analogic Technologies, Inc. Isolated lateral MOSFET in epi-less substrate

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL176029C (nl) * 1973-02-01 1985-02-01 Philips Nv Geintegreerde logische schakeling met komplementaire transistoren.
US4000413A (en) * 1975-05-27 1976-12-28 Intel Corporation Mos-ram
US4195357A (en) * 1978-06-15 1980-03-25 Texas Instruments Incorporated Median spaced dummy cell layout for MOS random access memory
US4198697A (en) * 1978-06-15 1980-04-15 Texas Instruments Incorporated Multiple dummy cell layout for MOS random access memory
EP0166386A3 (de) * 1984-06-29 1987-08-05 Siemens Aktiengesellschaft Integrierte Schaltung in komplementärer Schaltungstechnik
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch
JPH0622276B2 (ja) * 1984-10-18 1994-03-23 日本テキサス・インスツルメンツ株式会社 半導体装置
JPH0654796B2 (ja) * 1986-07-14 1994-07-20 株式会社日立製作所 複合半導体装置
US4712124A (en) * 1986-12-22 1987-12-08 North American Philips Corporation Complementary lateral insulated gate rectifiers with matched "on" resistances
US5023689A (en) * 1987-03-18 1991-06-11 Nec Corporation Complementary integrated circuit device equipped with latch-up preventing means

Also Published As

Publication number Publication date
EP0449028B1 (en) 1996-06-05
US5087957A (en) 1992-02-11
JP3093771B2 (ja) 2000-10-03
JPH03272171A (ja) 1991-12-03
DE69119957T2 (de) 1997-02-13
KR0127296B1 (ko) 1997-12-29
DE69119957D1 (de) 1996-07-11
US5177586A (en) 1993-01-05
EP0449028A1 (en) 1991-10-02

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