KR890013657A - 반도체메모리 장치 - Google Patents

반도체메모리 장치 Download PDF

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Publication number
KR890013657A
KR890013657A KR1019890001785A KR890001785A KR890013657A KR 890013657 A KR890013657 A KR 890013657A KR 1019890001785 A KR1019890001785 A KR 1019890001785A KR 890001785 A KR890001785 A KR 890001785A KR 890013657 A KR890013657 A KR 890013657A
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KR
South Korea
Prior art keywords
memory device
semiconductor memory
transistors
memory cells
wlm
Prior art date
Application number
KR1019890001785A
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English (en)
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KR920008247B1 (ko
Inventor
노부아키 오츠카
준이치 미야모토
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Publication of KR890013657A publication Critical patent/KR890013657A/ko
Application granted granted Critical
Publication of KR920008247B1 publication Critical patent/KR920008247B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)

Abstract

내용 없음.

Description

반도체 메모리 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명의 제 1실시예에 따른 반도체메모리 장치를 도시해 놓은 블록도,
제 2도는 본 발명의 제 2실시예에 따른 반도체메모리 장치를 도시해 놓은 블록도,
제 3도는 제 1도 및 제 2도에 도시된 각 반도체메모리 장치에 적용되는 행디코더의 1개의 워드선에 대응하는 구성을 도시해 놓은 블록도.

Claims (6)

  1. 복수의 메모리셀을 갖춘 메모리셀어레이(M11∼Mmn)와, 어드레스신호에 대응해서 워드선(WL1∼WLm) 및 비트선(BL1∼BLm)을 각각 선택하는 행디코더(20) 및 열디코더(22), 상기 각 워드선(WL1∼WLm) 에 게이트가 가각 접속되면서 소오스가 고정전위에 접속되고, 또 드레인이 소정 패드(24)에 공통 접속된 복수의 트랜지스터(Q1∼Qm)를 구비하여 구성된 것을 특징으로 하는 반도체메모리장치.
  2. 제 1항에 있어서, 상기 각 메모리셀 (M11∼Mmn)이 게이트가 대응하는 워드선(WL1∼WLm)에 접속되어 있는 상기 각 트랜지스터 (Q1∼Qm)와 실질적으로 동일구조의 트랜지스터로 이루어진 것을 특징으로 하는 반도체메모리장치.
  3. 제 2항에 있어서, 상기 각 메모리셀 (M11∼Mmn)은 N챈널형 MOS트랜지스터를 포함하고 있고, 게이트가 대응하는 워드선(WL1∼WLm)에 접속되어 있는 상기 각 트랜지스터(Q1∼Qm)도 N챈널형 MOS트랜지스터인 것을 특징으로하는 반도체메모리장치.
  4. 제 2항에 있어서, 상기 각 메모리셀 (M11∼Mmn)은 플로팅게이트형 MOS트랜지스터를 포함하고 있고, 게이트가 대응하는 워드선에 접속되어 있는 상기 각 트랜지스터(Q1'∼Qm')도 플로팅게이트형 MOS트랜지스터인 것을 특징으로 하는 반도체메모리장치.
  5. 제 1항에 있어서, 상기 패드(24)는 상기 반도체메모리장치가 형성되는 칩내에 설치되는 것을 특징으로 하는 반도체메모리장치.
  6. 제 1항에 있어서, 상기 행디코더(20)가 어드레스신호를 디코드하는 헹디코드회로(12)와, 소정의 워드선을 각각 헹디코드회로로 부터의 출력신호레벨에 대응하는 전위로 설정하는 워드선 구동회로(I1,I2)를 구비하여 구성된 것을 특징으로 하는 반도체메모리장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890001785A 1988-02-16 1989-02-16 반도체메모리장치 KR920008247B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63-33436 1988-02-16
JP88-33436 1988-02-16
JP63033436A JPH01208795A (ja) 1988-02-16 1988-02-16 半導体記憶装置

Publications (2)

Publication Number Publication Date
KR890013657A true KR890013657A (ko) 1989-09-25
KR920008247B1 KR920008247B1 (ko) 1992-09-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890001785A KR920008247B1 (ko) 1988-02-16 1989-02-16 반도체메모리장치

Country Status (3)

Country Link
US (1) US4905194A (ko)
JP (1) JPH01208795A (ko)
KR (1) KR920008247B1 (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE101752T1 (de) * 1989-03-31 1994-03-15 Philips Nv Eprom, der eine mehrfache verwendung der bitleitungskontakte ermoeglicht.
US5097444A (en) * 1989-11-29 1992-03-17 Rohm Corporation Tunnel EEPROM with overerase protection
US5015191A (en) * 1990-03-05 1991-05-14 Amp Incorporated Flat IC chip connector
US5117426A (en) * 1990-03-26 1992-05-26 Texas Instruments Incorporated Circuit, device, and method to detect voltage leakage
US5181205A (en) * 1990-04-10 1993-01-19 National Semiconductor Corporation Short circuit detector circuit for memory arrays
JP3237127B2 (ja) * 1991-04-19 2001-12-10 日本電気株式会社 ダイナミックランダムアクセスメモリ装置
JPH05282898A (ja) * 1992-03-30 1993-10-29 Hitachi Ltd 半導体記憶装置
US5420822A (en) * 1992-03-31 1995-05-30 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US5465233A (en) * 1993-05-28 1995-11-07 Sgs-Thomson Microelectronics, Inc. Structure for deselecting broken select lines in memory arrays
US5440516A (en) * 1994-01-27 1995-08-08 Sgs-Thomson Microelectronics, Inc. Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same
US5619460A (en) * 1995-06-07 1997-04-08 International Business Machines Corporation Method of testing a random access memory
JP3250520B2 (ja) * 1998-05-15 2002-01-28 日本電気株式会社 ラインテスト回路およびラインテスト方法
JP3248497B2 (ja) * 1998-10-29 2002-01-21 日本電気株式会社 半導体記憶装置
JP3911440B2 (ja) * 2002-05-13 2007-05-09 松下電器産業株式会社 半導体記憶装置
US8891285B2 (en) 2011-06-10 2014-11-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224199A (ja) * 1984-04-20 1985-11-08 Fujitsu Ltd 半導体記憶装置
EP0195839B1 (en) * 1985-03-29 1989-08-09 Ibm Deutschland Gmbh Stability testing of semiconductor memories
JPS61289600A (ja) * 1985-06-17 1986-12-19 Fujitsu Ltd 半導体記憶装置
JPS62114200A (ja) * 1985-11-13 1987-05-25 Mitsubishi Electric Corp 半導体メモリ装置
JPS62128099A (ja) * 1985-11-28 1987-06-10 Fujitsu Ltd ワンタイムｒｏｍの試験回路
US4718042A (en) * 1985-12-23 1988-01-05 Ncr Corporation Non-destructive method and circuit to determine the programmability of a one time programmable device
JPS62177799A (ja) * 1986-01-30 1987-08-04 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
KR920008247B1 (ko) 1992-09-25
JPH01208795A (ja) 1989-08-22
US4905194A (en) 1990-02-27

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