ATE101752T1 - Eprom, der eine mehrfache verwendung der bitleitungskontakte ermoeglicht. - Google Patents
Eprom, der eine mehrfache verwendung der bitleitungskontakte ermoeglicht.Info
- Publication number
- ATE101752T1 ATE101752T1 AT89200830T AT89200830T ATE101752T1 AT E101752 T1 ATE101752 T1 AT E101752T1 AT 89200830 T AT89200830 T AT 89200830T AT 89200830 T AT89200830 T AT 89200830T AT E101752 T1 ATE101752 T1 AT E101752T1
- Authority
- AT
- Austria
- Prior art keywords
- row
- region
- bit line
- transistors
- injector
- Prior art date
Links
- 239000000758 substrate Substances 0.000 abstract 2
- 230000001427 coherent effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0491—Virtual ground arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP89200830A EP0389693B1 (de) | 1989-03-31 | 1989-03-31 | EPROM, der eine mehrfache Verwendung der Bitleitungskontakte ermöglicht |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE101752T1 true ATE101752T1 (de) | 1994-03-15 |
Family
ID=8202352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT89200830T ATE101752T1 (de) | 1989-03-31 | 1989-03-31 | Eprom, der eine mehrfache verwendung der bitleitungskontakte ermoeglicht. |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5017978A (de) |
| EP (1) | EP0389693B1 (de) |
| JP (1) | JP2967108B2 (de) |
| KR (1) | KR0155375B1 (de) |
| AT (1) | ATE101752T1 (de) |
| DE (1) | DE68913190T2 (de) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2624864B2 (ja) * | 1990-02-28 | 1997-06-25 | 株式会社東芝 | 不揮発性半導体メモリ |
| US5358887A (en) * | 1993-11-26 | 1994-10-25 | United Microelectronics Corporation | Ulsi mask ROM structure and method of manufacture |
| US5949704A (en) * | 1996-09-10 | 1999-09-07 | Macronix International Co., Ltd. | Stacked read-only memory |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4112509A (en) * | 1976-12-27 | 1978-09-05 | Texas Instruments Incorporated | Electrically alterable floating gate semiconductor memory device |
| US4184207A (en) * | 1978-01-27 | 1980-01-15 | Texas Instruments Incorporated | High density floating gate electrically programmable ROM |
| US4281397A (en) * | 1979-10-29 | 1981-07-28 | Texas Instruments Incorporated | Virtual ground MOS EPROM or ROM matrix |
| US4334292A (en) * | 1980-05-27 | 1982-06-08 | International Business Machines Corp. | Low voltage electrically erasable programmable read only memory |
| EP0133667A3 (en) * | 1983-08-12 | 1987-08-26 | American Microsystems, Incorporated | High coupling ratio dense electrically erasable programmable read-only memory |
| JPS60140600A (ja) * | 1983-12-28 | 1985-07-25 | Oki Electric Ind Co Ltd | 不揮発性メモリ装置 |
| FR2604022B1 (fr) * | 1986-09-16 | 1992-09-11 | Eurotechnique Sa | Memoire non volatile a grille flottante sans oxyde epais |
| US4769788A (en) * | 1986-09-22 | 1988-09-06 | Ncr Corporation | Shared line direct write nonvolatile memory cell array |
| JPS63252481A (ja) * | 1987-04-09 | 1988-10-19 | Toshiba Corp | 不揮発性半導体メモリ |
| JPH01208795A (ja) * | 1988-02-16 | 1989-08-22 | Toshiba Corp | 半導体記憶装置 |
| US4912676A (en) * | 1988-08-09 | 1990-03-27 | Texas Instruments, Incorporated | Erasable programmable memory |
-
1989
- 1989-03-31 AT AT89200830T patent/ATE101752T1/de not_active IP Right Cessation
- 1989-03-31 DE DE68913190T patent/DE68913190T2/de not_active Expired - Fee Related
- 1989-03-31 EP EP89200830A patent/EP0389693B1/de not_active Expired - Lifetime
-
1990
- 1990-03-22 US US07/497,953 patent/US5017978A/en not_active Expired - Lifetime
- 1990-03-28 KR KR1019900004152A patent/KR0155375B1/ko not_active Expired - Fee Related
- 1990-03-30 JP JP8141590A patent/JP2967108B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE68913190T2 (de) | 1994-08-04 |
| US5017978A (en) | 1991-05-21 |
| EP0389693A1 (de) | 1990-10-03 |
| DE68913190D1 (de) | 1994-03-24 |
| KR900015153A (ko) | 1990-10-26 |
| JPH02294068A (ja) | 1990-12-05 |
| KR0155375B1 (ko) | 1998-12-01 |
| EP0389693B1 (de) | 1994-02-16 |
| JP2967108B2 (ja) | 1999-10-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |