KR910016072A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR910016072A
KR910016072A KR1019910002225A KR910002225A KR910016072A KR 910016072 A KR910016072 A KR 910016072A KR 1019910002225 A KR1019910002225 A KR 1019910002225A KR 910002225 A KR910002225 A KR 910002225A KR 910016072 A KR910016072 A KR 910016072A
Authority
KR
South Korea
Prior art keywords
semiconductor device
interconnections
bent
arrangement interval
wirings
Prior art date
Application number
KR1019910002225A
Other languages
English (en)
Other versions
KR930009017B1 (ko
Inventor
히데노리 스즈키
사토시 야마노
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR910016072A publication Critical patent/KR910016072A/ko
Application granted granted Critical
Publication of KR930009017B1 publication Critical patent/KR930009017B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 1실시예에 따른 반도체장치의 패턴평면도, 제 2 도는 본 발명의 1실시예에 따른 반도체장치의 패턴평면도의 일부단면도.

Claims (2)

  1. 절연층(5)상에 소정의 간격을 유지하며 일정한 방향으로 연장되어 배치되고, 굴곡부(2)를 경계로 상기와는 다른 방향으로 연장되어 배치된 복수의 배선(1)과, 이 배선(1)상을 포함한 전면에 퇴적된 CVD막(3)이 구비되고, 상기 굴곡부(2)에서 절곡된 후의 상기 복수의 각 배선의 배치간격(λ2)이 절곡되기전의 상기 복수의 각 배선의 배치간격(λ1)보다도 넓어지도록 구성되어 있는 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 배치간격이 넓은 각 배선상에 위치하는 상기 CVD막의 두께를 a, 배선간격이 넓은 각 배선상호의간격을 λ로 했을 때, λ가 a의 약 1.8배 이상이 되도록 설정되어 있는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910002225A 1990-02-14 1991-02-09 반도체장치 KR930009017B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2031488A JPH06105710B2 (ja) 1990-02-14 1990-02-14 半導体装置
JP02-031488 1990-02-14
JP90-031488 1990-02-14

Publications (2)

Publication Number Publication Date
KR910016072A true KR910016072A (ko) 1991-09-30
KR930009017B1 KR930009017B1 (ko) 1993-09-18

Family

ID=12332657

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910002225A KR930009017B1 (ko) 1990-02-14 1991-02-09 반도체장치

Country Status (4)

Country Link
EP (1) EP0442491B1 (ko)
JP (1) JPH06105710B2 (ko)
KR (1) KR930009017B1 (ko)
DE (1) DE69114539T2 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0851159A (ja) * 1994-08-05 1996-02-20 Mitsubishi Electric Corp 半導体集積回路
DE19530951C2 (de) * 1995-08-23 1997-09-11 Bosch Gmbh Robert Verfahren zur Anordnung von Leiterbahnen auf der Oberfläche von Halbleiterbauelementen
DE19531651C2 (de) * 1995-08-29 2001-09-27 Bosch Gmbh Robert Verfahren zur Anordnung von Leiterbahnen auf der Oberfläche eines Halbleiterbauelements
WO2000070672A1 (de) * 1999-05-18 2000-11-23 Infineon Technologies Ag Ausgestaltung einer ecke einer in damaszener-technologie auf einem substrat hergestellten elektrischen leiterbahn aus insbesondere kupfer
JP5411436B2 (ja) * 2008-03-04 2014-02-12 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 集積回路及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364339A (ja) * 1986-09-03 1988-03-22 Mitsubishi Electric Corp 半導体装置の製造方法
JPS63111644A (ja) * 1986-10-30 1988-05-16 Toshiba Corp 半導体装置の製造方法
JPS6428941A (en) * 1987-07-24 1989-01-31 Konishiroku Photo Ind Integrated circuit device

Also Published As

Publication number Publication date
JPH03236239A (ja) 1991-10-22
DE69114539D1 (de) 1995-12-21
EP0442491A2 (en) 1991-08-21
EP0442491A3 (en) 1991-11-13
EP0442491B1 (en) 1995-11-15
JPH06105710B2 (ja) 1994-12-21
DE69114539T2 (de) 1996-05-02
KR930009017B1 (ko) 1993-09-18

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