KR910014996A - 집적회로 땜납 다이-접착 설계 및 방법 - Google Patents

집적회로 땜납 다이-접착 설계 및 방법 Download PDF

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KR910014996A
KR910014996A KR1019910000227A KR910000227A KR910014996A KR 910014996 A KR910014996 A KR 910014996A KR 1019910000227 A KR1019910000227 A KR 1019910000227A KR 910000227 A KR910000227 A KR 910000227A KR 910014996 A KR910014996 A KR 910014996A
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layer
conductive material
semiconductor device
major surface
semiconductor wafer
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KR1019910000227A
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KR940008380B1 (ko
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제이. 쉐넌 마이클
씨. 터니쥐 랜돌프
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완다 케이. 덴슨-로우
휴우즈 에어크라프트 캄파니
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Publication of KR910014996A publication Critical patent/KR910014996A/ko
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Abstract

내용 없음

Description

집적회로 땜납 다이-접착 설계 및 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 양호한 제1실시예에 따른 땜납/비아 인터페이스(solder/via interface)를 우선적으로 “탈수분”시기기 위한 개선된 MMIC 배면 금속화 시스템의 사시도.

Claims (21)

  1. 반도체 디아비수와 기판 사이에 전기적 상호접속을 제공하기 위해 기판에 금속적으로 접착되기에 적합한 반도체 디바이스에 있어서, 제1주요 표면 및 제2주요 표면을 갖고, 상기 제2주요 표면이 상기 웨이퍼를 통해 상기 제1주요 표면으로 연장되는 최소한 한개의 비아를 정하는 반도체 웨이퍼, 상기 반도체 웨이퍼의 상기 제2주요 표면상의 접지판 금속화층, 땜납 물질과 상기 비아의 접착을 방지하기 위해 최소한 상기 비아 내의 상기 접지판 금속화층 상에 형성된 제1층 수단, 및 상기 반도체 웨이퍼를 상기 기판에 집착시키기 위해 상기 제1층 수단상에 형성된 제2층 수단을 포함하는 것을 특징으로 하는 반도체 디바이스.
  2. 제1항에 있어서, 상기 제1층 수단이 상기 비아의 표면 상에 형성된 제1전도성 물질층을 포함하고, 상기 제1전도성 물질이 상기 땝납 물질을 습식시키는 것을 방지하는 것을 특징으로 하는 반도체 디바이스.
  3. 제2항에 있어서, 상기 제1전도성 물질이 비교적 얇은 전기도금된 닉켈층이고, 상기 닉켈층이 상기 반도체 웨이퍼의 상기 접지판 금속화층 및 상기 비아의 상기 표면 상에 증착되는 것을 특징으로 하는 반도체 디바이스.
  4. 제3항에 있어서, 상기 제2층 수단이 상기 제1전도성 물질층 상에 형성된 제2전도성 물질층을 포함하고, 상기 제2전도성 물질층이 상기 비아의 주변 에지에서 종결되는 것을 특징으로 하는 반도체 디바이스.
  5. 제4항에 있어서, 상기 제2전도성 물질이 상기 닉컬층에 증착되어 상기 닉켈층과 접촉하는 비교적 얇은 금속화된 금속층이고, 상기 금속화된 금층이 상기 비아의 주변 에지에 종결되는 것을 특징으로 하는 반도체 디바이스.
  6. 제5항에 있어서, 상기 반도체 디바이스가 칼륨 비소화물로 제조되고, 상기 땜납 물질이 상기 비아내의 상기 닉켈층상의 거의 습식이 되지 않는 전기 전도성 금속 합금인 것을 특징으로 하는 반도체 디바이스.
  7. 제6항에 있어서, 상기 금속화된 금층상에 형성되어 상기 금속화된 금층과 접촉하는 상기 땜납 물질층을 더 포함하는 것을 특징으로 하는 반도체 디바이스.
  8. 기판에 접착되기에 적합한 반도체 디바이스에 있어서, 반도체 웨이퍼, 상기 반도체 웨이퍼의 제1표면에 배치된 집적 회로, 상기 반도체 웨이퍼를 통해 제2표면에서 부터 상기 제1표면으로 횡으로 연장되는 최소한 한개의 비아, 및 상기 제1전도성 물질이 상기 직접 회로와 인터페이스되도록 상기 비아의 표면 상에 증착되는 상기 제1전도성 물질 및 상기 제1전도성 물질에 인접한 상기 반도체 웨이퍼 제2표면 상에 증착되고 상기 비아의 외부 에지에서 종결되는 제2전도성 물질을 갖는 상기 반도체 웨이퍼 제2표면 상에 제공되는 접지판층을 포함하고, 상기 제1전도성 물질이 상기 비아의 상기 표면과 접촉되는 경우 땜납 물질의 습식을 방지하고, 상기 제2전도성 물질이 상기 반도체 웨이퍼를 상기 기판에 상호접속시키기 위해서 상기 접지판층에 대해 상기 접지 물질의 습식을 허용하는 것을 특징으로 하는 반도체 디바이스.
  9. 제8항에 있어서, 상기 제1전도성 물질이 닉켈로 제조된 장벽판이 것을 특징으로 하는 반도체 디바이스.
  10. 제9항에 있어서, 상기 닉켈 장벽판이 상기 웨이퍼의 상기 제2표면 및 상기 비아의 상기 표면상의 연속층으로서 전기 도금되는 것을 특징으로 하는 반도체 디바이스.
  11. 제8항에 있어서, 상기 제1전도성 물질이 상기 반도체 웨이퍼의 상기 제2표면 상에 증착된 비교적 얇은 금속화층 및 상기 금속화층 상에 증착되어 상기 금속화층과 접촉하는 비교적 얇은 닉켈 장벽층을 포함하는 것을 특징으로 하는 반도체 디바이스.
  12. 제8항에 있어서, 상기 제2전도성 물질이 비교적 얇은 전기도금된 금층인 것을 특징으로 하는 반도체 디바이스.
  13. 제8항에 있어서, 상기 반도체 웨이퍼가 갈륨 비소화물이고, 상기 반도체 디바이스가 마이크로파 집적 회로 디바이스인 것을 특징으로 하는 반도체 디바이스.
  14. 반도체 디바이스를 제조하는 방법에 있어서, (a)제 1주요 표면 및 제2 주요 표면을 갖는 반도체 웨이퍼를 제공하는 단계, (b)상기 반도체 웨이퍼를 통해 상기 제2표면에서부터 상기 제1표면으로 거의 횡으로 연장되는 최소한 한개의 비아를 형성하는 단계, (c) 상기 제1주요 표면에 전기 회로를 제조하는 단계, (d)상기 비아 및 상기 제2주요 표면과 접촉하고, 상기 전기 회로와 인터페이스된 상기 비아내에 있는 제1전도성 물질층을 증착시키는 단계, (e) 상기 비아내의 제1전도성층을 마스크하는 단계, 및 (f) 제2 전도성 물질을 상기 전도성 물질층상에 증착시키는 단계를 포함하고, 상기 반도체 디바이스를 기판에 접착시키기 위해서 상기 제1전도성층이 땜납 물질의 접착을 방지하고, 상기 제2전도성층이 상기 땜납 물질의 접착을 촉진하는 것을 특징으로 하는 방법.
  15. 제14항에 있어서, 상기 (g)상기 제2 전도성층과 접촉하게 상기 제2전도성층상에 상기 땜납 물질층을 증착시는 단계를 포함하는 것을 특징으로 하는 반도체 디바이스.
  16. 제14항에 있어서 상기 (b)단계가 상기 반도체 웨이퍼를 통해 다수의 비아들을 에칭하는 단계를 포함하는 것을 특징으로 하는 방법.
  17. 제14항에 있어서, 상기 (a) 단계가 갈륨 비소화물 반도체 웨이퍼를 제공하는 단계를 포함하는 것을 특징으로 하는 방법.
  18. 제17항에 있어서, 상기 (c)단계가, 최소한 상기 갈륨 비소화물 웨이퍼의 상기 제1주요 표면 상의 마이크로파 주파수 스펙트럼 내에서 동작할 수 있는 전기 집적회로를 제고하는 단계를 포함하는 것을 특징으로 하는 방법.
  19. 제14항에 있어서, 상기 (d) 단계가 연속적이고 비교적 얇은 낙켈층을 상기 웨이퍼의 상기 제2 주요 표면 상에 증착시키는 단계를 포함하고, 상기 닉켈층이 상기 땜납 물질의 습식을 방지하는 것을 특징으로 하는 방법.
  20. 제14항에 있어서, 상기(f) 단계가 상기 비아의 주변부에서 종결되는 상기 제2주요 표면상에 비교적 얇은 금층을 증착시키는 단계를 포함하는 것을 특징으로 하는 방법.
  21. 반도체 디바이스를 기판에 금속적으로 접착시키는 방법에 있어서, (a)제1주요 표면, 제2 주요 표면, 상기 제2 주요 표면에서 부터 상기 제1 주요 표면으로 거의 횡으로 연장되는 최소한 한개의 비아, 상기 제1주요 표면 상의 회로, 및 상기 제2 주요 표면 상에 증착되고 상기 비아 및 상기 제2주요 표면과 접촉한 제1전도성 물질 및 상기 제1 전도성 물질 상에 증착되고 상기 비아의 주변부에서 종결되는 제2 전도성 물질을 포함하는 접지판층을 갖는 반도체 웨이퍼를 제공하는 단계, (b)상기 반도체 웨이퍼의 상기 제2 전도성 물질에 납땜되기에 적합한 금속화된 표면을 갖는 기판을 제공하는 단계, (c) 상기 반도체 웨이퍼와 상기 기판 사이에 전도성 납땜 물질을 증착시키는 단계, 및 (d) 상기 납땜 물질이 상기 제2전도성 물질 및 상기 기판의 상기 금속화된 표면을 습식시키도록 상기 납땜 물질을 가열함으로써 그 사이에 접착을 형성하는 단계를 포함하고, 상기 반도체 기판을 상기 기판에 접착시키기 위해서 상기 제1전도성층이 상기 땜납 물질의 습식을 방지하고, 상기 제2 전도성 층이 상기 땜납 물질의 습식을 촉진하는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910000227A 1990-01-10 1991-01-09 집적 회로 땜납 다이-접착 설계 KR940008380B1 (ko)

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US07/463,186 US5027189A (en) 1990-01-10 1990-01-10 Integrated circuit solder die-attach design and method

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