KR900013625A - IC디바이스의 리플로(reflow)본딩용 범프구조 - Google Patents

IC디바이스의 리플로(reflow)본딩용 범프구조 Download PDF

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KR900013625A
KR900013625A KR1019900001527A KR900001527A KR900013625A KR 900013625 A KR900013625 A KR 900013625A KR 1019900001527 A KR1019900001527 A KR 1019900001527A KR 900001527 A KR900001527 A KR 900001527A KR 900013625 A KR900013625 A KR 900013625A
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gold
semiconductor device
metal
bump
tape
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KR0166967B1 (ko
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제이. 매도우 란잔
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존 지.웨브
내셔널 세미컨덕터 코포레이션
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Abstract

내용 없음

Description

IC디바이스의 리플로(refiow)본딩용 범프구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본딩 패드를 도시하는 웨이퍼 부분 단면도.
제 2도는 금속층을 연속적으로 피복한 제 1도의 웨이퍼 부분에 대한 도시도.
제 3도는 본딩 패드의 중심부상에 개구부를 지니는 포토레지스트로 피복한 제 2도의 웨이퍼 부분에 대한 도시도.
제 4도는 포토레지스트 개구부내에 전기도금된 금층, 주석 및 금층을 지니는 제 3도의 웨이퍼 부분에 대한 도시도.
제 5도는 납땜할 준비가 되어있는 구리 핑거(finger)를 지닌 제 4도의 웨이퍼 부분에 대한 도시도.
제 6도는 금-주석 공정(共晶) 땜납을 사용하여 금 범프(bump)로 납땜된 구리 핑거에 대한 도시도.

Claims (11)

  1. 반도체 디바이스상에 위치하며 외부 표면을 지니는 금속 범프, 조립 테이프와 연관되는 금속 핑거, 상기 테이프 핑거를 상기 범프의 외부 표면에 접합시킴에 있어 상기 본드형 반도체 디바이스에 있는 금속 주석을 완전히 없애는 금-주석 공정 땜납을 포함하는 테이프 조립 본드형 반도체 디바이스.
  2. 제 1항에 있어서, 상기 범프는 금으로 이루어지며 상기 금속형태는 구리로 이루어지는 테이프 조립 본드형 반도체 디바이스.
  3. 제 2항에 있어서, 상기 금 범프는 상기 반도체 디바이스의 알루미늄 본딩 패드 상부에 위치하여 있는 테이프 조립 본드형 반도체 디바이스.
  4. 제 3항에 있어서, 상기 알루이늄 본딩 패드와 상기 금 범프사이에 위치한 알루미늄층, 니켈-바나듐 합금층 및 금층을 포함하는 테이프 조립 본드형 반도체 디바이스.
  5. 본드형 반도체 디바이스 표면에 위치한 알루미늄 본딩 패드를 지니는 본드형 반도체 디바이스를 제조하는 방법으로서, 상기 본딩 패드와 일치하여 금속 범프를 형성하는 단계, 주석층을 상기 금속 범프의 상부표면에 증착하는 단계, 금층을 상기 주석층 상부에 중착하는 단계, 금이 피복된 구리 핑거를 상기 금속범프의 금층에 대항하여 압착하는 단계, 상기 조립체를 금-주석 공정용융 온도보다 높이 가열함으로서 상기 주석이 상기 구리 핑거 및 상기 금속 범프를 접촉시키는 공정 액상을 형성하도록 상기 금과 화합하는 단계, 상기 조립체를 냉각시킴으로써 상기 구리 핑거가 상기 금속 범프에 납땜되는 단계를 포함하는 테이프 조립 본드형 반도체 디바이스 제조방법.
  6. 제 5항에 있어서, 증착된 주석양은 상기 가열단계 다음 상기 주석이 공정 합급으로 완전히 변환되도록 제어되는 테이프 조립 본드형 반도체 디바이스 제조방법.
  7. 제 5항에 있어서, 상기 금속 범프가 금으로 이루어지는 테이프 조립 본드형 반도체 디바이스 제조방법.
  8. 제 5항에 있어서, 상기 금속 범프가 이범프상의 외부금층을 지닌 구리로 이루어지는 테이프 조립 본드형 반도체 디바이스 제조방법.
  9. 제 5항에 있어서, 상기 범프 형성 단계는 도전성막으로 상기 반도체를 피복함으로써 이행되며 상기 범프는 마스크의 개구를 통해 전기도금함으로써 제조되는 테이프 조립 본드형 반도체 디바이스 제조방법.
  10. 제 9항에 있어서, 상기 도전성막은 제 1부착금속층, 제 2방벽 금속층 및 제 3도전성 부식방지 금속층을 포함하는 3개의 층으로 이루어지는 테이프 조립 본드형 반도체 디바이스 제조방법.
  11. 제 10항에 있어서, 상기 층 각각이 연속적인 진공 증착을 이루게하는 진공 챔버에서 연속적으로 증착된 알루미늄, 니켈-바나듐 합금 및 금으로 이루어지는 테이프 조립 본드형 반도체 디바이스 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900001527A 1989-02-09 1990-02-08 테이프 조립체 본딩용 반도체 디바이스 및 그 제조방법 KR0166967B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US308,704 1981-10-05
US07/308,704 US4922322A (en) 1989-02-09 1989-02-09 Bump structure for reflow bonding of IC devices
US308704 1989-02-09

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Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021300A (en) * 1989-09-05 1991-06-04 Raytheon Company Solder back contact
JPH03233972A (ja) * 1990-02-08 1991-10-17 Matsushita Electron Corp 半導体装置用電極およびその製造方法
US5121871A (en) * 1990-04-20 1992-06-16 The United States Of America As Represented By The United States Department Of Energy Solder extrusion pressure bonding process and bonded products produced thereby
AU7954491A (en) * 1990-05-14 1991-12-10 Richard Lee Schendelman Interdigitated trans-die lead construction and method of construction for maximizing population density of chip-on-board construction
JP2540652B2 (ja) * 1990-06-01 1996-10-09 株式会社東芝 半導体装置
US5556810A (en) * 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
US5130275A (en) * 1990-07-02 1992-07-14 Digital Equipment Corp. Post fabrication processing of semiconductor chips
DE4025622A1 (de) * 1990-08-13 1992-02-20 Siemens Ag Anschlusskontakthoecker und verfahren zu dessen herstellung
JPH0574824A (ja) * 1991-08-26 1993-03-26 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
US5197654A (en) * 1991-11-15 1993-03-30 Avishay Katz Bonding method using solder composed of multiple alternating gold and tin layers
USH1934H1 (en) 1992-05-01 2001-01-02 Lucent Technologies, Inc. Gold-tin solder suitable for self-aligning applications
JP3141364B2 (ja) * 1992-05-06 2001-03-05 住友電気工業株式会社 半導体チップ
US5346857A (en) * 1992-09-28 1994-09-13 Motorola, Inc. Method for forming a flip-chip bond from a gold-tin eutectic
US5821627A (en) * 1993-03-11 1998-10-13 Kabushiki Kaisha Toshiba Electronic circuit device
US5508229A (en) * 1994-05-24 1996-04-16 National Semiconductor Corporation Method for forming solder bumps in semiconductor devices
US5918794A (en) * 1995-12-28 1999-07-06 Lucent Technologies Inc. Solder bonding of dense arrays of microminiature contact pads
US6137690A (en) * 1997-08-18 2000-10-24 Motorola Electronic assembly
JP3420917B2 (ja) 1997-09-08 2003-06-30 富士通株式会社 半導体装置
US6157079A (en) * 1997-11-10 2000-12-05 Citizen Watch Co., Ltd Semiconductor device with a bump including a bump electrode film covering a projecting photoresist
US6184581B1 (en) * 1997-11-24 2001-02-06 Delco Electronics Corporation Solder bump input/output pad for a surface mount circuit device
SG77652A1 (en) 1998-03-18 2001-01-16 Hitachi Cable Semiconductor device lead-patterning substrate and electronics device and method for fabricating same
JP3553413B2 (ja) * 1999-04-26 2004-08-11 富士通株式会社 半導体装置の製造方法
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
US6737353B2 (en) * 2001-06-19 2004-05-18 Advanced Semiconductor Engineering, Inc. Semiconductor device having bump electrodes
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
TW530402B (en) * 2002-03-01 2003-05-01 Advanced Semiconductor Eng Bump process
US6642158B1 (en) * 2002-09-23 2003-11-04 Intel Corporation Photo-thermal induced diffusion
US7088004B2 (en) * 2002-11-27 2006-08-08 International Rectifier Corporation Flip-chip device having conductive connectors
US7455787B2 (en) 2003-08-01 2008-11-25 Sunpower Corporation Etching of solar cell materials
US7109583B2 (en) * 2004-05-06 2006-09-19 Endwave Corporation Mounting with auxiliary bumps
DE102004023752B4 (de) * 2004-05-11 2006-08-24 Infineon Technologies Ag Verfahren zur Vermeidung der Verringerung der Dicke der Umverdrahtung
KR100660889B1 (ko) 2005-11-14 2006-12-26 삼성전자주식회사 반도체 패키지의 위스커 결함을 억제하는 인쇄회로기판 및이를 이용한 반도체 패키지 탑재방법
US7919859B2 (en) * 2007-03-23 2011-04-05 Intel Corporation Copper die bumps with electromigration cap and plated solder
US10231344B2 (en) * 2007-05-18 2019-03-12 Applied Nanotech Holdings, Inc. Metallic ink
US8404160B2 (en) * 2007-05-18 2013-03-26 Applied Nanotech Holdings, Inc. Metallic ink
US8506849B2 (en) * 2008-03-05 2013-08-13 Applied Nanotech Holdings, Inc. Additives and modifiers for solvent- and water-based metallic conductive inks
US20090286383A1 (en) * 2008-05-15 2009-11-19 Applied Nanotech Holdings, Inc. Treatment of whiskers
US9730333B2 (en) * 2008-05-15 2017-08-08 Applied Nanotech Holdings, Inc. Photo-curing process for metallic inks
US20100000762A1 (en) * 2008-07-02 2010-01-07 Applied Nanotech Holdings, Inc. Metallic pastes and inks
JP5740389B2 (ja) 2009-03-27 2015-06-24 アプライド・ナノテック・ホールディングス・インコーポレーテッド 光焼結及び／またはレーザー焼結を強化するためのバッファ層
US8422197B2 (en) * 2009-07-15 2013-04-16 Applied Nanotech Holdings, Inc. Applying optical energy to nanoparticles to produce a specified nanostructure
US9598776B2 (en) 2012-07-09 2017-03-21 Pen Inc. Photosintering of micron-sized copper particles
US20150171039A1 (en) * 2013-12-13 2015-06-18 Chipmos Technologies Inc. Redistribution layer alloy structure and manufacturing method thereof
US9136237B2 (en) * 2013-12-17 2015-09-15 Oracle International Corporation Electroplated solder for high-temperature interconnect

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3141226A (en) * 1961-09-27 1964-07-21 Hughes Aircraft Co Semiconductor electrode attachment
US3874072A (en) * 1972-03-27 1975-04-01 Signetics Corp Semiconductor structure with bumps and method for making the same
US4005472A (en) * 1975-05-19 1977-01-25 National Semiconductor Corporation Method for gold plating of metallic layers on semiconductive devices
JPS5459080A (en) * 1977-10-19 1979-05-12 Nec Corp Semiconductor device
US4418857A (en) * 1980-12-31 1983-12-06 International Business Machines Corp. High melting point process for Au:Sn:80:20 brazing alloy for chip carriers
JPS57152147A (en) * 1981-03-16 1982-09-20 Matsushita Electric Ind Co Ltd Formation of metal projection on metal lead
JPS57188848A (en) * 1981-05-18 1982-11-19 Hitachi Ltd Circuit element
JPS592352A (ja) * 1982-06-28 1984-01-07 Toshiba Corp 半導体装置の製造方法
US4518112A (en) * 1982-12-30 1985-05-21 International Business Machines Corporation Process for controlled braze joining of electronic packaging elements

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DE69026631D1 (de) 1996-05-30
JPH02246335A (ja) 1990-10-02
KR0166967B1 (ko) 1999-01-15
EP0382080A3 (en) 1991-07-03
US4922322A (en) 1990-05-01
EP0382080B1 (en) 1996-04-24
EP0382080A2 (en) 1990-08-16

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