JPH03233972A - 半導体装置用電極およびその製造方法 - Google Patents
半導体装置用電極およびその製造方法Info
- Publication number
- JPH03233972A JPH03233972A JP2029029A JP2902990A JPH03233972A JP H03233972 A JPH03233972 A JP H03233972A JP 2029029 A JP2029029 A JP 2029029A JP 2902990 A JP2902990 A JP 2902990A JP H03233972 A JPH03233972 A JP H03233972A
- Authority
- JP
- Japan
- Prior art keywords
- film
- aluminum
- aluminum film
- electrode
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 54
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 54
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 14
- 239000012298 atmosphere Substances 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000007738 vacuum evaporation Methods 0.000 claims description 4
- 238000003746 solid phase reaction Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000011282 treatment Methods 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 17
- 239000000853 adhesive Substances 0.000 abstract description 7
- 230000001070 adhesive effect Effects 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 abstract 1
- 239000011261 inert gas Substances 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 239000007787 solid Substances 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 239000010410 layer Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
Classifications
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
産業上の利用分野
本発明は銅線を用いて半導体素子と外部リードを結線さ
せるのに適した半導体素子側に形成された半導体装置用
電極とその製造方法に関するものである。
せるのに適した半導体素子側に形成された半導体装置用
電極とその製造方法に関するものである。
従来の技術
半導体装置において、半導体素子と外部リードとを接続
するために、金線やアルミニウム線が広く用いられてき
たが、近年、金線やアルミニウム線に代わる細線として
銅線が注目され実用化されつつある。また、半導体素子
側の電極としてはアルミニウム膜が広く用いられている
が、近年、アルミニウムに銅やシリコンを添加するアル
ミニウム単層膜やまたはアルミニウム、バナジウム、ア
ルミニウムを順次形成する三層構造の電極も製造され信
頼性向上が図られている。
するために、金線やアルミニウム線が広く用いられてき
たが、近年、金線やアルミニウム線に代わる細線として
銅線が注目され実用化されつつある。また、半導体素子
側の電極としてはアルミニウム膜が広く用いられている
が、近年、アルミニウムに銅やシリコンを添加するアル
ミニウム単層膜やまたはアルミニウム、バナジウム、ア
ルミニウムを順次形成する三層構造の電極も製造され信
頼性向上が図られている。
発明が解決しようとする課題
銅線を用い、超音波熱圧着法によって、アルミニウム膜
を電極とした半導体素子と外部リードを結線する際、条
件に応じて、二つの断線不良が発生する。すなわち、一
つは接着条件が不充分な場合は鋼線を溶解させて作った
銅ボールとアルミニウム膜との間のはずれを含む接着不
良である。また接着条件が過度の場合は、アルミニウム
膜下の半導体基板を破壊させる不良である。接着条件は
主に接着温度、印加する超音波のパワー、時間および荷
重によって決まる。銅はアルミニウムに比較して硬度が
高いため、銅ボールを変形させてアルミニウム膜に接着
する際、金線やアルミニウム線を用いて接着する時に比
べて大きな接着のためのパワーと荷重を必要とする。そ
のため、接着条件が不充分であるとはずれによる断線と
なり、過度であると半導体基板にダメージを与え、半導
体基板を破壊させ、断線不良となってしまう。前記接着
不良と半導体基板の破壊をおこさない中間の条件が最適
条件である。しかし、アルミニウム膜を電極とした場合
、この最適接着領域が狭く、接着条件の少しのばらつき
によって、接着不良あるいは、半導体基板の破壊の両不
良を発生させて半導体装置として致命的な断線不良とな
ってしまう。本発明は、銅線を用いて接着する際に適し
た半導体装置用電極およびその製造方法を提案するもの
で、それによって接着条件に対して広い最適接着領域を
確保するものである。
を電極とした半導体素子と外部リードを結線する際、条
件に応じて、二つの断線不良が発生する。すなわち、一
つは接着条件が不充分な場合は鋼線を溶解させて作った
銅ボールとアルミニウム膜との間のはずれを含む接着不
良である。また接着条件が過度の場合は、アルミニウム
膜下の半導体基板を破壊させる不良である。接着条件は
主に接着温度、印加する超音波のパワー、時間および荷
重によって決まる。銅はアルミニウムに比較して硬度が
高いため、銅ボールを変形させてアルミニウム膜に接着
する際、金線やアルミニウム線を用いて接着する時に比
べて大きな接着のためのパワーと荷重を必要とする。そ
のため、接着条件が不充分であるとはずれによる断線と
なり、過度であると半導体基板にダメージを与え、半導
体基板を破壊させ、断線不良となってしまう。前記接着
不良と半導体基板の破壊をおこさない中間の条件が最適
条件である。しかし、アルミニウム膜を電極とした場合
、この最適接着領域が狭く、接着条件の少しのばらつき
によって、接着不良あるいは、半導体基板の破壊の両不
良を発生させて半導体装置として致命的な断線不良とな
ってしまう。本発明は、銅線を用いて接着する際に適し
た半導体装置用電極およびその製造方法を提案するもの
で、それによって接着条件に対して広い最適接着領域を
確保するものである。
課題を解決するための手段
本発明の半導体用電極は、半導体素子側の電極を半導体
基板と接触する第1のアルミニウム膜。
基板と接触する第1のアルミニウム膜。
つづいてAe 3N i膜とし、この上に銅と接触する
第2のアルミニウム膜が形成された三層構造とするもの
である。そして、この構造の電極を得る製造方法は半導
体基板上に真空蒸着によって順次、第1のアルミニウム
膜と、ニッケル膜、および第2のアルミニウム膜を形成
のち、不活性雰囲気中で450℃から550℃の温度範
囲で30分間程熱処理し、第1と第2のアルミニウム膜
にはさまれたニッケル膜を固相反応によってA(!3N
i膜とするものである。
第2のアルミニウム膜が形成された三層構造とするもの
である。そして、この構造の電極を得る製造方法は半導
体基板上に真空蒸着によって順次、第1のアルミニウム
膜と、ニッケル膜、および第2のアルミニウム膜を形成
のち、不活性雰囲気中で450℃から550℃の温度範
囲で30分間程熱処理し、第1と第2のアルミニウム膜
にはさまれたニッケル膜を固相反応によってA(!3N
i膜とするものである。
作用
半導体素子側の電極をアルミニウム、 A Q 3 N
i+アルミニウムの三層構造とすることで、銅線を接
着する際の最適接着領域を著しく拡大できる。すなわち
、半導体基板と接触する第1のアルミニウム膜は、半導
体基板との接触抵抗を下げるために、また、硬いAe3
Niと半導体基板との接着時の応力緩和にも効果的であ
る。また、硬度の高いAe3Ni膜層を硬度の低いアル
ミニウム膜ではさむことで銅線を接着する際の接着力に
対して、半導体基板の破壊を緩和させることができる。
i+アルミニウムの三層構造とすることで、銅線を接
着する際の最適接着領域を著しく拡大できる。すなわち
、半導体基板と接触する第1のアルミニウム膜は、半導
体基板との接触抵抗を下げるために、また、硬いAe3
Niと半導体基板との接着時の応力緩和にも効果的であ
る。また、硬度の高いAe3Ni膜層を硬度の低いアル
ミニウム膜ではさむことで銅線を接着する際の接着力に
対して、半導体基板の破壊を緩和させることができる。
さらに銅ボールと接触する第2のアルミニウム膜は、銅
ボールと合金化することによって良好な接着を得ること
ができる。
ボールと合金化することによって良好な接着を得ること
ができる。
実施例
本発明の実施例を図でもって説明する。第1図は本発明
による半導体装置の電極構造を示す断面図である。半導
体装置としてはプレーナ型トランジスタを例にして示す
。半導体基板1の領域内に、ベース領域2およびエミッ
タ領域3を形成したのち、二酸化硅素膜4の一部を除き
、ベース電極とエミッタ電極の形成用窓を形成する。そ
して第1のアルミニウム膜5とニッケル膜6aそして第
2のアルミニウム膜7を真空蒸着で形成したのち、ベー
ス電極とエミッタ電極のみの金属層を残す。しかるのち
・、窒素雰囲気中で500℃の温度で30分間熱処理し
、ニッケルとアルミニウムを固相反応させニッケル膜6
aをAe3Ni膜6bとすることにより半導体装置用電
極が形成される。
による半導体装置の電極構造を示す断面図である。半導
体装置としてはプレーナ型トランジスタを例にして示す
。半導体基板1の領域内に、ベース領域2およびエミッ
タ領域3を形成したのち、二酸化硅素膜4の一部を除き
、ベース電極とエミッタ電極の形成用窓を形成する。そ
して第1のアルミニウム膜5とニッケル膜6aそして第
2のアルミニウム膜7を真空蒸着で形成したのち、ベー
ス電極とエミッタ電極のみの金属層を残す。しかるのち
・、窒素雰囲気中で500℃の温度で30分間熱処理し
、ニッケルとアルミニウムを固相反応させニッケル膜6
aをAe3Ni膜6bとすることにより半導体装置用電
極が形成される。
さらに詳しく説明すると、第1のアルミニウム膜5と第
2のアルミニウム膜7にはさまれたAe:+Ni6bは
まず、半導体基板1に第1のアルミニウム膜5を厚さが
3μ、つづいてニッケル膜6aを厚さが0.5μ、そし
て第2のアルミニウム膜7を厚さが2μになるまで真空
蒸着により形成したのち、不活性雰囲気中で450℃か
ら550℃の温度範囲で約30分間熱処理することによ
り、容易に得られる。しかしながら、第1および第2の
アルミニウム膜は厚み1μ以上に、またニッケル膜の厚
みは0.7μ以下にすることが必要である。なぜならば
、アルミニウム膜に対してニッケル膜が厚すぎると熱処
理によってアルミニウム膜の全部がAC3Niとなって
しまい、直接に半導体基板もしくは、鋼と接触すること
になり、接触抵抗の増大や接着力の低下となってしまう
からである。また、いたずらにニッケル膜に対してアル
ミニウム膜を厚くすることは、真空蒸着に長時間を要し
、またホトエツヂングによる微細加工の精度低下となる
。第1のアルミニウム膜としては1〜4μ、ニッケル膜
は0.2〜0.7μ、第2のアルミニウム膜としては1
〜3μが適当であった。
2のアルミニウム膜7にはさまれたAe:+Ni6bは
まず、半導体基板1に第1のアルミニウム膜5を厚さが
3μ、つづいてニッケル膜6aを厚さが0.5μ、そし
て第2のアルミニウム膜7を厚さが2μになるまで真空
蒸着により形成したのち、不活性雰囲気中で450℃か
ら550℃の温度範囲で約30分間熱処理することによ
り、容易に得られる。しかしながら、第1および第2の
アルミニウム膜は厚み1μ以上に、またニッケル膜の厚
みは0.7μ以下にすることが必要である。なぜならば
、アルミニウム膜に対してニッケル膜が厚すぎると熱処
理によってアルミニウム膜の全部がAC3Niとなって
しまい、直接に半導体基板もしくは、鋼と接触すること
になり、接触抵抗の増大や接着力の低下となってしまう
からである。また、いたずらにニッケル膜に対してアル
ミニウム膜を厚くすることは、真空蒸着に長時間を要し
、またホトエツヂングによる微細加工の精度低下となる
。第1のアルミニウム膜としては1〜4μ、ニッケル膜
は0.2〜0.7μ、第2のアルミニウム膜としては1
〜3μが適当であった。
第2図には第1図に示した半導体素子のエミッタ電極部
の拡大図に銅&’jt 8を結線させた状態を示す。な
お、同一名称には同一番号を付した。銅線8の先端は球
状であったものが、超音波印加と荷重により、変形し第
2のアルミニウム膜7と接する状態を示す。
の拡大図に銅&’jt 8を結線させた状態を示す。な
お、同一名称には同一番号を付した。銅線8の先端は球
状であったものが、超音波印加と荷重により、変形し第
2のアルミニウム膜7と接する状態を示す。
第3図には縦軸に接着強度、横軸に接着条件をとり、そ
の最適接着領域を従来例(アルミニウム膜−層電極)の
場合と本発明による実施例の場合とを比較して示した。
の最適接着領域を従来例(アルミニウム膜−層電極)の
場合と本発明による実施例の場合とを比較して示した。
なお、Aは従来例での最適接着領域、Bは本発明による
最適接着領域である。第3図かられかるように、従来例
では最適接着領域が狭い。
最適接着領域である。第3図かられかるように、従来例
では最適接着領域が狭い。
発明の効果
本発明によれば、接着条件を強くしても半導体基板の破
壊は発生せず、その結果、最適接着領域を広くすること
ができ工業的利用価値大である。
壊は発生せず、その結果、最適接着領域を広くすること
ができ工業的利用価値大である。
第1図は本発明による半導体装置用電極の断面図、第2
図はその電極に鋼線を接着した状態を示す拡大断面図、
第3図は本発明と従来例の場合の最適接着領域を示す図
である。 1・・・・・・半導体基板、2・・・・・・ベース領域
、3・・・・・・エミッタ領域、二酸化硅素膜、5・・
・・・・第1のアルミニウム膜、6a・・・・・・ニッ
ケル膜、6b・・・・・・Ae3Ni膜、7・・・・・
・第2のアルミニウム膜、8・・・・・・M線。
図はその電極に鋼線を接着した状態を示す拡大断面図、
第3図は本発明と従来例の場合の最適接着領域を示す図
である。 1・・・・・・半導体基板、2・・・・・・ベース領域
、3・・・・・・エミッタ領域、二酸化硅素膜、5・・
・・・・第1のアルミニウム膜、6a・・・・・・ニッ
ケル膜、6b・・・・・・Ae3Ni膜、7・・・・・
・第2のアルミニウム膜、8・・・・・・M線。
Claims (2)
- (1)半導体基板上に、第1のアルミニウム膜とAl_
3Ni膜と第2のアルミニウム膜が順次積層された半導
体装置用電極。 - (2)全ての拡散処理が終了した半導体基板上に第1の
アルミニウム膜、ニッケル膜、つづいて第2のアルミニ
ウム膜の三層を真空蒸着で形成した後、不活性雰囲気中
で熱処理を施し、ニッケル膜とアルミニウム膜を固相反
応させて Al_3Niを形成し、前記半導体基板上に第1のアル
ミニウム膜とAl_3Ni膜および第2のアルミニウム
膜の三層構造を形成することを特徴とする半導体装置用
電極の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2029029A JPH03233972A (ja) | 1990-02-08 | 1990-02-08 | 半導体装置用電極およびその製造方法 |
US07/929,472 US5298793A (en) | 1990-02-08 | 1992-08-13 | Semiconductor device including an electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2029029A JPH03233972A (ja) | 1990-02-08 | 1990-02-08 | 半導体装置用電極およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
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JPH03233972A true JPH03233972A (ja) | 1991-10-17 |
Family
ID=12264987
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2029029A Pending JPH03233972A (ja) | 1990-02-08 | 1990-02-08 | 半導体装置用電極およびその製造方法 |
Country Status (2)
Country | Link |
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US (1) | US5298793A (ja) |
JP (1) | JPH03233972A (ja) |
Families Citing this family (16)
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JPH09213943A (ja) * | 1996-01-29 | 1997-08-15 | Mitsubishi Electric Corp | パワーmosfetの製造方法 |
GB9624477D0 (en) * | 1996-11-23 | 1997-01-15 | Matra Bae Dynamics Uk Ltd | Microwave circuits |
CN1098789C (zh) * | 1997-01-01 | 2003-01-15 | 江伟业 | 压水(气)轮 |
US5976964A (en) | 1997-04-22 | 1999-11-02 | Micron Technology, Inc. | Method of improving interconnect of semiconductor device by utilizing a flattened ball bond |
US6600215B1 (en) | 1998-04-02 | 2003-07-29 | Micron Technology, Inc. | Method and apparatus for coupling a semiconductor die to die terminals |
US6169331B1 (en) * | 1998-08-28 | 2001-01-02 | Micron Technology, Inc. | Apparatus for electrically coupling bond pads of a microelectronic device |
US6544880B1 (en) * | 1999-06-14 | 2003-04-08 | Micron Technology, Inc. | Method of improving copper interconnects of semiconductor devices for bonding |
US6555757B2 (en) * | 2000-04-10 | 2003-04-29 | Ngk Spark Plug Co., Ltd. | Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions |
US7073702B2 (en) * | 2003-10-17 | 2006-07-11 | International Business Machines Corporation | Self-locking wire bond structure and method of making the same |
US8357998B2 (en) * | 2009-02-09 | 2013-01-22 | Advanced Semiconductor Engineering, Inc. | Wirebonded semiconductor package |
US8101871B2 (en) * | 2009-05-26 | 2012-01-24 | Lsi Corporation | Aluminum bond pads with enhanced wire bond stability |
US8432024B2 (en) | 2010-04-27 | 2013-04-30 | Infineon Technologies Ag | Integrated circuit including bond wire directly bonded to pad |
US8618677B2 (en) | 2012-04-06 | 2013-12-31 | Advanced Semiconductor Engineering, Inc. | Wirebonded semiconductor package |
TWI569396B (zh) * | 2014-12-08 | 2017-02-01 | 財團法人工業技術研究院 | 具有焊線的晶片結構 |
DE102015219183B4 (de) | 2015-10-05 | 2019-06-06 | Infineon Technologies Ag | Leistungshalbleiterbauelement, Halbleitermodul, Verfahren zum Verarbeiten eines Leistungshalbleiterbauelements |
CN111489975A (zh) * | 2020-04-23 | 2020-08-04 | 南通大学 | 一种铝镍半导体引线的制作方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3877062A (en) * | 1966-09-14 | 1975-04-08 | Siemens Ag | Method for producing metal structures upon semiconductor surfaces |
US3662454A (en) * | 1970-03-18 | 1972-05-16 | Rca Corp | Method of bonding metals together |
US3781596A (en) * | 1972-07-07 | 1973-12-25 | R Galli | Semiconductor chip carriers and strips thereof |
US4042954A (en) * | 1975-05-19 | 1977-08-16 | National Semiconductor Corporation | Method for forming gang bonding bumps on integrated circuit semiconductor devices |
JPS5851425B2 (ja) * | 1975-08-22 | 1983-11-16 | 株式会社日立製作所 | ハンドウタイソウチ |
DE2649773A1 (de) * | 1976-10-29 | 1978-05-11 | Bosch Gmbh Robert | Halbleiteranordnung |
US4141020A (en) * | 1976-12-29 | 1979-02-20 | International Business Machines Corporation | Intermetallic aluminum-transition metal compound Schottky contact |
US4176443A (en) * | 1977-03-08 | 1979-12-04 | Sgs-Ates Componenti Elettronici S.P.A. | Method of connecting semiconductor structure to external circuits |
US4433004A (en) * | 1979-07-11 | 1984-02-21 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor device and a method for manufacturing the same |
DE3107943A1 (de) * | 1981-03-02 | 1982-09-16 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung von loetbaren und temperfaehigen edelmetallfreien duennschichtleiterbahnen |
US4728534A (en) * | 1986-08-04 | 1988-03-01 | Motorola, Inc. | Thick film conductor structure |
JP2511289B2 (ja) * | 1988-03-30 | 1996-06-26 | 株式会社日立製作所 | 半導体装置 |
US4922322A (en) * | 1989-02-09 | 1990-05-01 | National Semiconductor Corporation | Bump structure for reflow bonding of IC devices |
-
1990
- 1990-02-08 JP JP2029029A patent/JPH03233972A/ja active Pending
-
1992
- 1992-08-13 US US07/929,472 patent/US5298793A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5298793A (en) | 1994-03-29 |
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