GB2285174A - Via-hole and production method of via-hole - Google Patents

Via-hole and production method of via-hole Download PDF

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Publication number
GB2285174A
GB2285174A GB9425339A GB9425339A GB2285174A GB 2285174 A GB2285174 A GB 2285174A GB 9425339 A GB9425339 A GB 9425339A GB 9425339 A GB9425339 A GB 9425339A GB 2285174 A GB2285174 A GB 2285174A
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Prior art keywords
metal layer
hole
electroless
substrate
layer
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GB9425339A
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GB9425339D0 (en
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Katsuya Kosaki
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP33082293A priority Critical patent/JPH07193214A/en
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Publication of GB9425339D0 publication Critical patent/GB9425339D0/en
Publication of GB2285174A publication Critical patent/GB2285174A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76868Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

2285174 VIA-HOLE AND PRODUCTION METHOD OF VIA-HOLE FTELD OF THR TWRNTION

The present invention relates to a via-hole having a high aspect ratio (depth/aperture width), and a method for producing the via-hole. BACKGROUND OF THE TNVENTTON

In a conventional semiconductor device, a via-hole is employed as a wiring structure for connecting opposite front and rear surfaces of a semiconductor or insulator substrate through a hole penetrating the substrate.

Figures 9(a)-9(e) are sectional views illustrating process steps of forming a via-hole in a conventional production method of a semiconductor device. In the figures, reference numeral 1 designates a GaAs substrate, numeral la designates a bottomed hole formed in the substrate 1, and numeral lb designates a-through-hole penetrating the substrate 1. Reference numeral 2 designates an insulating film comprising SiN or SiON, and numeral 33 designates a photores1st pattern. Reference numeral 8 designates a metal layer formed by depositing Ti and Au-in this order using a sputtering technique (hereinafter referred to as a sputtered metal layer), and numeral 8a designates a portion of the inner surface of the hole la where the sputtered metal layer 8 is not deposited. Further, reference numeral 9 designates an electroplated Au layer, numeral 10 designates a wiring pattern, and numeral 11 designates a low resistance metal layer formed over the rear surface of the substrate 1 by vapor deposition or plating.

A description is given of the production process.

Initially, an insulating film 2, such as SiN or SiON, is formed on a GaAs substrate 1, and a photoresist pattern (not shown) is formed on the insulating film 2. Using the photoresist pattern as a mask, the insulating film 2 and the substrate 1 are selectively etched by RIE (Reactive Ion Etching) to form a hole la having prescribed width and depth, followed by removal of the photoresist pattern (Figure 9(a)).

Thereafter, the entire surface of the GaAs substrate 1 including the inner surface of the hole la is subjected to sputtering of T1 and Au in this order, forming a sputtered metal layer 8 (figure 9(b)). Then, a photoresist pattern 33 is formed on the sputtered metal layer 8 except a region where a wiring pattern is to be produced. Using the photoresist-pattern 33 as a mask and the low resistance Au layer of the sputtered metal layer 8 as a feeding layer, an Au layer 9 is selectively electroplated on the exposed part of the sputtered metal layer 8 (figure 9(c)).

After removal of the photoresist pattern 33, portions of the sputtered metal layer 8 exposed by the removal of the photoresist pattern 33 are selectively removed by ion milling or etching, whereby a wiring pattern 10 is formed from the front surface of the GaAs substrate 1 along the inner wall of the hole la (figure 9(d)).

Thereafter, the rear surface of the GaAs substrate I is polished until a through-hole lb penetrating the substrate is formed, i.e., until the wiring pattern 10 is exposed at the rear surface of the substrate. Finally, a low resistance metal layer 11 comprising Au or the like is formed over the rear surface of the GaAs substrate 1 including the exposed wiring pattern 10, preferably by vapor deposition or plating, whereby a via-hole structure shown in figure 9(a) is obtained.

This via-hole is employed as a wiring structure for grounding a microstrip line of a high-frequency semiconductor IC chip or as a wiring structure for grounding a source of an FET.

Figures 10 and 11 illustrate a high-frequency and high-output GaAs MMIC (Monolithic Microwave Integrated Circuit) chip in which via-holes are employed as wirings for grounding source electrodes of FETs. Figure 10(a) is a plan view of the MMIC chip, and figure 10(b) is an enlarged view of a portion A of figure 10(a). Figure 11(a) is a sectional view taken along a line lla-lla of figure 10(a), and figure 11(b) is a sectional view taken along a line llb-llb of figure 10(a).

In the figures, reference numeral 1 designates a GaAs substrate. A plurality of FETs are arranged in a line on the GaAs substrate 1. Gate electrodes 203a of the respective FETs are connected to a common gate electrode 203, and -the common gate electrode 203 is connected to a gate bonding pad 223. Drain electrodes of the respective FETs are connected to drain wirings 201a, and the drain wirings 201a are connected to a common drain wiring 201. Further, the common drain wiring 201 is connected to a drain bonding pad 221. Source electrodes of the respective FETs are connected to source grounding wirings 10a. In figures 11(a) and 11(j:), the source grounding wiring 10a is connected through the hole lb to a grounded low resistance metal layer lla on the rear surface of the substrate 1.

In the above-described production process of a viahole, after the formation of the sputtered metal layer 8 over the entire surface of the substrate I including the inner surface of the hole la, the Au layer 9 is selectively electroplated using the sputtered metal layer 8 as a feeding layer. Thereafter, the rear surface of the substrate I is polished to expose the wiring pattern 10, and the low resistance metal layer 11 is formed on the rear surface of the substrate 1. In this conventional method, however, when the hole la has a high aspect ratio, for example, an aperture width less than 60 pm and a depth exceeding 100 pm, the sputtered metal layer 8 used as a feeding layer for electroplating is not deposited evenly on the inner surface of the hole la. The unevenness of the sputtered metal layer 8 causes-an uneven thickness of the Au layer 9 electroplated -on the sputtered metal layer 8. When the sputtered metal layer 8 is discontinuous on the inner surface of the hole la as shown in figure 9(b), the Au layer 9 electroplated on the sputtered metal layer 8 is also discontinuous between the upper part and the lower part of the hole la as shown in figure 9(c). Consequently, the wiring layer on the front surface of the.substrate 1, i.e., the electroplated Au layer 9, is not connected to the wiring on the rear surface of the substrate 1, i.e., the low resistance metal layer 11, through the hole lb.

There is a prior art technique of forming a via-hole wiring, in which an Au layer is plated over the inner surface of the hole of the substrate by'electroless plating and, thereafter, the rear surface of the substrate is polished and the rear side wiring is formed. However, since the electroless plating provides a very low growth rate of the-Au layer, the thickness of the-plated Au layer is very thin. Further, the electrolessplated Au layer has a poor adhesion to the inner surface of.the hole. Therefore, in this prior art method, it is-impossible to produce a viahole with a reliable strength and a low resistance.

SUMMARY OF THE INVENTTON

It is an object of the present invention to provide a via-hole structure in which a thick metal layer having a low resistance is disposed over an inner surface of a hole of a semiconductor or insulator substrate having a high aspect ratio, and the metal layer is adhered closely to the inner surface of the hole.

It is another object of the present invention to provide a method of producing the via-hole.

Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various,additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.

According to a first aspect of the present invention, in a method of producing a via-hole,-a hole having a prescribed depth is formed in a prescribed region of a semiconductor substrate, and a base metal layer having a function of a feeding layer for electroplating is formed on the inner surface of the hole by sputtering and electroless plating. Then, a low resistance metal is electroplated using the base metal layer as a feeding layer. Finally, the rear surface of the substrate is polished, and a wiring layer is formed on the rear surface of the substrate, electrically contacting the. electroplated low resistance metal layer. In this method, since the inner surface of the hole is completely covered with the base metal layer formed by sputtering and electroless plating, a thick low resistance metal layer can be electroplated over the inner surface of the hole without discontinuity.

According to a second aspect of the present invention, in a method of producing a via-hole, a hole having a prescribed depth is formed in a prescribed region of a substrate, and a metal layer having a good adhesion to the inner surface of the hole and a function of a feeding layer for electroplating is sputtered over the entire surface of the substrate including the inner surface of the hole. Thereafter, by electroless plating using the sputtered metal layer as a catalyst, a metal layer having a good adhesion to the surface of the sputtered metal layer and the inner surface of the hole is selectively plated on the surface of the sputtered metal layer and on the inner surface of the hole where the sputtered metal layer is absent. Thereafter, a low resistance metal is electroplated using the sputtered metal layer and the electroless-plated metal layer as feeding layers,; followed by polishing of the rear surface of the substrate. Finally, a wiring layer is formed on the 1 rear surface of the substrate, electrically contacting the electroplated low resistance metal layer. In this method, since the inner surface of the hole is completely covered with the sputtered metal layer and the electroless-plated metal layer, a thick low resistance metal layer can be electroplated over the inner surface of the hole without discontinuity. Further, since the sputtered metal layer and the electroless-plated metal layer have a good adhesion to the inner surface of the hole, the electroplated low resistance metal layer is formed with a good adhesion to the inner surface of the hole through the sputtered metal layer and the electroless-plated metal layer.

According to a third aspect of the present invention, in a method of producing a via-hole, a hole having a prescribed depth is formed in a prescribed region of a substrate, and a metal layer having a good adhesion to the inner surface of the hole is selectively plated on the inner surface of the hole by electroless plating. Then, a metal layer having a good adhesion to the surfaces of the substrate and the electroless-plated metal layer and having a function of a feeding layer is sputtered over these surfaces. Thereafter, a low resistance metal is electroplated using the sputtered metal layer and the electroless-plated metal layer as feeding"14yers, followed by polishing of the rear surface of the substrate. Finally, a wiring layer is formed on the rear surface of the substrate, electrically contacting the electroplated low resistance metal layer. In this method, since the inner surface of the hole is completely covered with the sputtered metal layer and the electroless-plated metal layer, a thick low resistance metal layer can be electroplated over the inner surface of the hole without discontinuity. Further, since the sputtered metal layer and the electroless-plated metal layer have a good adhesion to the inner surface of the hole, the electroplated low resistance metal layer is formed with a good adhesion to,the inner surface of the hole through the sputtered metal layer and the electroless-plated metal layer.

According to a fourth aspect of the present invention, in the abovedescribed method of producing a via-hole, the electroless-plated metal layer is formed on the inner surface of the hole so that it does not have a portion protruding from the hole over the front surface-of the substrate. Therefore, the sputtered metal layer and the electroplated metal layer formed on the electroless-plated metal layer do not swell at the periphery of the opening of the hole, so that portions of these layers on the front surface of the substrate are made flat.

RRTRV nRSCRTPTTON OF THE DRAWINGS Figures l(a)-l(d) are sectional views illustrating process steps in a method of producing a via-hole of a semiconductor device in accordance with a first embodiment of the present invention.

Figures 2(a)-2(c) and 3(a)-3(c) are sectional views illustrating process steps in a method of producing a via-hole of a semiconductor device in accordance with a second embodiment of the present invention.

Figures 4(a)-4(d) and 5(a)-5(c) are sectional views illustrating process steps in a method of producing a viahole of a semiconductor device in accordance with a third embodiment of the present invention.

Figures 6(a) and 6(b) are sectional views for explaining a problem in the production process according to the second and third embodiments of the invention.

Figures 7(a)-7(c) and 8(a)-8(c) are sectional views illustrating process steps in a method of producing a viahole of a semiconductor device in accordance with a fourth embodiment of the present invention.

Figures.9(a)-9(e) are sectional views illustrating process steps in a method of producing a via-hole of a semiconductor device according to the prior art.

Figures 10(a) and 10(b) are diagrams for explaining a conventional highfrequency and high-output MMIC, in which figure 10(a) is a plan view of the MMIC, and figure 10(b) is an enlarged view of a portion A of figure 10(a).

Figure ll(a) is a sectional view taken along a line lla-11a of figure 10(a), and figure 11(b) is a sectional view taken along a line llb-11b of figure 10(a).

nRTATT.Rn DESCRIPTION OF THE PRRPRRRM RMBODIMENTS [Embodiment 11 Figures l(a)-l(d) Are sectional views illustrating process steps in a method of producing a via-hole of a semiconductor device in accordance with a first embodiment of the present invention. In the figures, the same reference numerals as in figures 9(a)-9(e) designate the same or corresponding parts. Reference numeral 7 designates an Ni base alloy layer comprising, for example, Ni-P, Ni-B, or Ni-B-W, formed by electroless-plating (hereinafter referred to as an electroless-plated Ni base alloy layer).

A description is given of the production process.

Initially, an insulating film 2, such as SiN or SiON, is formed on the surface of the GaAs substrate 1, and a photoresist pattern (not shown) is formed on the insulating film 2. Using the photoresist film 2 as a mask, the insulating fl lm 2 and the GaAs substrate 1 are selectively etched by RIE to form a hole la having a depth of 100 - 120 pm and an aperture width of 50 - 60 pm, followed by removal of the photoresist pattern.

Thereafter, a first metal layer comprising T!, Cr, or Ni and having a thickness less than 500 A and a second metal 12 - layer comprising a low resistance metal, such as Au, and having a thickness of about 2000 A are successively deposited over the entire surface of the GaAs substrate 1 including the inner surface of the hole la using a sputtering technique, whereby a sputtered metal layer 8 is formed (figure 1(a)). The first metal layer comprising Ti, Cr, or Ni has a good adhesion to the inner surface of the hole la of the GaAs substrate 1. Then, a photoresist pattern 33 is formed on the sputtered metal layer 8 except a region where a wiring pattern is to be formed. Using the photoresist pattern 33 as a mask and the sputtered metal layer 8 as a catalyst, an Ni base alloy layer 7 about 5000 A thick is selectively formed on the unmasked portion of the sputtered metal layer 8 and on the inner surface of the hole la where the sputtered metal layer 8 is absent, by electroless plating (figure 1(b)). The electroless-plated Ni base alloy layer 7 has a good adhesion to the surface of the sputtered metal layer 8 and the inner surface of the hole la.

Thereafter, using the low resistance Au layer included in the sputtered metal layer 8 and the electroless-plated Ni base alloy layer 7 as feeding layers-, an Au layer 9 having a thickness exceeding 3 pm is formed on the electroless-plated Ni base alloy layer 7 by electroplating (figure l(c)).

After removal of the photoresist pattern.33, portions of the sputtered metal layer 8 exposed by the removal of the photoresist pattern 33 are selectively removed by ion milling or etching, whereby a wiring pattern 10 is formed from the front surface of the GaAs substrate 1 over the inner surface of the hole la of the substrate 1. Thereafter, the rear surface of the GaAs substrate 1 is polished until the wiring pattern 10 is exposed, i.e., until a through-hole lb penetrating the substrate 1 is formed. Finally, an Au layer 11 is formed over the rear surface of the GaAs substrate 1 including the exposed surface of the wiring pattern 10, preferably by vapor deposition or plating, resulting in a via-hole structure in which the wiring pattern 10 is connected to the rear side wiring 11 via the through-hole lb (figure l(d)). Since the first metal layer comprising Ti, Cr, or Ni of the sputtered metal layer 8 has a high resistance, it is desired that the polishing of the GaAs substrate 1 is carried out until the high resistance first metal layer is completely removed and the-second metal layer, i.e., the low resistance Au layer, is exposed.

In this first embodiment of the present invention, after formation of the sputtered metal layer 8 on the inner surface of the hole la of the GaAs substrate 1, the electroless-plated Ni base alloy layer 7 is formed on the sputtered metal layer 8 and on portions of the inner surface - 14 a of the hole la where the sputtered metal layer 8 is absent. Thereafter, using the sputtered metal layer 8 and the electroless-plated Ni base alloy layer 7 as feeding layers, the Au layer 9 is electroplated. Therefore, a thick electroplated Au layer 9 exceeding 3 pm is evenly formed over the inner surface of the hole la without discontinuity. In addition, the first metal layer comprising Ti, Cr, or Ni included in the sputtered metal layer 8 adheres closely to the inner surface of the hole la with a good adhesion, and the electroless-plated Ni base alloy layer 7 adheres closely to the sputtered metal layer 8 and the inner surface of the hole la with a good adhesion. Therefore, the electroplated Au layer 9 is formed with a good adhesion to the inner surface of the hole la through the sputtered metal layer 8 and the electroless-plated Ni base layer 7. After the formation of the wiring pattern 10 comprising the abovedescribed layers 7, 8, and 9, the rear surface of the GaAs substrate 1 is polished to expose the wiring pattern 10, and the Au layer 11 is formed on the rear surface of the substrate. In the via-hole structure produced in this way, the wiring on the front surface of the substrate 1, i.e., the wiring pattern 10 including the electroplated Au layer 9, is connected to the wiring on the rear surface of the substrate, i.e., the Au layer 11, through the through-hole 1b, with high reliability. Further, the strength of the via-hole is improved. [Embodiment 2] Figures 2(a)-2(c) and 3(a)-3(c) are sectional views illustrating process steps in a method of producing a viahole of a semiconductor device in accordance with a second -embodiment of the present invention. In figures, the same reference numerals as in figures l(a)-l(d) designate the same or corresponding parts. Reference numeral 66 designates Pd nuclei serving as a catalyst of electroless plating.

A description is given of the production process.

Initially,. an insulating film 2 comprising SiN or SiON is formed on the surface of the GaAs substrate 1, and a photoresist pattern 3 is formed on the insulating film 2. Using the photoresist pattern 3 as a mask, the insulating film 2 and the GaAs substrate I are etched by RIE to form a hole la having a depth of 100 - 120 pm and an aperture width of 50 pm. Thereafter, using the photoresist pattern 3 as a mask, a Pd activated solution, for example, a mixture of PdC12 and HC1, is applied to the inner surface of the hole la, whereby Pd nuclei 66 are deposited on the inner surface of the hole la (figure 2(a)).

After removal of the photoresist pattern 3 (figure 2(b)), by electroless plating using the insulating film 2 as a mask and the Pd nuclei 66 as a catalyst, an Ni base alloy layer 7, such as Ni-P, Ni-B, or Ni-B-W, is selectively formed on the inner surface of the hole la to a thickness of about 5000 A (figure 2(c)). The electroless-plated Ni base alloy layer 7 adheres closely to the surface of the hole la with a good adhesion.

Thereafter, a first metal layer comprising Ti, Cr, or Ni and having a thickness less than 500 A and a second metal layer comprising a low resistance metal, such as Au, and having a thickness of about 2000 A are successively sputtered on the surface of the insulating film 2 and on the surface of the electroless-plated Ni base alloy layer 7 in the hole la, resulting in a sputtered metal layer 8 (figure 3(a)).

In the step of figure 3(b), a photoresist pattern 33 is formed on the sputtered metal layer 8 except a region where a wiring pattern is to be formed. Using the photoresist pattern 33 as a mask, an Au layer 9 having a thickness of 3 pm or more is selectively electroplated on the sputtered metal layer 8 and on the electroless-plated Ni base alloy layer 7. The sputtered metal layer 8 and the Ni base alloy -layer 7 serve as feeding layers for the electroplating.

After removal of the photoresist pattern 33, portions of the sputtered metal layer 8 exposed by the removal of the photoresist pattern 33 are selectively removed by ion milling or etching, whereby a wiring pattern 10 is formed" from the front surface of the GaAs substrate 1 over the inner surface of the hole la of the substrate 1. Thereafter, the rear surface of the GaAs substrate 1 is polished until the wiring pattern 10 is exposed at the rear surface,i.e., until a through-hole lb penetrating the substrate 1 is formed. Finally, an Au layer 11 is formed on the rear surface of the GaAs substrate I including the exposed surface of the wiring pattern 10 by vapor deposition or plating, resulting in a via-hole structure in which the wiring pattern 10 is connected to the rear side Au wiring 11 via the through-hole lb (figure 3(c)).

In this second embodiment of the present invention, after the selective electroless plating of the Ni base alloy layer 7 on the inner surface of the hole la of the GaAs substrate 1, the sputtered metal layer 8 having a function of a feeding layer for electroplating is formed on the front surface of the GaAs substrate 1 and on the surface of the electrolessplated Ni base alloy layer 7. Thereafter, the Au layer 9 is electroplated on the sputtered metal layer 8 and on the electroless-plated Ni base alloy layer 7 using these layers as feeding layers. Therefore, a thick electroplated Au layer exceeding 3 pm can be formed without discontinuity. In addition, the electroless-plated Ni base alloy layer 7 comprising NiP, Ni-B, Ni-B-W, or the like adheres closely to the inner surface of the hole la of the GaAs substrate 1 with a good adhesion, and the first metal layer comprising Ti, Cr, or Ni included in the sputtered metal layer 8 adheres closely to the electroless-plated Ni base alloy layer 7 and mhe insulating film 2 with a good adhesion.. Therefore, the electroplated Au layer 9 is formed with a good adhesion to the inner surface of the hole la through the sputtered metal layer 8 and the electrolessplated Ni base layer 7. After the formation of the wiring pattern 10 comprising the above-described layers 7, 8, and 9, the rear surface of the GaAs substrate 1 is polished to expose the wiring pattern 10, and the Au layer 11 is formed on the rear surface of the substrate. In the via-hole structure produced in this way, the wiring on the front surface of the substrate 1, i.e., the wiring pattern 10 including the electroplated Au layer 9, is connected to the wiring on the rear surface of the substrate, i.e., the Au layer 11, via the through-hole lb, with high reliability. Further, the strength of the via-hole is improved. [Embodiment 31 Figures,4(a)-4(d) and 5(a)-5(c) are sectional views illustrating process steps of producing a via-hole of a semiconductor device in accordance with a third embodiment of the present invention. In these figures, the same reference.numerals as in figures l(a)-l(d) designate the same or corresponding parts. Reference numeral 4 designates a metal layer comprising one selected from Ti, Cr, and Ni, numeral 5 designates an Au layer, and numeral 6 designates Pd layer. These layers 4, 5, and 6 are formed by vapor deposition.

A description is given of the production process.

Initially, an insulating film 2, such as SiN or SiON, is formed on the surface of the GaAs substrate 1, and a photoresist pattern 3 is formed on the insulating film 2. Using the photoresist pattern 3 as a mask, the insulating film 2 and the GaAs substrate 1 are selectively etched by RIE to form a hole la having a depth of 100 - 120 pm and an aperture width of 50 - 60 pm (figure 4(a)).

Using the photoresist pattern 3 as a mask, a metal layer 4 comprising Ti, Cr, or Ni and having a thickness less than 500 A, an Au layer 5 having a thickness less than 500 A, and a Pd layer 6 having a thickness less than 500 A are successively deposited on the bottom of the hole la by vapor deposition (figure 4(b)). The metal layer 4 comprising Ti, qr, or Ni adheres closely to the bottom of the hole la. The Pd layer 6 serves as a catalyst in the subsequent electroless plating process. The Au layer 5 interposed between the metal layer 4 and the Pd layer 6 serves as a buffer layer that prevents separation of the Pd layer 6 from the metal layer 4 due to the difference in linear expansion coefficients between these layers 4 and 6.

After removal of the photoresist pattern 3 (figure 4(c)), using the insulating film 2 as a mask and the Pd layer 6 as a catalyst, an Ni base alloy layer 7 about 5000 A thick is formed on the inner surface of the hole la by electroless plating (figure 4(d)).

Thereafter, a first metal layer comprising Ti, Cr, or NI and having a thickness less than 500 A and a second metal layer comprising a low resistance metal, such as Au, and having a thickness of about 2000 A are successively sputtered on the surface of the insulating film 2 and on the surface of the electroless-plated Ni base alloy layer 7 in the hole la, resulting in a sputtered metal layer 8 (figure 5(a)).

In the step of figure 5(b), a photoresist pattern 33 is formed on the sputtered metal layer 8 except a region where a wiring pattern is to be formed. Using the photoresist pattern 33 as a mask, an Au layer 9 having a thickness exceeding 3 pm is selectively electroplated on the sputtered metal layer 8 and on the electroless-plated Ni base alloy layer 7. The sputtered metal layer-8 and the electrolessplated Ni base alloy layer 7 serve as feeding layers in the electroplating process.

After removal of the photores:st pattern 33, portions of the sputtered metal layer 8 exposed by the removal of the photoresist pattern 33 are selectively removed by ion - milling or etching, whereby a wiring pattern 10 is formed from the front surface of the GaAs substrate 1 over the inner surface of the hole la. Thereafter, the rear surface of the GaAs substrate 1 is polished until the wiring pattern 10 is exposed at the rear surface, i.e., until a throughhole lb penetrating the substrate 1 is formed. Finally, an Au layer 11 is formed over the rear surface of the GaAs substrate I including the exposed surface of the wiring pattern 10 by vapor deposition or plating, resulting in a via-hole structure in which the wiring pattern 10 is connected to the rear side Au wiring 11 via the through-hole lb (figure 5(c)-). Since the metal layer 4 comprising Ti, Cr, or Ni has a high resistance, it is desired that the polishing of the substrate 1 is carried out until the high resistance metal layer 4 is completely removed and the low resistance Au layer 5 is exposed.

Also in this third embodiment of the invention, the same effects as described in the second embodiment are achieved. In addition, since the vapor-deposited Pd layer 6 is used as a catalyst for the electrolessplating of the Ni base alloy layer 7, the process of immersing the substrate 1 in a Pd activated solution to deposit Pd nuclei as in the second embodiment can be dispensed with.

In the production of the via-hole structure according to the second or third embodiment of the invention, the electroless-plated Ni base alloy layer 7 sometimes protrudes over the periphery of the opening of the hole la as shown in figure 6(a). In this case,.as shown in figure 6(b), the protruding portion of the Ni base alloy layer 7 causes an uneven surface of the electroplated Au layer 9 at the periphery of the opening of the hole la. The uneven portion of the Au layer 9 is an obstacle to a stable wire-bonding on the Au layer 9. This problem is solved in a fourth embodiment of the present invention described hereinafter. [Embodiment 41 Figures 7(a)-7(c) and B(a)-S(c) are sectional views illustrating process steps of producing a via-hole of a semiconductor device according to the fourth embodiment of the present invention. In the figures, the same reference numerals as in figures 1(a)-l(d) designate the same or corresponding parts. Reference numeral 2a designates an insulating film, and numeral 22 designates an overhanging portion of the insulating film 2.

A description is given of the production process.

Initially, an insulating film 2, such as SiN or SiON, is formed on the surface of the GaAs substrate 1, and a photoresist pattern 3 is formed on the insulating film 2. Using the photoresist pattern 3 as a mask, the insulating film 2 and the GaAs substrate 1 are selectively etched by RIE to form a hole having prescribed depth and width. Then, - 23 the inner surface of the hole la is subjected to isotropic chemical etching that over-etches the side wall of the hole, whereby a hole la having a depth of 100 - 120 pm and an aperture width of 50 - 60 pm is formed (figure 7(a)). The insulating film 2 has a portion 22 overhanging the hole la.

As in the above-described third embodiment, using the photoresist pattern 3 as a mask, a metal layer comprising one selected from Ti, Cr, and Ni and having a thickness less than 500 A, an Au layer 5 having a thickness less than 500 A, and a Pd layer 6 having a thickness less than 500 A are successively vapor-deposited on the bottom of the via-hole la (figure 7(b)).

After removal of the photoresist pattern 3 (figure 7(c)), using the insulating film 2 as a mask and the vapordeposited Pd layer 6 as a catalyst, an Ni base alloy layer 7 about 5000 A thick is formed on the inner surface of the hole la by electroless plating (figure 8(a)). In the electroless plating, the overhanging portion 22 of the insulating film 2 prevents the plated Ni base alloy layer 7 from protruding over the front surface of the GaAs substrate 1.

The overhanging portion 22 of the insulating film 2 is removed by ion milling or selective etching (figure 8(b)). Thereafter, as illustrated in figure 8(c), the sputtered metal layer 8 and the electroplated Au layer 9 are selectively formed in the same process as described with respect to figures 5(a) and 5(b). Finally, as illustrated in figure 5(c), the rear surface of the GaAs substrate I is polished to expose the wiring pattern 10, and the Au layer 11 is formed over the rear surface of the substrate 1, whereby a via-hole structure in which the wiring pattern 10 is connected to the rear side Au wiring 11 via the throughhole lb is produced.

Also in this fourth embodiment of the invention, the same effects as described in the third embodiment are achieved. Further, since the unwanted protrusion of the electroless-plated Ni base alloy layer 7 from the periphery of the opening of the hole la is avoided, the electroplated Au layer 9 on the front surface of the GaAs substrate 1 has an even surface that facilitates the subsequent wire-bonding of the Au layer 9.

In the above-described first to fourth embodiments, after the formation of the electroless-plated N! base alloy layer 7, the surface of the electroless-plated Ni base alloy layer 7 may be substituted by a substitution type electroless plating of Au. in this case, the adhesion between the electroless-plated N! base alloy layer 7 and the electroplated Au layer 9 is improved.

Although in the above-described first to fourth embodiments the insulating film 2 is used as a mask for the electroless plating of the Ni base alloy layer 7, when another metal pattern is exposed in a region of the substrate other than the region shown in the figures, a photoresist pattern masking this metal pattern is formed before the formation of the electroless-plated Ni base alloy 'layer 7.

-While in the above-described first to fourth embodiments the electrolessplated metal layer 7 comprises Ni base alloy, the electroless-plated metal layer 7 may comprise other metals so far as the metal has a good adhesion to the surface to which it is plated.

While in the above-described first to fourth embodiments Au is employed as a low resistance metal, other low resistance metals, such as Ag or Cu, may be employed.

In the foregoing description, emphasis has been placed upon a via-hole structure of a semiconductor device employing a GaAs substrate. However, the structure and the production process of the via-hole according to the present invention may be applied to other semiconductor devices including substrates of other semiconducior materials or insulators, such as sapphire, or devices other than semiconductor devices and including insulator substrates.

1

Claims (1)

  1. Claims
    1. A via-hole a substrate a through-hole and having an inner surface; a sputtered metal layer disposed on part of the surface of the substrate and on the inner surface of the through-hole an electroless-plated metal layer disposed on the sputtered metal layer and the inner surface of the through-hole; and an electroplated metal layer disposed on the electroless-plated metal layer comprising: having a surface; penetrating,the substrate 2. The via-hole of claim 1 wherein said through-hole has a depth and an aperture width in an aspect ratio (depth/aperture width) larger than 5/3.
    3. The via-hole of claim 1 wherein said sputtered metal layer comprises a first metal layer comprising one selected from Ti, Cr, and Ni and having a good adhesion to the inner surface of the through-hole, and a second metal layer having a low resistance disposed on the first metal layer.
    4. The via-hole of claim 1 wherein said electroless plated metal layer is an electroless-plated Ni base alloy layer.
    5. The via-hole of claim 1 wherein said electroplated metal layer is an electroplated Au layer.
    6. A via-hole comprising:
    a substrate having a surface; a through-hole penetrating the substrate and having an inner surface; an electroless-plated metal layer disposed on the inner surface of the through-hole a sputtered metal layer disposed on part of the surface of the substrate and on the electroless-plated metal layer; and an electroplated metal layer disposed on the electroless-plated metal layer and on the sputtered metal layer 7. The via-hole of claim 6 wherein said through-hole has a depth and an aperture width in an aspect ratio (depth/aperture width) larger than 5/3.
    8. The via-hole of claim 6 wherein said sputtered - 28 metal layer comprises a first metal layer comprising one selected from Ti, Cr, and Ni and having a good adhesion to the inner surface of the through-hole, and a second metal layer having a low resistance and disposed on the first metal layer.
    9. The via-hole of claim 6 wherein said electroless plated metal layer is an electroless-plated Ni base alloy layer.
    10. The via-hole of claim 6 wherein said electroplated metal layer is an electroplated Au layer.
    11. A method of producing a via-hole comprising:
    forming a hole in a prescribed region of a substrate having opposite front and rear surfaces, said hole having a prescribed depth from the front surface of the substrate and an inner surface; sputtering a metal layer on the inner surface of the hole plating a metal layer on the inner surface of the hole and on the sputtered metal layer by electroless plating; and electroplating a low resistance metal layer on - 29 the electroless-plated metal layer 12. The method of claim-11 further comprising:
    after formation of the electroplated low resistance metal layer polishing the rear surface of the substrate until the hole penetrates through the substrate and forming a low resistance metal layer over the rear surface of the substrate electrically contacting the electroplated metal layer 13. A method of producing a via-hole comprising:
    forming a hole in a prescribed region of a substrate having opposite front and rear surfaces, said hole having a prescribed depth from the front surface of the substrate and an inner surface; sputtering a metal layer on part of the front surface of the substrate and on the inner surface of the hole selectively plating a metal layer on the inner surface of the hole where the sputtered metal layer is absent and on a portion of the sputtered metal layer to be a wiring layer, by electroless plating using the sputtered metal layer as a catalyst; and electroplating a low resistance metal layer on the electroless-plated metal layer using the sputtered metal layer and the electroless-plated metal layer as feeding layers.
    14. The method of claim 13 wherein said hole depth and an aperture width in an aspect ratio (depth/aperture width) larger than 5/3.
    has a 15. The method of claim 13 wherein said sputtered metal layer is formed by sputtering a first metal having a good adhesion to the inner surface of the hole on the inner surface of the hole and then sputtering a second metal having a low resistance on the sputtered first metal.
    16. The method of claim 15 wherein the first metal is one selected from Ti, Cr, and Ni, and the second metal is Au.
    17. The method of claim 13 wherein said electroless plated metal layer is an electroless-plated Ni base alloy layer.
    18. The method of claim 13 wherein said electroplated metal layer is an electroplated Au layer.
    19. The method of claim 17 further including substituting the surface of the electroplated Ni base alloy layer by a substitution type electroless plating of Au.
    20. The method of claim 13 further comprising:
    after formation of the electroplated low resistance metal layer, polishing the rear surface of the substrate until the hole penetrates through the substrate and forming a low resistance metal layer over the rear surface of the substrate electrically contacting the electroplated metal layer and 21. A method of producing a via-hole comprising:
    forming a hole in a prescribed region of a substrate having opposite front and rear surfaces, said hole having a prescribed depth from the front surface of the substrate and an inner surface; plating a metal layer - on the inner surface of the hole by electroless plating; sputtering a metal layer on the front surface of the substrate and on the electroless-plated metal layer; and electroplating a low resistance metal layer on the sputtered metal layer and on the electroless-plated metal layer using the sputtered metal layer and the electroless-plated metal layer as feeding layers.
    22. The method of claim 21 wherein said hole has a depth and an aperture width in an aspect ratio (depth/aperture width) larger than 5/3.
    23. The method of claim 21 wherein said electroless plated metal layer is an electroless-plated Ni base alloy layer.
    24. The method of claim 21 wherein said electroless-plated metal layer is formed by electroless-plating an Ni base alloy layer on the inner surface of the hole using, as a catalyst, a Pd layer selectively vapor-deppsited at the bottom of the hole 25. The method of claim 21 wherein said sputtered metal layer is formed by sputtering a first metal having a good adhesion to the surface of the substrate and to the surface of the electroless-plated metal layer and then sputtering a second metal having a low resistance on the sputtered first metal.
    26. The method of claim 21 wherein said electroplated metal layer is an electroplated Au layer.
    27. The method of claim 23 further including substituting the surface of the electroplated Ni base alloy layer by a substitution type electroless plating of Au.
    28. The method of claim 24 further including substituting the surface of the electroplated Ni base alloy layer by a substitution type electroless plating of Au.
    29. The method of claim 25 wherein the first metal is one selected from Ti, Cr, and Ni, and the second metal is Au.
    30. The method of claim 21 further including:
    after formation of the electroplated low resistance metal layer, polishing the rear surface of the substrate until the hole penetrates through the substrate; and forming a low resistance metal layer over the rear surface of the substrate electrically contacting the electroplated metal layer 1. A method of producing a via-hole comprising:
    preparing a substrate rear surfaces; forming an insulating film of the substrate selectively etching portions of the insulating film and the substrate by anisotropic etching, thereby forming an opening in a prescribed region of the insulating film and a hole in the substrate opposite the opening of the insulating film, said hole having a prescribed depth from the front surface of the substrate having opposite front and on the front surface selectively etching the substrate at the inner surface of the hole by isotropic etching to increase the width of the hole using the insulating film having the opening as a mask, selectively plating a metal layer on the inner surface of the hole by electroless plating; selectively removing a portion of the insulating film contacting the electroless-plated metal layer selectively sputtering a metal layer on the insulating film and on the electroless-plated metal layer and electroplating a low resistance metal layer on the electroless-plated metal layer and on the sputtered metal layer using the electroless-plated metal layer and the sputtered metal layer as feeding layers.
    32. The method of claim 31 wherein said hole depth and an aperture width in an aspect ratio (depth/aperture width) larger than 5/3.
    has a 33. The method of claim 31 wherein said electroless plated metal layer is an Ni base alloy layer.
    34. The method of claim 31 wherein said electroless plated metal layer is formed by electroless-plating an Ni base alloy layer on the inner surface of the hole using a Pd layer selectively vapor-deposited at the bottom of the hole as a catalyst.
    35. The method of claim 31 wherein said sputtered metal layer is formed by sputtering a first metal having a good adhesion to the surface of the substrate and to the surface of the electroless-plated metal layer and then sputtering a second metal having a low resistance on the sputtered first metal.
    36. The method of claim 31 wherein said electroplated metal layer is an electroplated Au layer.
    - 36 37. The method of claim 33 further including substituting the surface of the electroplated Ni base alloy layer by a substitution type electroless plating of Au.
    38. The method of claim 34 further including substituting the surface of the electroplated Ni base alloy layer by a substitution type electroless plating of Au.
    39. The method of claim 35 wherein the first metal is one selected from Ti, Cr, and Ni, and the second metal is Au.
    40. The method of claim 31 further including:
    after formation of the electroplated low resistance metal layer polishing the rear surface of the substrate until the hole penetrates through the substrate and forming a low resistance metal layer over the surface of the substrate, electrically contacting the electroplated metal layer 41. A method of producing a via-hole in a semiconductor device, substantially as herein described with reference to Figure 1, Figures 2 and 3, Figures 4 and 5 or Figures 7 and 8 of the accompanying drawings.
    42. In a semiconductor device, a via-hole substantially as herein described with reference to Figure 1, Figures 2 and 3, Figures 4 and 5 or Figures 7 and 8 of the accompanying drawings.
    37 - 42. In a semiconductor device, a via-hole substantially as herein described with reference to Figure 1, Figures 2 and 3, Figures 4 and 5 or Figures 7 and 8 of the accompanying drawings.
GB9425339A 1993-12-27 1994-12-15 Via-hole and production method of via-hole Withdrawn GB2285174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33082293A JPH07193214A (en) 1993-12-27 1993-12-27 Via-hole and its formation

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GB2285174A true GB2285174A (en) 1995-06-28

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GB (1) GB2285174A (en)

Cited By (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1064417A1 (en) * 1998-03-20 2001-01-03 Semitool, Inc. Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
WO2001046494A1 (en) * 1999-12-22 2001-06-28 Ebara Corporation Electroless plating solution and method of forming wiring with the same
SG82084A1 (en) * 1999-07-09 2001-07-24 Applied Materials Inc In-situ electroless copper seed layer enhancement in an electroplating system
US6565729B2 (en) 1998-03-20 2003-05-20 Semitool, Inc. Method for electrochemically depositing metal on a semiconductor workpiece
US6632345B1 (en) 1998-03-20 2003-10-14 Semitool, Inc. Apparatus and method for electrolytically depositing a metal on a workpiece
US6664640B2 (en) 2001-07-30 2003-12-16 Nec Compound Semiconductor Devices, Ltd. Semiconductor device
US6806186B2 (en) 1998-02-04 2004-10-19 Semitool, Inc. Submicron metallization using electrochemical deposition
US6821909B2 (en) 2002-10-30 2004-11-23 Applied Materials, Inc. Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application
US6824666B2 (en) 2002-01-28 2004-11-30 Applied Materials, Inc. Electroless deposition method over sub-micron apertures
US6899816B2 (en) 2002-04-03 2005-05-31 Applied Materials, Inc. Electroless deposition method
US6905622B2 (en) 2002-04-03 2005-06-14 Applied Materials, Inc. Electroless deposition method
US6908534B2 (en) 1998-04-30 2005-06-21 Ebara Corporation Substrate plating method and apparatus
US7025866B2 (en) 2002-08-21 2006-04-11 Micron Technology, Inc. Microelectronic workpiece for electrochemical deposition processing and methods of manufacturing and using such microelectronic workpieces
US7138014B2 (en) 2002-01-28 2006-11-21 Applied Materials, Inc. Electroless deposition apparatus
US7288486B2 (en) 2005-12-01 2007-10-30 Mitsubishi Electric Corporation Method for manufacturing semiconductor device having via holes
WO2008129423A2 (en) * 2007-04-23 2008-10-30 Cufer Asset Ltd. L.L.C. Conductive via formation
US7651934B2 (en) 2005-03-18 2010-01-26 Applied Materials, Inc. Process for electroless copper deposition
US7654221B2 (en) 2003-10-06 2010-02-02 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US7659203B2 (en) 2005-03-18 2010-02-09 Applied Materials, Inc. Electroless deposition process on a silicon contact
US7827930B2 (en) 2004-01-26 2010-11-09 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US7867900B2 (en) 2007-09-28 2011-01-11 Applied Materials, Inc. Aluminum contact integration on cobalt silicide junction
US8158507B2 (en) 2010-02-08 2012-04-17 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
CN102473639A (en) * 2010-03-09 2012-05-23 松下电器产业株式会社 Process for production of semiconductor device, and semiconductor device
US8581411B2 (en) 2009-08-20 2013-11-12 Mitsubishi Electric Corporation Semiconductor device
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8765574B2 (en) 2012-11-09 2014-07-01 Applied Materials, Inc. Dry etch process
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8846163B2 (en) 2004-02-26 2014-09-30 Applied Materials, Inc. Method for removing oxides
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9236266B2 (en) 2011-08-01 2016-01-12 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9299582B2 (en) 2013-11-12 2016-03-29 Applied Materials, Inc. Selective etch for metal-containing materials
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US10170282B2 (en) 2013-03-08 2019-01-01 Applied Materials, Inc. Insulated semiconductor faceplate designs
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3724110B2 (en) 1997-04-24 2005-12-07 三菱電機株式会社 A method of manufacturing a semiconductor device
US7033463B1 (en) 1998-08-11 2006-04-25 Ebara Corporation Substrate plating method and apparatus
JP4637009B2 (en) * 2005-12-02 2011-02-23 三菱電機株式会社 A method of manufacturing a semiconductor device
JP2008053429A (en) * 2006-08-24 2008-03-06 Fujikura Ltd Semiconductor device
JP6277693B2 (en) * 2013-11-29 2018-02-14 三菱電機株式会社 Semiconductor device
JP6272431B2 (en) * 2016-10-04 2018-01-31 ラピスセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0388563A1 (en) * 1989-03-24 1990-09-26 SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.) Method for forming a contact/VIA

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0388563A1 (en) * 1989-03-24 1990-09-26 SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.) Method for forming a contact/VIA

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6806186B2 (en) 1998-02-04 2004-10-19 Semitool, Inc. Submicron metallization using electrochemical deposition
US6932892B2 (en) 1998-03-20 2005-08-23 Semitool, Inc. Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
US6919013B2 (en) 1998-03-20 2005-07-19 Semitool, Inc. Apparatus and method for electrolytically depositing copper on a workpiece
US6565729B2 (en) 1998-03-20 2003-05-20 Semitool, Inc. Method for electrochemically depositing metal on a semiconductor workpiece
US6632345B1 (en) 1998-03-20 2003-10-14 Semitool, Inc. Apparatus and method for electrolytically depositing a metal on a workpiece
US6638410B2 (en) 1998-03-20 2003-10-28 Semitool, Inc. Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
EP1064417A1 (en) * 1998-03-20 2001-01-03 Semitool, Inc. Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
EP1064417A4 (en) * 1998-03-20 2006-07-05 Semitool Inc Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
US6811675B2 (en) 1998-03-20 2004-11-02 Semitool, Inc. Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
US6908534B2 (en) 1998-04-30 2005-06-21 Ebara Corporation Substrate plating method and apparatus
SG82084A1 (en) * 1999-07-09 2001-07-24 Applied Materials Inc In-situ electroless copper seed layer enhancement in an electroplating system
WO2001046494A1 (en) * 1999-12-22 2001-06-28 Ebara Corporation Electroless plating solution and method of forming wiring with the same
US6664640B2 (en) 2001-07-30 2003-12-16 Nec Compound Semiconductor Devices, Ltd. Semiconductor device
US7138014B2 (en) 2002-01-28 2006-11-21 Applied Materials, Inc. Electroless deposition apparatus
US6824666B2 (en) 2002-01-28 2004-11-30 Applied Materials, Inc. Electroless deposition method over sub-micron apertures
US6905622B2 (en) 2002-04-03 2005-06-14 Applied Materials, Inc. Electroless deposition method
US6899816B2 (en) 2002-04-03 2005-05-31 Applied Materials, Inc. Electroless deposition method
US7025866B2 (en) 2002-08-21 2006-04-11 Micron Technology, Inc. Microelectronic workpiece for electrochemical deposition processing and methods of manufacturing and using such microelectronic workpieces
US6821909B2 (en) 2002-10-30 2004-11-23 Applied Materials, Inc. Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application
US7654221B2 (en) 2003-10-06 2010-02-02 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US7827930B2 (en) 2004-01-26 2010-11-09 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US8846163B2 (en) 2004-02-26 2014-09-30 Applied Materials, Inc. Method for removing oxides
US7651934B2 (en) 2005-03-18 2010-01-26 Applied Materials, Inc. Process for electroless copper deposition
US8308858B2 (en) 2005-03-18 2012-11-13 Applied Materials, Inc. Electroless deposition process on a silicon contact
US7659203B2 (en) 2005-03-18 2010-02-09 Applied Materials, Inc. Electroless deposition process on a silicon contact
US7288486B2 (en) 2005-12-01 2007-10-30 Mitsubishi Electric Corporation Method for manufacturing semiconductor device having via holes
WO2008129423A2 (en) * 2007-04-23 2008-10-30 Cufer Asset Ltd. L.L.C. Conductive via formation
WO2008129423A3 (en) * 2007-04-23 2009-09-17 Cufer Asset Ltd. L.L.C. Conductive via formation
US7867900B2 (en) 2007-09-28 2011-01-11 Applied Materials, Inc. Aluminum contact integration on cobalt silicide junction
US8581411B2 (en) 2009-08-20 2013-11-12 Mitsubishi Electric Corporation Semiconductor device
US8158507B2 (en) 2010-02-08 2012-04-17 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
US8349736B2 (en) 2010-03-09 2013-01-08 Panasonic Corporation Semiconductor device manufacturing method and semiconductor device
CN102473639A (en) * 2010-03-09 2012-05-23 松下电器产业株式会社 Process for production of semiconductor device, and semiconductor device
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9236266B2 (en) 2011-08-01 2016-01-12 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US9012302B2 (en) 2011-09-26 2015-04-21 Applied Materials, Inc. Intrench profile
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9887096B2 (en) 2012-09-17 2018-02-06 Applied Materials, Inc. Differential silicon oxide etch
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8765574B2 (en) 2012-11-09 2014-07-01 Applied Materials, Inc. Dry etch process
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US9449845B2 (en) 2012-12-21 2016-09-20 Applied Materials, Inc. Selective titanium nitride etching
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US9093390B2 (en) 2013-03-07 2015-07-28 Applied Materials, Inc. Conformal oxide dry etch
US10170282B2 (en) 2013-03-08 2019-01-01 Applied Materials, Inc. Insulated semiconductor faceplate designs
US9153442B2 (en) 2013-03-15 2015-10-06 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9093371B2 (en) 2013-03-15 2015-07-28 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9991134B2 (en) 2013-03-15 2018-06-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9184055B2 (en) 2013-03-15 2015-11-10 Applied Materials, Inc. Processing systems and methods for halide scavenging
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9209012B2 (en) 2013-09-16 2015-12-08 Applied Materials, Inc. Selective etch of silicon nitride
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9711366B2 (en) 2013-11-12 2017-07-18 Applied Materials, Inc. Selective etch for metal-containing materials
US9299582B2 (en) 2013-11-12 2016-03-29 Applied Materials, Inc. Selective etch for metal-containing materials
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch

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JPH07193214A (en) 1995-07-28

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