JP4637009B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a metal plating layer is formed on a GaAs substrate and a manufacturing method thereof.

  In a semiconductor device using a GaAs substrate, a wiring structure using a via hole, that is, a wiring structure in which a via hole penetrating the substrate is formed and the front surface side and the back surface side of the substrate are electrically connected is widely used. In the step of forming a metal plating layer such as an Au layer on the inner surface of the via hole, a method using a NiP film as a plating power feeding layer is used. The metal plating layer formed by this method has excellent coverage in the via hole as compared with the case where a Ti film or the like is formed as a plating power feeding layer (see, for example, Patent Document 1).

JP-A-7-193214

  In the conventional method for manufacturing a semiconductor device, when a NiP film is used as a plating power feeding layer, the adhesion force of the NiP film to the GaAs substrate is not sufficient. For this reason, it has been difficult to form a metal plating layer with small film thickness variation on the GaAs substrate.

  The present invention has been made to solve the above problems, and by increasing the adhesion of the plating power feeding layer to the GaAs substrate, a semiconductor device capable of forming a metal plating layer with a small variation in film thickness on the GaAs substrate, And it aims at providing the manufacturing method.

The method of manufacturing a semiconductor device according to the present invention includes a step of forming a layer containing Ni in a via hole penetrating a GaAs substrate, diffusing the Ni into the GaAs substrate, and the GaAs substrate, the plated power supply layer, A step of forming a NiGaAs layer, and after forming the NiGaAs layer, a metal plating layer is formed so as to cover the Ni-containing layer in the via hole using the Ni-containing layer as a power feeding layer And a process . Other features will be described in detail below.

  According to the present invention, it is possible to obtain a semiconductor device capable of forming a metal plating layer having a small film thickness variation on a GaAs substrate by increasing the adhesion of the plating power feeding layer to the GaAs substrate, and a method for manufacturing the same. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.

Embodiment A semiconductor device according to the present invention is formed using a GaAs substrate. Hereinafter, a method for manufacturing this semiconductor device will be described. First, although not shown, an element such as a transistor is formed on the main surface (front surface) of the GaAs substrate. Next, as shown in FIG. 1, a via hole receiving metal 2 is formed on the surface side of the GaAs substrate 1 (in the following explanation of the manufacturing method, the surface side of the GaAs substrate 1 is shown downward).

  Next, the back side of the GaAs substrate 1 is shaved so that the thickness of the substrate is about 50 to 200 μm. Next, the back side of the GaAs substrate 1 is selectively etched using the via hole receiving metal 2 as a stopper. As a result, as shown in FIG. 2, a via hole 3 penetrating the GaAs substrate 1 is formed. The diameter of the via hole 3 is about 30 to 100 μm. The etching is performed using, for example, an ICP-RIE (Inductively Coupled Plasma-Reacitve Ion Etching) apparatus.

  Next, a NiP film having a thickness of about 300 nm is formed on the entire back surface of the GaAs substrate 1 by using an electroless plating method. As a result, a NiP film 4 is formed on the inner surface of the via hole 3 and the back surface side of the GaAs substrate 1 as shown in FIG. This film is a film used as a plating power supply layer when a metal plating layer is formed in the inside of the via hole 3 and the back surface of the GaAs substrate 1 in a later step. Further, the concentration of P (phosphorus) contained in the NiP film 4 is about 6 to 15 wt% (weight%). If the concentration of P is low, the NiGaAs layer to be formed later becomes thick and the amount of warpage of the substrate increases. When the concentration of P is high, the adhesion of the NiP film is deteriorated.

  Next, the NiP film 4 is heat-treated at a temperature of 200 to 300 ° C. for 10 minutes in an atmosphere such as nitrogen. As a result, as shown in FIG. 4, Ni contained in the NiP film 4 diffuses toward the GaAs substrate 1, and a NiGaAs layer 5 is formed at the interface between the GaAs substrate 1 and the NiP film 4. Since the NiGaAs layer 5 is formed by the heat treatment, the adhesion of the NiP film 4 to the GaAs substrate 1 can be dramatically improved. In addition, before or after the above heat treatment, the whole or part of the NiP film 4 is amorphous. After the heat treatment, the amorphous part of the NiP film 4 is crystallized, and a stable film can be obtained.

  Next, an Au film having a thickness of about 50 nm is formed on the entire surface of the back surface of the GaAs substrate 1 by substitution gold plating. Further, an Au film is formed in a required thickness by electrolytic plating. At this time, the NiP film 4 serves as a plating power supply layer when forming the Au film. As a result, as shown in FIG. 5, an Au plating layer 6 is formed on the inner surface of the via hole 3 and the back surface side of the GaAs substrate 1 so as to cover the NiP film 4.

  As described above, a via hole 3 is formed in the GaAs substrate 1 as shown in FIG. 5, and a structure in which the NiGaAs layer 5, NiP layer 4, and Au plating layer 6 are laminated on the inner surface and the back surface of the GaAs substrate 1 is obtained. be able to. In the manufacturing method described above, the via hole 3 is formed on the back surface side of the GaAs substrate 1, but a structure in which the via hole 3 is not formed may be used. Further, the laminated structure may be formed on the surface side of the GaAs substrate 1. That is, a structure in which the NiGaAs layer 5, the NiP layer 4, and the Au plating layer 6 are sequentially formed on either the front surface or the back surface of the GaAs substrate substrate 1 may be employed.

  In the above manufacturing method, the NiP film 4 is formed on the GaAs substrate 1 and subjected to heat treatment, whereby the NiGaAs layer 5 is formed at the interface between the GaAs substrate 1 and the NiP film 4 (see FIG. 4). Here, the relationship between the film thickness of the NiGaAs layer 5 and the heat treatment temperature of the heat treatment will be described. FIG. 6 shows the thickness of the NiP film and the NiGaAs layer after forming a NiP film of about 250 nm on the GaAs substrate by electroless plating and performing heat treatment. When the heat treatment temperature is 150 to 250 ° C., the thickness of the NiP film is reduced to about 150 to 200 nm, and the thickness of the NiGaAs layer is 150 to 200 nm. Therefore, by performing the heat treatment at the above temperature, Ni contained in the NiP film is diffused to the GaAs substrate side, and a NiGaAs layer of about 150 to 200 nm is formed at the interface between the GaAs substrate and the NiP film.

  Since the above-described NiGaAs layer is formed between the GaAs substrate and the NiP film, the adhesion of the NiP film to the GaAs substrate can be dramatically improved as compared with the case where the NiGaAs layer is not formed. Therefore, when an Au plating layer is formed using a NiP film as a plating power supply layer, a metal plating layer having a small thickness variation and a stable strength can be formed on the GaAs substrate.

  Next, FIG. 7 shows the relationship between the thickness ratio of the NiGaAs layer to the thickness of the NiP film and the amount of warpage of the GaAs substrate. The amount of warpage of the GaAs substrate increases as the film thickness ratio is increased. This is presumably because an increase in the film thickness ratio increases the stress applied to the GaAs substrate. If the amount of warpage of the GaAs substrate increases, it will hinder electrical measurement and assembly processes. For this reason, the amount of warpage of the GaAs substrate needs to be a predetermined amount or less.

  When the amount of warpage of the GaAs substrate that does not affect the electrical measurement or assembly process is 3.0 or less, the film thickness ratio needs to be less than 1.5. In other words, in the manufacturing method described above, by setting the thickness ratio of the NiGaAs layer to the NiP film to be less than 1.5, the adhesion force of the NiP film to the GaAs substrate is improved, and the electrical measurement and assembly processes are hindered. A plating power feeding layer (NiP film) that does not come into contact can be formed.

  Next, FIG. 8 shows the thickness ratio of the NiGaAs layer to the thickness of the NiP film after heat-treating the NiP film at 250 ° C. using the phosphorus concentration (% by weight) of the NiP film formed on the GaAs substrate as a parameter. . As the phosphorus concentration increases, the film thickness ratio decreases. When the phosphorus concentration is 6% (weight%) or more, the film thickness ratio is less than 1.5. Therefore, in the manufacturing method described above, by setting the phosphorus concentration (wt%) in the NiP film to 6% or more, the adhesion of the NiP film to the GaAs substrate is improved, and the electrical measurement and assembly processes are hindered. It is possible to form a plated power feeding layer (NiP film) that does not cause damage.

  In the structure and the manufacturing method of the semiconductor device described above, the example in which the NiP film is formed as the plating power feeding layer of the Au plating layer has been shown. However, the same effect can be obtained by replacing the NiP film with a Ni-based electroless plating layer such as a NiB film.

Sectional drawing which shows the manufacturing method of a semiconductor device. Sectional drawing which shows the manufacturing method of a semiconductor device. Sectional drawing which shows the manufacturing method of a semiconductor device. Sectional drawing which shows the manufacturing method of a semiconductor device. Sectional drawing which shows the manufacturing method of a semiconductor device. The figure which shows the film thickness of the NiP film | membrane and NiGaAs layer after heat processing of a NiP film | membrane. The figure which shows the relationship between the curvature amount of a GaAs substrate, and the film thickness ratio of a NiGaAs layer / NiP film | membrane. The figure which shows the relationship between the film thickness ratio of a NiGaAs layer / NiP film | membrane, and the phosphorus concentration of a NiP film | membrane.

Explanation of symbols

  1 GaAs substrate, 2 via hole receiving metal, 3 via hole, 4 NiP film, 5 NiGaAs layer, 6 Au plating layer.

Claims (4)

  Forming a layer containing Ni in a via hole penetrating the GaAs substrate;
  Diffusing the Ni into the GaAs substrate and forming a NiGaAs layer between the GaAs substrate and the Ni-containing layer;
  Forming a metal plating layer so as to cover the Ni-containing layer in the via hole using the Ni-containing layer as a power feeding layer after forming the NiGaAs layer;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein a heat treatment at 150 to 250 [deg.] C. is performed when forming the NiGaAs layer.   The method of manufacturing a semiconductor device according to claim 1, wherein a film thickness ratio of the NiGaAs layer to the Ni-containing layer is less than 1.5.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the Ni-containing layer is a NiP film, and a phosphorus content in the film is 6 wt% or more. 5. .

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