JP2002190477A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same, in which the resistance value of a via-hole conductor inside a depressed hole of high aspect ratio formed in a semiconductor substrate is reduced, and the via-hole conductor is satisfactorily brought into contact with a backside metal with satisfactory adhesion. SOLUTION: This semiconductor device comprises device-element components 2a, 2b, 3, a through-hole 1b that pierces the semiconductor substrate 1, a base metal layer 5 formed on the surface of the semiconductor substrate and on the sidewall face of the through-hole, an electroplated Cu layer 7 filled inside the through-hole via the underlying metal layer, a wiring metal layer 9 that connects the ground electrodes of the device-element parts to the electroplated Cu layer, and a backside metal layer 11 formed on the backside of the semiconductor substrate to contact the electroplated Cu layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a via hole structure and a method of manufacturing the same, and more particularly, to a semiconductor device having a through hole having a high aspect ratio and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, demand for mobile communication devices such as mobile phones and personal handy phone systems (PHS) has been rapidly expanding, and with this, the operating frequency has changed from the MHz band to GH.
The frequency is increasing toward the z band. Gallium arsenide (GaAs) field effect transistors (FETs) capable of high-gain, low-distortion, and low-current operation even in a high-frequency region are widely used for frequency conversion circuits and signal amplification circuits in reception / transmission sections of these mobile communication devices. Have been.

A GaAs FET is formed on a semi-insulating substrate made of GaAs, is divided into chips by dicing at the time of mounting, and is mounted on a lead frame. A connection is made. However, in such a configuration, there is a problem that the Au wire acts as a parasitic inductance particularly in the operation in a high frequency region, and lowers the gain of the FET.

In order to solve this problem, a structure in which a through hole is formed in a GaAs substrate and an electric connection between a source electrode of a FET and a lead frame is formed using the through hole, that is, a so-called via hole structure has been actively researched and developed. I have. According to this method, the distance between the source electrode and the lead frame can be shortened as compared with the case where the Au wire is used, so that the parasitic inductance is largely suppressed, and a decrease in the gain of the FET can be prevented.

With the miniaturization of mobile communication equipment, GaAs
The downsizing of the FET is indispensable, and the through hole of the via hole needs to be reduced. However, reducing the size of the through hole in the via hole deteriorates the coverage of the wiring metal in the through hole, so that the resistance value of the via hole is increased. As a result, there is a problem that the parasitic inductance increases and the gain of the FET decreases. Was.

In order to solve this problem, Japanese Patent Laid-Open No. 7-193214 discloses a semiconductor device in which a through hole is reduced and a via hole having a large thickness of a low-resistance metal adhered to an inner wall of the through hole is provided. It is disclosed in the gazette.
FIG. 5 is a cross-sectional view illustrating the method of manufacturing the semiconductor device disclosed in the publication. Hereinafter, a method for manufacturing this type of semiconductor device will be described with reference to FIG.

First, as shown in FIG. 5A, an FET having a source electrode 2a, a drain electrode 2b, and a gate electrode 3 is formed on the surface of a GaAs substrate 1. Next, an insulating film 4 is formed, and then a photoresist pattern (not shown) is formed. Then, using this photoresist pattern as a mask, reactive ion etching (RI) is performed on the GaAs substrate 1.
E), the depth is 100 to 120 μm, and the opening width is 5
A concave hole 1a of 0 to 60 μm is formed, and thereafter, the photoresist pattern is removed.

Next, the entire surface of the GaAs substrate 1 including the inner surface of the concave hole 1a is sputtered to form an adhesion layer made of Ti, Cr or Ni having a thickness of 500 ° or less, and a low adhesion layer made of Au having a thickness of about 2000 °. A base metal layer 12 is formed by laminating resistance metal layers in this order.

Subsequently, as shown in FIG. 5B, a photoresist pattern 8 is formed on a portion of the base metal layer 12 other than a portion to be left as a wiring. Next, using the photoresist pattern 8 as a mask and using the underlying metal layer 12 as a catalyst, the exposed portion of the underlying metal layer 12 and the inner surface of the concave hole 1a where the underlying metal layer 12 is not formed are selectively deposited. An electroless Ni-based alloy plating layer 13 of about 5000 ° is formed. Here, the electroless Ni-based alloy plating layer 13 adheres to the surface of the base metal layer 12 and the inner surface of the concave hole 1a with high adhesion.

Next, an electrolytic Au plating layer 9 having a thickness of 3 μm or more is formed on the surface of the electroless Ni-based alloy plating layer 13 using the base metal layer 12 and the electroless Ni-based alloy plating layer 13 as power supply layers for plating. The reason why the electrolytic Au plating method was selected here is that the inner surface of the concave hole 1a can be covered with good coverage, the growth rate is high, a film thickness on the order of microns can be formed, and a wiring pattern with low resistance can be formed.

Next, as shown in FIG. 5C, after the photoresist pattern 8 is removed, a portion disposed below the photoresist pattern 8 of the base metal layer 12 is selected by ion milling or etching. After the removal, a wiring pattern 10a connected to the source electrode 2a is formed from the surface of the GaAs substrate 1 along the inner wall surface of the concave hole 1a. 10b indicates a wiring pattern connected to the drain electrode 2b formed at the same time.

Thereafter, the GaAs substrate 1 is mechanically polished from the back surface side, and as shown in FIG. 5D, a through hole 1b of the GaAs substrate 1 is formed through the concave hole 1a. Thereby, the bottom of the wiring pattern 10a is exposed from the through hole 1b, and the surface of the exposed wiring pattern 10a is
On the back surface of the substrate 1, a back surface metal layer 1 is formed by vapor deposition or plating.
Form one. Thus, through the through hole 1b,
A via hole in which the wiring pattern 10a and the back metal 11 are conducted is obtained.

[0013]

As described above, the method of manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. 7-193214 has a source electrode 2a, a drain electrode 2b, and a gate electrode 3 on the surface of a GaAs substrate 1. After forming the FET, a depth of 100 to 120 μm is formed on the surface of the GaAs substrate 1.
m, a step of forming a concave hole 1a having an opening width of 50 to 60 μm; a step of forming a base metal layer 12 and an electroless Ni-based alloy plating layer 13 on the surface of the GaAs substrate 1 and the inner surface of the concave hole 1a; Metal layer 12 and electroless Ni-based alloy plating layer 1
Electrolyte A 3 connected to a source electrode as a power supply layer for plating
The method includes a step of forming a u-plated layer 9 and a step of mechanically polishing the back surface of the substrate to expose the bottom of the wiring pattern 10a and form the back metal layer 11.

In order to expose the bottom of the wiring pattern 10a from the through hole 1b of the GaAs substrate 1, as shown in FIG. 5D, in accordance with the technique described in JP-A-7-193214, the GaAs substrate 1a Polishing accuracy of 15
Since the thickness is about μm, the thickness of the bottom of the wiring pattern 10a needs to be 20 μm or more. In this case, 5 μm or more can be secured at the bottom after polishing. Here, the polishing accuracy refers to a difference between a maximum and a minimum polishing amount within the same substrate surface or between different substrates, which is actually obtained by polishing with a predetermined polishing amount. The bottom of the wiring pattern 10a is approximately 2
500 下地 underlying metal layer 12 and about 5000 無 electroless Ni
It is composed of the system alloy plating layer 13 and the electrolytic Au plating layer 9, and the electrolytic Au plating layer 9 occupies most of the thickness. The thickness must be 20 μm or more.

However, even if the electrolytic Au plating layer 9 is formed in the concave hole 1a with a thickness of 20 μm or more, the thickness of the diffusion layer of the reactive species is different between the surface and the bottom of the concave hole 1a. The plating growth rate at the bottom is lower than the plating growth rate at the surface of the concave hole 1a.
As shown in FIG. 5, a void is formed in a state where the surface of the electrolytic Au plating layer 9 is closed. This phenomenon occurs remarkably when the aspect ratio of the concave hole 1a is high. For example, in the above example, the depth is 100 to 120 μm, and the opening width is 50 to 60 μm.
In the case of the m-shaped concave hole 1a, when the plating thickness at the bottom of the electrolytic Au plating layer 9 has grown to 10 μm, the plating thickness at the surface of the electrolytic Au plating layer 9 has grown to 30 μm. A void having a closed surface is formed, and the plating growth at the bottom of the electrolytic Au plating layer 9 is 10 μm.
Stop at

As described above, in the above example, the film thickness at the bottom of the wiring pattern 10a is limited to 10 μm,
Polishing accuracy of the back surface of the GaAs substrate 1a is about 15 μm. Therefore, when the back surface of the GaAs substrate 1 is polished to form the through hole 1b, there is a high possibility that the bottom of the wiring pattern 10a will be lost. After that, the back metal 11 is formed, and the wiring pattern 10 that contacts the back metal 11 is formed.
The contact surface a is only a metal side wall layer having a thickness of 10 μm or less as shown in FIG. 7, which causes an increase in resistance component and a decrease in adhesive strength at the contact surface. As a result, G
Wiring pattern 10a on aAs substrate 1a and back metal layer 1
1 (hereinafter referred to as the resistance value of the via hole) increases to 4 to 10 mΩ, causing a problem of increasing the parasitic inductance and decreasing the gain of the FET.

Further, since the bonding strength between the back metal 11 and the wiring pattern 10a is low, a via hole open defect occurs in reliability such as a temperature cycle.

The present invention has been made to solve the above-described problems, and has the object of reducing the resistance value of a via hole formed on the inner surface of a high aspect ratio concave hole formed in a semiconductor substrate.
It is another object of the present invention to provide a semiconductor device in which a via hole is in close contact with a back metal and a method for manufacturing the same.

[0019]

According to the present invention, there is provided a semiconductor device comprising:
An element portion formed on the surface of the semiconductor substrate, a through hole penetrating the semiconductor substrate, a base metal layer formed on the surface of the semiconductor substrate and a side wall surface of the through hole, and filling the through hole with the base metal layer And a wiring metal layer connecting the ground electrode of the element portion and the electrolytic Cu plating layer, and a back metal layer formed on the back surface of the semiconductor substrate by connecting to the electrolytic Cu plating layer.

According to another aspect of the present invention, there is provided a semiconductor device formed on a surface of a semiconductor substrate, a through hole penetrating the semiconductor substrate, and a surface of the semiconductor substrate including the element portion and a side wall surface of the through hole. Base metal layer, an electrolytic Au plating layer formed on the surface of the base metal layer by being connected to the ground electrode of the element portion, and an electrolytic Cu plating layer filled in the through holes via the base metal layer and the electrolytic Au plating layer. And electrolytic Cu on the back surface of the semiconductor substrate.
A back metal layer formed in connection with the plating layer.

According to any one of the above structures, the resistance of the via hole formed in the through hole can be sufficiently reduced. That is, it is easy to form the electrolytic Cu plating layer with a sufficient thickness from the bottom for the hole having a high aspect ratio. Therefore, the electrolytic C
When the u-plated layer is filled and the back surface of the semiconductor substrate is polished into a through hole, the electrolytic C
It is possible to secure a sufficient thickness of the u plating layer.
Further, since the back metal is in contact with the entire surface of the electrolytic Cu plating layer exposed on the back surface, the adhesion strength is improved, and the reliability such as a temperature cycle is improved.

In any one of the above structures, the through hole may
The opening width can be 10 to 60 μm and the aspect ratio can be 0.5 to 4.

In any of the above structures, the electrolytic Cu plating layer is filled with a thickness of 20 μm or more from the bottom of the through hole. Preferably, it is filled with a thickness of 35 μm or more. Then, the semiconductor substrate is mechanically polished from the back side,
In the step of exposing the electrolytic Cu plating layer from the back surface of the semiconductor substrate, the thickness of the exposed portion of the electrolytic Cu plating layer after the back surface polishing should remain at least 20 μm even if the accuracy of polishing the back surface of the semiconductor substrate is 15 μm. become. Thereby, for example, when a via hole is formed in a through hole having a depth of 100 μm and an opening width of 50 μm, the resistance value of the via hole becomes 2 mΩ or less, the parasitic inductance is suppressed, and the FE
The gain of T is improved by 2-3 dB.

In this configuration, the electrolytic Cu plating layer is
It is provided on the inner surface of the through hole and its peripheral portion, and is preferably formed with a thickness of 10 μm or less on the surface of the semiconductor substrate.

In any one of the above structures, the base metal layer may include an adhesion layer made of Ti or Cr in close contact with the side wall surface of the through hole, and a barrier layer made of Ni or Pt laminated on the adhesion layer. And a low-resistance metal layer made of Au or Cu laminated on the barrier layer. According to this configuration, the adhesion layer improves the adhesion with the concave hole. The barrier layer is formed of Au,
This prevents a low-resistance metal layer such as Cu from diffusing into the semiconductor substrate. The low-resistance metal layer is formed of Au,
This has the function of uniformly forming an electrolytic plating layer of Cu or the like on the wafer surface.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming an element portion on a surface of a semiconductor substrate, a step of selectively forming a concave hole from the surface of the semiconductor substrate, a step of forming a concave hole from the surface of the semiconductor substrate, A step of forming a base metal layer on the inner surface, a step of filling the concave hole with an electrolytic Cu plating layer via the base metal layer, and a step of forming a wiring metal layer connecting the ground electrode of the element portion and the electrolytic Cu plating layer. A step of reducing the thickness of the semiconductor substrate from the back surface to expose the electrolytic Cu plating layer on the back surface, and a process of forming a back metal layer on the back surface of the semiconductor substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an element portion on a surface of a semiconductor substrate; forming a concave hole selectively from the surface of the semiconductor substrate; Forming a base metal layer on the inner surface of the concave hole, forming an electrolytic Au plating layer on the surface of the base metal layer so as to be connected to the ground electrode of the element portion, and forming the base metal layer and the electrolytic Au on the concave hole. Filling the electrolytic Cu plating layer via the plating layer, thinning the semiconductor substrate from the back surface to expose the electrolytic Cu plating layer on the back surface, and forming a back metal layer on the back surface of the semiconductor substrate And a step.

According to any one of the above methods, the resistance of the via hole formed in the through hole can be sufficiently reduced. That is, it is easy to form the electrolytic Cu plating layer with a sufficient thickness from the bottom for the hole having a high aspect ratio. Therefore, after filling the inner surface of the concave hole of the semiconductor substrate with the electrolytic Cu plating layer and polishing the back surface of the semiconductor substrate to expose the electrolytic Cu plating layer, within the range of general polishing accuracy, the electrolytic Cu plating layer Can secure a sufficient thickness.

Preferably, in any of the above methods,
In the step of forming the electrolytic Cu plating layer, a plating solution used for electrolytic plating is a copper sulfate plating solution containing a polymer surfactant and an additive of a sulfur compound. Copper sulfate plating solutions containing these additives are widely used for through-hole plating of printed wiring boards and micro-via plating of build-up printed wiring boards. The polymer surfactant has a function of suppressing the growth of plating on the surface of the microvia, and the sulfur compound has a function of promoting the growth of plating on the bottom of the microvia. By adding these two types of additives to the copper sulfate plating solution, it becomes easy to fill and fill a micro via having an opening width of 80 to 150 μm and an aspect ratio of about 1. That is, in the step of forming a base metal layer on the surface of the semiconductor substrate and the inner surface of the concave hole, and performing electrolytic Cu plating on the surface of the semiconductor and the concave hole using the base metal layer as a power supply layer, the bottom of the concave hole has plating growth. It is promoted and plating growth is suppressed on the semiconductor substrate. Therefore, the bottom of the concave hole can be grown to a thickness of, for example, 35 μm or more, and the thickness on the semiconductor substrate can be suppressed to, for example, 10 μm or less.

Preferably, in any of the above methods,
In the step of forming the electrolytic Cu plating layer, the plating solution used for the electrolytic plating is an electrolytic plating solution having a copper concentration of 25 to 75 g / L.

As a copper sulfate plating solution used for through-hole plating of a printed wiring board, a low copper concentration electrolytic plating solution having a copper concentration of 15 to 25 g / L called a high-throw bath emphasizing uniform electrodeposition is used. . However, in a high throw bath, a via hole according to the invention, for example a depth of 10
When electrolytic plating is performed on a concave hole having a diameter of 0 μm and an opening width of 50 μm, the plating growth rate is extremely slow, and a processing time of 4 hours is required to fill the electrolytic Cu plating layer, which has a problem in productivity. Therefore, in order to increase the electrolytic current value of the plating solution used for electrolytic plating, when the copper concentration is increased to 25 to 75 g / L, the electrolytic Cu plating layer is filled in a concave hole having a depth of 100 μm and an opening width of 50 μm. Processing time is 2
Time was reduced. Therefore, by this configuration, the inner surface of the concave hole having a high aspect ratio formed from the surface of the semiconductor substrate,
The electrolytic Cu plating layer can be filled in a short time, and the productivity is improved.

Preferably, in any of the above methods,
In the step of forming an electrolytic Cu plating layer, plating is performed by gradually reducing the electrolytic current value of electrolytic plating.

Since the microvias of the build-up method printed wiring board have an aspect ratio of about 1, the electrolytic current value during plating can be fixed and the microvias can be filled. On the other hand, for example, when electrolytic Cu plating is performed with a fixed electrolytic current value in a concave hole having a depth of 100 μm and an opening width of 50 μm and an aspect ratio of 2,
As the concave Cu is filled with the electrolytic Cu plating layer, the electrolytic C
Since the surface area of the u-plated layer decreases, the current density increases, and the smoothness function of the additive does not work, and voids are generated. Therefore, in the method of the present invention, in order to control the current density of the electrolytic Cu plating within a certain range, a plating method in which the electrolytic current value is reduced stepwise is used. With this configuration, the inner surface of the concave hole having a high aspect ratio of 1 to 4 formed from the surface of the semiconductor substrate can be filled with the electrolytic Cu plating layer with high smoothness.

[0034]

(Embodiment 1) FIGS. 1 and 2
FIG. 5 is a sectional view illustrating the method of manufacturing the semiconductor device in the first embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 5 indicate the same or corresponding parts.

Hereinafter, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG. First, as shown in FIG. 1A, an FET having a source electrode 2a, a drain electrode 2b, and a gate electrode 3 is formed on the surface of a GaAs substrate 1.
Next, an insulating film 4 is formed, and then a photoresist pattern (not shown) is formed. Then, using this photoresist pattern as a mask, the GaAs substrate 1 is subjected to dry etching by inductively coupled plasma (ICP), A concave hole 1a having a thickness of 100 μm and an opening width of 50 μm is formed, and thereafter, the photoresist pattern is removed. Next, the entire surface of the GaAs substrate 1 including the inner surface of the concave hole 1a is sputtered with an adhesion layer made of Ti or Cr having a thickness of about 1000Å and a thickness of 2000Å.
A barrier layer of Ni or Pt with a thickness of 20
A base metal layer 5 is formed by laminating a low resistance metal layer made of Au or Cu of about 00 ° in this order.

Subsequently, as shown in FIG. 1B, a photoresist pattern 6 is formed on a portion of the base metal layer 5 other than the portion to be filled with the concave hole, and then the photoresist pattern 6 is used as a mask. Using the underlying metal layer 5 as a power supply layer, an electrolytic Cu plating layer 7 is formed on the surface of the underlying metal layer 5 to a thickness of 35 μm or more at the bottom of the concave hole 1a.
It is formed so as to be deposited on the s substrate 1 with a thickness of 10 μm or less. In addition, the thickness of the electrolytic Cu plating layer 7 at the bottom of the concave hole 1a may be 20 μm or more if only the polishing accuracy when mechanically polishing the semiconductor substrate from the back surface side is considered, but is 35 μm or more as described above. Then, the actual process can be easily performed and is more realistic. Here, the plating solution used for the electrolytic Cu plating is a copper sulfate plating solution containing a polymer surfactant and an additive of a sulfur compound, and the copper concentration is adjusted to 25 to 75 g / L. Further, the electrolytic current value of the electrolytic Cu plating was 0.9 μA per concave hole 1a,
Continuous plating is performed for 40 minutes while changing the order of 0.6 μA and 0.3 μA.

Incidentally, in the prior art of Japanese Patent Application Laid-Open No. 7-193214, in order to uniformly form the electrolytic Au plating layer 9 corresponding to the electrolytic Cu plating layer 7 of the present embodiment on the inner surface of the concave hole 1a, it is necessary to use Although the power supply layer for plating is formed by using the base metal layer 12 made of a low-resistance metal and the electroless Ni-based alloy plating layer 13, the base metal layer 5 of the present embodiment is formed by sputtering conditions of each metal layer. And by optimizing the film thickness, the inner surface of the concave hole 1a is uniformly covered,
As the power supply layer for forming the electrolytic Cu plating layer 7, only the base metal layer 5 is sufficient.

Next, after removing the photoresist pattern 6, as shown in FIG. 1C, a photoresist pattern 8 is formed on a portion of the base metal layer 5 other than a portion to be left as a wiring. Next, using the photoresist pattern 8 as a mask, the underlying metal layer 5 as a power supply layer,
An electrolytic Au plating layer 9 having a thickness of about 5 μm is formed on the surface and the surface of the electrolytic Cu plating layer 7.

Further, as shown in FIG. 2D, after removing the photoresist pattern 8, the underlying metal layer 5 exposed on the GaAs substrate 1 is selectively removed by ion milling or etching. Thereby, the GaAs substrate 1
Base metal layer 5 formed on the surface and on the inner surface of concave hole 1a
And the electrolytic C filled in the concave hole 1a via the base metal 5.
A wiring pattern 10a connected to the source electrode 2a is formed of the u plating layer 7 and the electrolytic Au plating layer 9 formed on the surface of the GaAs substrate 1 and the electrolytic Cu plating layer 7.

In the present embodiment, the wiring pattern 1
As an example of the formation of the Oa layer, the case where the electrolytic Au plating layer 9 formed by the electrolytic Au plating method is used has been described. However, instead of this, an Au film is formed by vapor deposition or sputtering, and the Au film is patterned and interconnected. It may be a pattern. At this time, the wiring pattern can be formed regardless of the position of the power supply layer.

Thereafter, as shown in FIG.
The substrate 1 is mechanically polished from the back side to penetrate the concave hole 1a to form a through hole 1b. Thereby, the wiring pattern 10
The bottom of a is exposed from the through hole 1b, and a back metal layer 11 is formed on the exposed surface of the wiring pattern 10a and the back of the GaAs substrate 1 by vapor deposition or plating. In this way, a via hole in which the wiring pattern 10a and the back metal layer 11 as the back wiring are conducted through the through hole 1b is obtained.

(Embodiment 2) FIGS. 3 and 4 are sectional views showing steps of a method for manufacturing a semiconductor device according to Embodiment 2 of the present invention. In the figure, the same reference numerals as those in FIG. 5 indicate the same or corresponding parts.

Hereinafter, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG. First, as shown in FIG. 3A, an FET having a source electrode 2a, a drain electrode 2b, and a gate electrode 3 is formed on the surface of a GaAs substrate 1.
Next, an insulating film 4 is formed, and then a photoresist pattern (not shown) is formed. Then, using this photoresist pattern as a mask, the GaAs substrate 1 is subjected to dry etching by inductively coupled plasma (ICP) to form a A concave hole 1a having a thickness of 100 μm and an opening width of 50 μm is formed, and thereafter, the photoresist pattern is removed. Next, the entire surface of the GaAs substrate 1 including the inner surface of the concave hole 1a is sputtered with an adhesion layer made of Ti or Cr having a thickness of about 1000Å and a thickness of 2000Å.
A barrier layer of Ni or Pt with a thickness of 20
A base metal layer 5 is formed by laminating a low resistance metal layer made of Au or Cu of about 00 ° in this order.

Subsequently, as shown in FIG. 3B, after a photoresist pattern 8 is formed on a portion of the underlying metal layer 5 other than a portion to be left as a wiring, the photoresist pattern 8 is used as a mask to form the underlying metal layer. Using the layer 5 as a power supply layer, an electrolytic Au plating layer 9 having a thickness of about 5 μm is formed on the surface of the base metal layer 5.

Next, as shown in FIG. 3 (c), after the photoresist pattern 8 is removed, the photoresist pattern is formed on the recessed hole 1a to be filled with the electrolytic Cu plating layer in the next step and on the portion other than the periphery thereof. 6 is formed. Next, using the photoresist pattern 6 as a mask, and using the underlying metal layer 5 as a power supply layer, an electrolytic Cu plating layer 9 is formed on the surface of the electrolytic Au plating layer 9.
The plating layer 7 is formed at the bottom of the concave hole 1a with a thickness of 35 μm or more, and is formed on the GaAs substrate 1 so as to be deposited at a thickness of 10 μm or less. Here, the plating solution used for the electrolytic Cu plating is a copper sulfate plating solution containing a polymer surfactant and an additive of a sulfur compound, and the copper concentration is 2%.
Adjust to 5 to 75 g / L. Further, at the time of electrolytic Cu plating, the electrolytic current value per one concave hole 1a is 0.9 μm.
A, 0.6 μA and 0.3 μA are sequentially changed, and continuous plating is performed for 40 minutes each.

After removing the photoresist pattern 6,
As shown in FIG. 4D, the underlying metal layer 5 exposed on the GaAs substrate 1 by ion milling or etching.
Is selectively removed. Thereby, the base metal layer 5 and the electrolytic Au plating layer 9 formed on the surface of the GaAs substrate 1 and the inner surface of the concave hole 1a and the electrolytic Cu plating layer 7 filled in the concave hole 1a via the electrolytic Au plating layer 9 are formed. The wiring pattern 10a connected to the source electrode 2a is formed.

Thereafter, as shown in FIG.
The substrate 1 is mechanically polished from the back side to penetrate the concave hole 1a to form a through hole 1b. Thereby, the wiring pattern 10
The bottom of a is exposed from the through hole 1b, and a back metal layer 11 is formed on the exposed surface of the wiring pattern 10a and the back of the GaAs substrate 1 by vapor deposition or plating. In this way, a via hole in which the wiring pattern 10a and the back metal layer 11 as the back wiring are conducted through the through hole 1b is obtained.

With the above configuration, the resistance value of the via hole is reduced from 4 to 10 mΩ to 2 mΩ or less. As a result, the parasitic inductance is suppressed and the
Is improved by 2 to 3 dB.

[0049]

According to the present invention, a high-aspect-ratio through-hole selectively formed from the surface of a semiconductor substrate has a via hole filled with an electrolytic Cu plating layer, which is a low-resistance metal, with high smoothness. A semiconductor device is configured, the opening of the through hole can be reduced, and the size of the semiconductor element can be reduced. In addition, since the electrolytic Cu plating layer, which is a low-resistance metal, can be formed in the through hole with a sufficient thickness, the resistance value of the via hole is reduced, and as a result, the parasitic inductance is suppressed and the gain is improved. Furthermore, since the electrolytic Cu plating layer filled in the through hole and the back metal are in good contact with each other, the reliability of the via hole due to the temperature cycle is improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing the step following FIG.

FIG. 3 is a sectional view illustrating each step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 4 is a sectional view showing the step following FIG. 3 by step;

FIG. 5 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

FIG. 6 is a diagram illustrating a conventional electrolytic method A for manufacturing a semiconductor device.
Sectional view for explaining the problem of the u plating layer

FIG. 7 is a cross-sectional view for explaining a problem of a wiring pattern in a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 GaAs substrate 1a concave hole 1b through hole 2a source electrode 2b drain electrode 3 gate electrode 4 insulating film 5 base metal layer 6 photoresist pattern 7 electrolytic Cu plating layer 8 photoresist pattern 9 electrolytic Au plating layer 10a wiring pattern 10b wiring pattern 11 Back metal layer 12 Base metal layer 13 Electroless Ni-based alloy plating layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) GC01 GD01 GJ05 HC11 HC16 HC30

Claims (11)

[Claims] An element portion formed on a surface of the semiconductor substrate; a through hole penetrating the semiconductor substrate; a base metal layer formed on a surface of the semiconductor substrate and a side wall surface of the through hole; An electrolytic Cu plating layer in which holes are filled through the base metal layer, a ground electrode of the element portion, and the electrolytic C
A semiconductor device comprising: a wiring metal layer connected to a u-plate layer; and a back metal layer formed on the back surface of the semiconductor substrate by connecting to the electrolytic Cu plating layer. 2. An element portion formed on a surface of a semiconductor substrate, a through hole penetrating the semiconductor substrate, a base metal layer formed on a surface of the semiconductor substrate including the element portion and a side wall surface of the through hole. And an electrolytic Au plating layer formed on the surface of the underlying metal layer by connecting to a ground electrode of the element portion; and electrolytic Cu plating filled in the through hole via the underlying metal layer and the electrolytic Au plating layer. A semiconductor device comprising: a layer; and a back metal layer formed on the back surface of the semiconductor substrate so as to be connected to the electrolytic Cu plating layer. 3. The through hole has an opening width of 10 to 60 μm.
3. The semiconductor device according to claim 1, wherein m and the aspect ratio are 0.5 to 4. 4. The semiconductor device according to claim 1, wherein the electrolytic Cu plating layer is filled with a thickness of 20 μm or more from the bottom of the through hole. 5. The semiconductor device according to claim 1, wherein the electrolytic Cu plating layer is provided on an inner surface of the through hole and a peripheral portion thereof, and is formed with a thickness of 10 μm or less on the surface of the semiconductor substrate. 5. The semiconductor device according to 4. 6. The base metal layer includes: an adhesion layer made of Ti or Cr in close contact with a side wall surface of the through hole; a barrier layer made of Ni or Pt laminated on the adhesion layer;
3. A low-resistance metal layer made of Au or Cu laminated on the barrier layer.
3. The semiconductor device according to claim 1. 7. A step of forming an element portion on a surface of a semiconductor substrate, a step of selectively forming a concave hole from the surface of the semiconductor substrate, and a step of forming a base metal layer on the surface of the semiconductor substrate and an inner surface of the concave hole. Forming a hole, filling the concave hole with an electrolytic Cu plating layer via the base metal layer, and forming a wiring metal layer connecting the ground electrode of the element portion and the electrolytic Cu plating layer. A step of reducing the thickness of the semiconductor substrate from the back surface to expose the electrolytic Cu plating layer on the back surface, and a step of forming a back metal layer on the back surface of the semiconductor substrate. A method for manufacturing a semiconductor device. 8. A step of forming an element portion on the surface of the semiconductor substrate, a step of selectively forming a concave hole from the surface of the semiconductor substrate, and a step of forming a base metal layer on the surface of the semiconductor substrate and the inner surface of the concave hole. Forming an electrolytic Au plating layer on the surface of the underlying metal layer so as to be connected to the ground electrode of the element portion; and forming the concave hole through the underlying metal layer and the electrolytic Au plating layer via the underlying metal layer and the electrolytic Au plating layer. Filling the electrolytic Cu plating layer with a metal substrate, thinning the semiconductor substrate from the back surface to expose the electrolytic Cu plating layer on the back surface, and forming a back metal layer on the back surface of the semiconductor substrate. And a method for manufacturing a semiconductor device. 9. The plating solution used for electrolytic plating in the step of filling the electrolytic Cu plating layer is a copper sulfate plating solution containing a polymer surfactant and an additive of a sulfur compound. 9. The method for manufacturing a semiconductor device according to 7 or 8. 10. The plating solution used for the electrolytic plating in the step of filling the electrolytic Cu plating layer is an electrolytic plating solution having a copper concentration of 25 to 75 g / L. Of manufacturing a semiconductor device. 11. The method according to claim 7, wherein, in the step of filling the electrolytic Cu plating layer, plating is performed by gradually decreasing an electrolytic current value of the electrolytic plating.
The manufacturing method of the semiconductor device described in the above.