JP2002526663A - Submicron metallization using electrochemical deposition - Google Patents

Abstract

Methods for depositing a metal into a micro-recessed structure in the surface of a microelectronic workpiece are disclosed. The methods are suitable for use in connection with additive free as well as additive containing electroplating solutions. In accordance with one embodiment, the method includes making contact between the surface of the microelectronic workpiece and an electroplating solution in an electroplating cell that includes a cathode formed by the surface of the microelectronic workpiece and an anode disposed in electrical contact with the electroplating solution. Next, an initial film of the metal is deposited into the micro-recessed structure using at least a first electroplating waveform having a first current density. The first current density of the first electroplating waveform is provided to enhance the deposition of the metal at a bottom of the micro-recessed structure. After this initial plating, deposition of the metal is continued using at least a second electroplating waveform having a second current density. The second current density of the second electroplating waveform is provided to assist in reducing the time required to substantially complete filling of the micro-recessed structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Cross reference with related applications]

This application claims priority by US application Ser. No. 60/103061, "Submicron Copper Metallization by Electrochemical Deposition," filed Oct. 5, 1998, incorporated herein by reference.

[0002]

[Statement regarding research or development with federal support]

 Not applicable.

[0003]

BACKGROUND OF THE INVENTION

An integrated circuit is an interconnected collection of elements formed in a semiconductor material and in an insulating material on the surface of the semiconductor material. Elements that can be formed in semiconductor materials include:
Includes MOS transistors, bipolar transistors, diodes and diffusion transistors. Devices that can be formed in the insulating material include thin film resistors and capacitors. Typically, 100 or more integrated circuit dies (IC chips) have a diameter of 20
Constructed on 3.2 mm (8 inch) silicon wafer. The elements used in each die are connected to each other by conductor paths formed in the insulator. Typically, two or more subsequent levels of conductor paths separated by insulating layers are used for interconnection. At present, aluminum alloys and silicon oxides are typically used in practice as conductors and insulators, respectively.

[0004] Delays in the propagation of electrical signals between elements on a single die limit the performance of integrated circuits. More specifically, these delays limit the speed at which the integrated circuit processes electrical signals. Large propagation delays reduce the speed at which the integrated circuit can process electrical signals, while small delays increase this speed. Therefore, integrated circuit manufacturers seek ways to reduce propagation delays.

[0005] For each interconnect path, the signal propagation delay can be characterized by a time delay τ. E. FIG. H. Stevens, Interconnect Techn
ology, QMC, Inc. , July 1993. As for the signal transmission between the transistors of the integrated circuit, an approximate expression of the time delay τ is given by:

Τ = RC [1+ (V_SAT/ RI_SATWhere R and C are the equivalent resistance and capacitance of the interconnect path, respectively. _SAT And V_SATAre the transistors that apply signals to the interconnect paths.
The maximum (saturated) current, and the drain-source voltage when current saturation occurs
is there. The resistance of the path is proportional to the specific resistance ρ of the conductive material. The path capacitance is
Relative permittivity K_eIs proportional to The small value of τ is the ratio V_SAT/ RI_SATTo reduce
Requires that the interconnect lines carry a sufficiently high current density. Therefore, this
Low ρ conductors and low K that can deliver high current densities in manufacturing high performance integrated circuits. _e Insulation should be used.

In order to meet the above criteria, the most preferred interconnect structure, the interconnect line at a lower K _e insulating body copper is replaced with a line of silicon oxide insulating body of the aluminum alloy. Copper Gose Mainstream: Low-
k to Follow, Semiconductor International
nal, Nov .; 1997 pp. See 67-70. The specific resistance of the copper thin film is in the range of 1.7 to 2.0 μΩcm, while the specific resistance of the aluminum alloy is high, 3.0.
To 3.5 μΩcm.

[0008] Despite the advantageous properties of copper, several issues must be addressed for copper interconnects to mature in mass production.

[0009] Copper diffusion is one such problem. Under the influence of an electric field, and only at moderately high temperatures, copper moves rapidly through silicon oxide. It is also believed that copper moves rapidly through the low _Ke insulator. Such copper diffusion causes failure of devices formed in the silicon.

Another problem is the property of copper that readily oxidizes when immersed in an aqueous solution or exposed to an oxygen-containing atmosphere. The oxidized surface of the copper is rendered non-conductive, thereby limiting the current carrying capacity of a given conductive path when compared to a non-oxidized copper path of similar dimensions.

[0011] Yet another problem with the use of copper in integrated circuits is the difficulty in using copper in multilayer integrated circuit structures with insulating materials. Using traditional copper deposition methods, copper adheres only very weakly to the insulating material.

Finally, direct plasma etching of copper cannot be used in copper fine line patterning because copper does not form volatile halide compounds. Therefore,
Copper is difficult to use in the increasingly smaller geometries required for advanced integrated circuit devices.

The semiconductor industry has addressed some of the above issues and has adopted a common standard interconnect architecture for copper interconnects. For this purpose, the industry has etched trenches and vias in the insulator, filled the trenches and vias with a deposit of copper, and by chemical-mechanical polishing (CMP) above the top surface of the insulator. To achieve copper fine line patterning by removing the copper from the copper. To implement such an architecture and thereby form copper lines in the insulator, an interconnect architecture called a dual damascus architecture can be used. FIG. 1 illustrates the steps of a process generally required to implement a dual Damascus architecture.

High aspect ratio (depth / diameter) vias and high aspect ratio (depth / width)
It is difficult to deposit a thin and uniform barrier and seed layer in the trench. The upper portions of such channels and vias tend to pinch off before each channel and / or via is completely filled or layered with the desired material.

[0015] The electrodeposition of copper metallization has been found to be the most effective method of depositing copper in trenches and vias. This method provides the best electrical transfer (ele
ctromigration) has been found to provide resistive performance. However, this copper electrodeposition method is not without its own problems. For example, acidic copper plating solutions for copper interconnects often include organic additives to improve throwing power, enhance planarization effects, and provide proper deposition characteristics. Since such additives play an important role in copper plating, the concentrations of these additives in the plating solution must be tightly controlled to ensure consistent groove filling and thin film properties. The inventor has recognized that it is desirable to use a plating solution without additives to improve solution management, thereby eliminating the need for monitoring additive concentrations. In addition, it has been recognized that some plating properties should be optimized, even in the presence of such additives.

[0016]

Summary of the Invention

The inventor has found that the application of metallization using low current density plating corrugations, particularly copper metallization, provides better groove and via fill results as compared to high current density plating corrugations. Was. This is because when a plating solution without additives is used,
Especially true. However, with such a low current density plating waveform, formation of a metal thin film having a required thickness is often very slow. Therefore, use a low current density plating waveform during the initial plating operation and, after the first plating operation is completed, to reduce the fill time and to provide a different thin film morphology if desired. A current density plating waveform is used.

According to one embodiment of the present invention, the waveform and its frequency are used to influence the surface morphology of the copper metallization deposition. In addition, high metal concentrations in the plating solution without additives are used to more effectively fill the groove and via structure.

The inventor has found that with respect to plating solutions containing additives, the use of a low metal concentration plating solution can optimize the plating process. Such a liquid produces a higher quality filling of the trenches and vias as compared to copper metallization deposited using a liquid having a high metal concentration.

A method is disclosed for depositing a metal within a micro-recess structure of a microelectronic circuit workpiece. The method is suitable for use in connection with additive-free and additive-containing electroplating solutions. According to one embodiment, the method includes the steps of providing a microelectronic circuit in an electroplating vessel having a cathode formed by a surface of a microelectronic circuit workpiece and an anode disposed in electrical contact with an electroplating solution. Contacting between the surface of the circuit workpiece and the electroplating solution. Next, an initial thin film of metal is deposited in the micro-recess structure using at least a first electroplating waveform having a first current density. A first current density of a first electroplating waveform is provided to enhance metal deposition at the bottom of the microrecess structure. After this initial plating, metal deposition is continued using at least a second electroplating waveform having a second current density. Subsequently, a second current density of the second electroplating waveform is provided to assist in reducing the time required for complete filling of the micro-recess structure.

[0020]

[Detailed description]

The present invention can be understood with reference to the experiments disclosed herein. Although the experiments were performed in connection with the plating of metals, including copper, it will be appreciated that the teachings disclosed herein are equally applicable to electroplating other metals. All experiments were performed on 200 mm wafers using plating tools such as those available from Semitool Inc., Carispell, Montana. Three plating solutions were tested. The first, solution 1 (either 24 g / L or 36 g / L copper), is free of organic additives. Solution 2 (Additive A) and Solution 2 (Additive B)
Contains organic additives from different vendors.

For copper concentrations between 15 and 36 g / L, good trench filling was obtained at current densities as low as 4 mA / cm ² . It is believed that due to the low concentration polarization, a high degree of microscopic throwing power at low current densities may be responsive to filling such trenches at high copper concentrations. FIG. 1 shows a scanning electron microscope (SE) obtained from a solution 1 of 24 g / L copper.
M) shows a cross section. Void-free filling was obtained for grooves having a width of 0.5 μm and an aspect ratio of 2: 1. The waveform used was a forward pulse (WF1) with 1 ms on and 1 ms off. This waveform was found to be insignificant for filling as long as the current density was low. As can be seen from FIG. 1, at 4 mA / cm ² , rough or large particles are observed, which means that particle growth is the fundamental mechanism for deposition, as opposed to the formation of new nuclei. As shown in FIG. 2, the copper deposition becomes smoother at higher current densities (40 mA / cm ² ). However, the filling at this high current was not good and seam voids were found in the grooves.

In view of the characteristics of the low and high current density waveforms, the inventors combine such waveforms within one electroplating process, thereby exploiting the benefits associated with each waveform to make it commercially viable. It has been found to provide a submicron electroplating process that matches the process characteristics (void filling and filling time) required for this. For this purpose,
During the first stage of the trench and / or via filling step in the process, an electroplating corrugation having a low current density is used. At some time following this first step, the electroplating waveform is converted to a higher current density waveform to complete the electroplating process and reduce the total time required for the process.

To understand how copper deposits inside trenches and vias leads to increased deposition at different current densities and thicknesses expressed in amp-minutes (A-min). Was. The results are compared in FIGS. 3 (a)-(d). Large particles were observed at low current densities (FIGS. 3A and 3B). 1.26A-mi thickness
Increasing from n to 3.78 A-min enhanced the growth at the bottom of the trench, possibly explaining why good packing was obtained at the low current density of FIG. Thus, low current density values should be chosen to provide enhanced growth of the copper metallization layer in the lower portion of the feature where the copper metallization is to be deposited. At high current densities (40 mA / cm ² , FIGS. 3 (c) and (d)), the deposition is smooth and adapts very well. Compared to FIG. 2 where seam voids were observed, conformal plating is not sufficient to guarantee void-free as the top portion of the groove is often pinched off first leaving a void inside. .

The seam voids shown in these figures are believed to result from overplating of the copper deposits on top of features due to high current distribution. It is expected that overplated copper will be preferentially removed if the waveform includes a reverse pulse. However, the addition of a reverse pulse does not improve groove filling, as shown in FIG. 4, where seam voids are still observed even in the case of pulse reverse waveforms.

Therefore, if a solution without additives is used, an initial low current density approach is required. The initial low current, in addition to good filling of the trench, is useful for improving contact with the seed layer, especially when the seed layer is very thin. However, the disadvantage of low current is that the process time is long. To avoid this, a low current plating waveform is used to fill small features and possibly enhance the seed layer,
A multi-step plating method in which high currents are then used to complete the process and provide a smooth surface for one or more subsequent CMP processes is preferred.

[0026] Figure 5 shows the resulting cross-section through the two-stage waveform of 32 mA / cm ² followed this with 4mA / cm ^2. An improvement in gap filling was observed. Using the same two-step waveform, increasing the concentration of copper (36 g / L) as shown in FIG. 6 provides a significant improvement in the filling process.

The effect of copper concentration on gap filling for acidic solutions with additives was tested using Solution 2 described above. FIG. 7 shows a metallized track plated from such a solution using a 20 mA / cm ² one-step waveform. FIG. 8 shows that the amount of copper in the solution was 20 g / L.
In this case, the cross section was obtained at 20 mA / cm ² . Although the surface of the deposition was smooth, voids were observed in the grooves at this copper concentration, as in solution 3. As the copper concentration dropped from 20 g / L to 10 g / L, no voids were observed as in FIG. Good gap filling at low concentrations of copper in the presence of organic additives is different from that obtained for solutions without additives where high concentrations of copper provide good gap filling. This implies a different governing mechanism for copper growth in the presence of additives. It has been found that the reversal of the pulses, like those obtained from the solution without additives, creates voids and rough surfaces in this solution with additives.

FIGS. 10A to 10C show the effect of the seed layer on gap filling. If the top of the feature is pinched off before filling is complete, a central void (FIG. 10a) is formed. Due to the line-of-sight deposition inherent in the PVD process, overhanging of the seed layer at the top of the feature is often the main reason for the central void, and furthermore, insufficient suppression of copper growth at the top of the trench during plating. Another reason. The former requires optimization of the PVD process to deposit a conformable layer, possibly with the PVD process and C
It would require a combination with another technique such as electrochemical plating for VD or small features. The latter requires optimization of the plating process by changing the components of the solution and the plating waveform.

The bottom and sidewall voids (FIG. 10b) are mainly due to poor seed layer coverage. If the wafer is exposed to air, copper oxide will already form on the seed layer before plating. This oxide is easily removed, and the underlying copper can chemically attack the wafer when it comes into contact with the acidic plating solution. This leads to exposure of the barrier layer to the solution and results in the formation of bottom or sidewall voids. There are ways to eliminate these voids by having a thick layer in the feature or by using a less aggressive plating solution for copper plating. By optimizing the seed layer, void-free gap filling was achieved as in FIG. 10 (c).

Many changes can be made to the above steps without departing from the basic teachings. Although the present invention has been described in terms of one or more specific process embodiments, those skilled in the art will recognize that changes may be made without departing from the scope and spirit of the invention.

[Brief description of the drawings]

FIG. 1 is a scanning electron microscope (SEM) showing a cross section of a metal coating layer plated on the outside of a semiconductor substrate.
(SEM) photograph, in which the metallization layer was deposited using a plating solution without organic additives and using a low current plating waveform.

FIG. 2 is an SEM photograph showing a cross section of a metal coating layer plated on the outside of a semiconductor substrate;
In this, the metallization layer was deposited using a plating solution without organic additives and using a high current plating waveform.

FIGS. 3 (a)-(d) are SEM photographs showing cross sections of metallization layers plated outside the semiconductor substrate, respectively, wherein the metallization layers have different current densities and thicknesses. Deposited using increased deposition.

FIG. 4 is a SEM photograph showing a cross section of a metal coating layer plated on the outside of a semiconductor substrate;
In this, the metallization layer was deposited using a pulsed reverse waveform.

FIG. 5 is an SEM photograph showing a cross section of a metal coating layer plated on the outside of a semiconductor substrate;
In this, the metallization layer was deposited using a two-step waveform consisting of an initial waveform having a low current density followed by a further waveform having a high current density.

FIG. 6 is an SEM photograph showing a cross section of a metal coating layer plated on the outside of a semiconductor substrate;
In this, the metallization layer was deposited using the two-step corrugations used to plate the metallization layer of FIG. However, the plating solution has a high copper concentration.

7 and 8 are SEM photographs showing a cross section of a metallization layer plated on the outside of a semiconductor substrate, respectively, in which the metallization layer uses a one-step waveform in a plating solution having an organic additive. Deposited.

FIG. 9 is an SEM photograph showing a cross section of a metal coating layer plated on the outside of a semiconductor substrate;
In this, the metallization layer was deposited using the one-step corrugation used in the metallization process of FIGS. However, the concentration of copper in the plating solution has been reduced.

10 (a) to 10 (c) are FIB photographs showing cross sections of a metal coating layer plated on the outside of a semiconductor substrate, wherein the metal coating layer is formed by plating a plating solution having an organic additive. Using plating, the photographs also show the effect of seed layer quality in the plating process.

[Procedure amendment]

[Submission date] May 24, 2001 (2001.5.24)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

2. A method for depositing metal in a micro-recess structure on a surface of a microelectronic circuit workpiece, the method comprising: contacting a surface of the microelectronic circuit workpiece with an electroplating solution in an electroplating container. An electroplating container having a cathode formed by the surface of the microelectronic circuit workpiece and an anode disposed in electrical contact with the electroplating solution, and having a first current density for a first predetermined time; Depositing an initial thin film of metal in the micro-recess structure using at least a first electroplating waveform having a second electroplating waveform having a second current density for a second predetermined time; And at least substantially completing the filling of the micro-recess structure, wherein the second current density of the second electroplating waveform is higher than the first current density of the first electroplating waveform.

3. A method for depositing a metal layer on a surface of a semiconductor wafer, comprising:
The anode and wafer are immersed in an electrolyte containing metal ions, and an anode and a wafer are used to electrolytically deposit an initial metal thin film on the wafer surface.
Electrolyte so as to produce a current of a first nominal current density for a first predetermined time with the electrolyte.
After the first scheduled time to apply a negative bias to the wafer with respect to the wafer and deposit additional metal on the initial metal film.
Increasing the flow to a second nominal current density substantially greater than the first nominal current density
A method that includes steps.

4. The electroplating solution according to claim 1, wherein the electroplating solution is substantially free of organic additives and has a metal to be electroplated at a first predetermined concentration, the concentration being within a plating bath containing organic additives.
4. A method as claimed in claim 1 , 2 or 3 which is higher than a second predetermined concentration suitable for use .

5. A method as claimed in claim 1 , wherein the metal to be plated comprises copper.

6. The method of claim 1 , 2 or 3 , wherein the ratio between the first current density and the second current density is about 1:10.

7. A method as claimed in claim 1 , 2 or 3 wherein the ratio between the first current density and the second current density is about 1: 8.

8. The method according to claim 1, wherein the first scheduled time is on the order of 30 seconds.
Way done.

9. electroplating solution were claimed in claim 4, including the concentration of metal of between about 15 g / L and 36 g / L method.

10. The method according to claim 1, wherein the first electroplating waveform is a pulse waveform.
The method charged to.

11. The method of claim 1 or 2 microrecesses structure has a width of submicron
the method of.

12. The method of claim 1, wherein the micro-recess structure has a width of about 0.5 microns.
Is a process of 2.

13. microrecesses structure aspect ratio of 2: claim 1 or with a 1
2 process.

14. An initial thinning of a metal deposited using a first electroplating corrugation.
The film has a first texture, and a second film deposited using a second electroplating corrugation
4. The process according to claim 1, wherein the second metal has a second structure different from the first structure.
Su.

15. Thin Sea microelectronic circuits workpiece prior to deposition of the initial film
Further comprising depositing a seed layer, wherein depositing the initial thin film enhances the thin seed layer.
The process of claim 1, 2, or 3.

16. After processing the micro-recess structure with the second electroplating waveform,
Use a third electroplating waveform containing a reverse current pulse to eliminate overfilling.
4. The method of claim 1, 2, or 3, further comprising treating the small recess structure.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Fulton, Dakkin 59937 White, Montana, USA 1653 F-Fissieu Pioboxes F-term (reference) 4K024 AA09 BA15 BB12 CA02 CA06 CA07 CA16 CB08 4M104 BB04 DD52

Claims (29)

[Claims] 1. A method for depositing metal in a micro-recess structure on a surface of a microelectronic circuit workpiece, the method comprising: bringing a surface of the microelectronic circuit workpiece into contact with an electroplating solution in an electroplating container. An electroplating container having a cathode formed by the surface of the microelectronic circuit workpiece and an anode disposed in electrical contact with the electroplating solution, and having a first current density for a first predetermined time; An initial thin film of metal is deposited in the micro-recess structure using at least the first electroplating waveform having a first current density of the first electroplating waveform wherein the first current density of the metal deposits at the bottom of the micro-recess structure. Assisting strengthening, using a second electroplating waveform having a second current density at least to continue metal deposition initiated at least some time after the first predetermined time; The second current density of the waveform has a minute recess structure Including steps that help to reduce the time required for substantially complete filling of the pulp. 2. The method of claim 1 wherein the electroplating solution is substantially free of organic additives and has a high concentration of the metal to be electroplated. 3. The method as claimed in claim 1, wherein the metal to be plated comprises copper. 4. The method of claim 1, wherein the ratio between the first current density and the second current density is about 1:10. 5. The method of claim 1, wherein the ratio between the first current density and the second current density is about 1: 8. 6. A method for depositing a metal in a micro-recess structure on a surface of a microelectronic circuit workpiece, the method comprising: bringing a surface of the microelectronic circuit workpiece into contact with an electroplating solution in an electroplating container. An electroplating container having a cathode formed by the surface of the microelectronic circuit workpiece and an anode disposed in electrical contact with the electroplating solution, and having a first current density for a first predetermined time; Depositing an initial thin film of metal in the micro-recess structure using at least a first electroplating waveform having a second electroplating waveform having a second current density for a second predetermined time; And at least substantially completing the filling of the micro-recess structure, wherein the second current density of the second electroplating waveform is higher than the first current density of the first electroplating waveform. 7. The method according to claim 6, wherein the electroplating solution has a high concentration of metal ions or compounds of the metal to be deposited in the micro-recess structure. 8. The method of claim 7, wherein the electroplating solution is substantially free of organic additives typically used as levelers or brighteners. 9. The method as claimed in claim 6, wherein the metal to be plated comprises copper. 10. The method according to claim 7, wherein the metal to be plated comprises copper. 11. The method as claimed in claim 8, wherein the metal to be plated comprises copper. 12. The method of claim 7, wherein the electroplating solution comprises a concentration of the metal between about 15 g / L and 36 g / L. 13. The method of claim 9, wherein the electroplating solution comprises a concentration of copper between about 15 g / L and 36 g / L. 14. The method of claim 10, wherein the electroplating solution comprises a concentration of copper between about 15 g / L and 36 g / L. 15. The method of claim 11, wherein the electroplating solution comprises a concentration of copper between about 15 g / L and 36 g / L. 16. The method according to claim 1, wherein a ratio between the first current density and the second current density is about 1:10.
7. The method as claimed in claim 6, wherein 17. The method of claim 6, wherein the ratio between the first current density and the second current density is about 1: 8. 18. The method according to claim 1, wherein a ratio between the first current density and the second current density is about 1:10.
A method as claimed in claim 7, wherein 19. The method according to claim 7, wherein the ratio between the first current density and the second current density is about 1: 8. 20. A ratio between the first current density and the second current density is about 1:10.
9. The method as claimed in claim 8, wherein 21. The method of claim 8, wherein the ratio between the first current density and the second current density is about 1: 8. 22. A ratio between the first current density and the second current density is about 1:10.
10. The method as claimed in claim 9, wherein 23. The method of claim 9, wherein the ratio between the first current density and the second current density is about 1: 8. 24. A ratio between the first current density and the second current density is about 1:10.
11. The method as claimed in claim 10, wherein 25. The method of claim 10, wherein the ratio between the first current density and the second current density is about 1: 8. 26. The method according to claim 26, wherein a ratio between the first current density and the second current density is about 1:10.
12. The method as claimed in claim 11, wherein 27. The method of claim 11, wherein the ratio between the first current density and the second current density is about 1: 8. 28. The method according to claim 6, wherein the first electroplating waveform is a pulse waveform. 29. The method according to claim 7, wherein the first electroplating waveform is a pulse waveform.