JPH03104230A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03104230A JPH03104230A JP1242453A JP24245389A JPH03104230A JP H03104230 A JPH03104230 A JP H03104230A JP 1242453 A JP1242453 A JP 1242453A JP 24245389 A JP24245389 A JP 24245389A JP H03104230 A JPH03104230 A JP H03104230A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- current density
- plated wiring
- resist
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims abstract 15
- 239000011229 interlayer Substances 0.000 claims abstract 2
- 238000007747 plating Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 10
- 239000010931 gold Substances 0.000 abstract description 10
- 229910052737 gold Inorganic materials 0.000 abstract description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 239000010936 titanium Substances 0.000 abstract description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052763 palladium Inorganic materials 0.000 abstract description 2
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 abstract 2
- 229910021529 ammonia Inorganic materials 0.000 abstract 1
- 230000002950 deficient Effects 0.000 abstract 1
- -1 etc. Chemical compound 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- SWXQKHHHCFXQJF-UHFFFAOYSA-N azane;hydrogen peroxide Chemical compound [NH4+].[O-]O SWXQKHHHCFXQJF-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000004347 surface barrier Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、メッキ配ｓｉｔｅの形成方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of forming a plating site.
近年、ＬＳＩ等の半導体装置の動作を高速化する要求が
多く、これに伴なって金属配線層に大電流を流し得る構
造のものが求められている。このため、大電流を流し得
る金属配線層として例えば金（Ａｌｌ ）等のメッキ配
Ｉ１層が提供されているが、良好な膜質で、しかも不良
率の少ない配線層にする必要がある。In recent years, there has been a growing demand for faster operation of semiconductor devices such as LSIs, and this has led to a need for structures that can allow large currents to flow through metal wiring layers. For this reason, a plating I1 layer made of, for example, gold (All) has been provided as a metal wiring layer that can carry a large current, but it is necessary to have a wiring layer with good film quality and a low defect rate.
従来の半導体装置は、第３図（Ａ）に示す如く、半導体
基板１上にアルミニウム配［１２を形成し、ＰＳＧ等の
居間絶縁膜３を形或し、ここに開口部３ａを設ける。次
に、メタル《パリアメタル及び密着性メタル〉４をスバ
ッタで形或し、レジスト５を塗布してパターニングし、
低電流密度で金メッキを行ない、金メッキ配線層６を形
成する。この場合、良好な躾質（低硬度、耐クラツク性
）のメッキ配Ｉｌ層６を得るには、低電流密度でメッｔ
を行なうことが必要である。次に、レジスト５を剥離し
、第３図（Ｂ）に示す如く、メタル４を過酸化水素アン
モニア及び王水でエッチング除去する。In the conventional semiconductor device, as shown in FIG. 3(A), an aluminum wiring board 12 is formed on a semiconductor substrate 1, a living room insulating film 3 such as PSG is formed, and an opening 3a is provided therein. Next, a metal (pariah metal and adhesive metal) 4 is formed by sputtering, a resist 5 is applied and patterned,
Gold plating is performed at a low current density to form a gold-plated wiring layer 6. In this case, in order to obtain a plated Il layer 6 with good texture (low hardness, crack resistance)
It is necessary to do the following. Next, the resist 5 is peeled off, and the metal 4 is etched away using hydrogen peroxide ammonia and aqua regia, as shown in FIG. 3(B).
メッキ配線層６を形成するに際して低電流密度でメッキ
を行なうが、低電流密度によるメッキはメッキレートが
遅く、アタック時間が長くなる。When forming the plating wiring layer 6, plating is performed at a low current density, but plating at a low current density results in a slow plating rate and a long attack time.
一般に、メタル４とレジスト５との界面における密着性
が弱いため、低電流密度でメッキを行なうとアタック時
間が長いので端部Ａからメッキのしみ込みが入り、メッ
キを行ないたくない部分（レジスト５とメタル４との間
）にも余分にメッキが付着してしまい、配線層と配線層
との間でショートを生じる問題点があった。この余分な
メッキはメタル４のエッチングの際にある程度除去でき
るが、あまりエッチングを過度に行なうとメッキ配線１
１１１６の方に悪影響が及ぶのであまりエッチングを過
度に行なえず、余分なメッキが残ってしまう。In general, since the adhesion at the interface between metal 4 and resist 5 is weak, if plating is performed at a low current density, the attack time will be long, and the plating will seep in from the edge A, which is the area where you do not want to plate (resist 5). There was a problem in that excess plating was deposited also between the wiring layer and the metal 4, causing a short circuit between the wiring layer and the wiring layer. This excess plating can be removed to some extent when etching metal 4, but if the etching is done too much, plated wiring 1
Since 1116 is adversely affected, excessive etching cannot be performed and excess plating remains.
一方、高ｔ流密度でメッキを行なうとしみ込みは入らな
いが、メッキ配線層の膜質が恩く《高硬度、耐クラック
性が悪い）、信頼性の高いメッキ配線層が得られない問
題点があった。On the other hand, if plating is performed at a high t current density, there will be no seepage, but the film quality of the plated wiring layer will be poor (high hardness, poor crack resistance), and the problem is that a highly reliable plated wiring layer cannot be obtained. there were.
本発明は、良好な膜質及び不良率の少ないメツキ配線層
を得ることができる半導体装置の製造方法を提供するこ
とを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can obtain a plating wiring layer with good film quality and a low defect rate.
（課題を解決するための手段） 第１図（Ａ）．（８）は本発明の原理説明図を示す。(Means for solving problems) Figure 1 (A). (8) shows a diagram explaining the principle of the present invention.
基板１上に、配線２及び配線２上に開口部１０ａを有す
る層悶絶縁膜１０を形成し、その表面にメタル層１１を
形成し、更にその表面に配線２上に開口部１２ａを有す
るレジスト１２を塗布し、レジスト開口部１２ａにメッ
本配線層１３を形成する半導体装置の製造方法において
、前記従来例の問題点は、レジスト開口部１２ａに、最
初にｇ電流密度でメッキ配線層１３ｔを所定厚さに形或
し、続いてその上に低電流密度でメッ．″Ｆ配線層１３
２を形成する工程を含むことを特徴とする半導体装置の
製造方法によって解決される。A layered insulating film 10 having wiring 2 and an opening 10a above the wiring 2 is formed on the substrate 1, a metal layer 11 is formed on the surface thereof, and a resist having an opening 12a above the wiring 2 is formed on the surface thereof. In the method of manufacturing a semiconductor device in which a plated wiring layer 13 is formed in a resist opening 12a by coating a plating wiring layer 13t on a resist opening 12a, the problem with the conventional method is that a plating wiring layer 13t is first coated on a resist opening 12a at a current density of g. Shaped to a predetermined thickness and subsequently plated at a low current density. "F wiring layer 13
The present invention is solved by a method for manufacturing a semiconductor device characterized by including a step of forming 2.
低電流密度（ ０．５１１八／ ｃｉ ）にてメッ゛１
を行なうと低硬度、耐クラック性のある良好な膜質のメ
ッキ配線層が得られ、一方、高電流密度（６＋ｅＡ／ａ
ｉ）にてメッキを行なうと、メッキレートが速くてアタ
ック時間が短かいので、メタル層１１とレジスト１２と
の界面部分の密着性が弱くてもその端部からメッキがし
み込むことはない。本発明では、最初に高電流密度のメ
ッキで界面端部にメッキ配線層１３１で蓋をし、続いて
低電流密度のメッキでメッキ配線１３２を形成する。こ
のようにすれば、メタル！ｌ１１とレジスト１２との界
而端部からしみ込みがなく、配線層間でショートを生じ
ることはなく、しかも、低硬度、耐クラツク性のある良
好な膜質のメッキ配線層が得られる。Messenger 1 at low current density (0.5118/ci)
By carrying out this process, a plated wiring layer with low hardness and good film quality with crack resistance can be obtained, while a high current density (6+eA/a
When plating is performed in i), the plating rate is fast and the attack time is short, so even if the adhesion at the interface between the metal layer 11 and the resist 12 is weak, the plating will not seep through the edges. In the present invention, the interface end is first covered with a plated wiring layer 131 by plating at a high current density, and then the plated wiring 132 is formed by plating at a low current density. If you do this, it's metal! There is no seepage from the boundary between l11 and resist 12, no short circuit occurs between wiring layers, and a plated wiring layer of good film quality with low hardness and crack resistance can be obtained.
第２図は本発明の一実施例の製造工程図を示す。 FIG. 2 shows a manufacturing process diagram of an embodiment of the present invention.
同図（Ａ＞に示す如く、半導体基板１上にアルミニウム
等の配線２を１．３μ■の厚さに形成し、層間絶縁ＩＪ
１１０としてＰＳＧＩＩｌ１０＋を１．０μ一．窒化１
１１０２を０。３μ−の厚さに形成し、開孔部１０ａを
開口する。表面にメタル層１１としてチタン（Ｔｉ ）
のバリアメタル１１１を５０００＾，パラジウム（Ｐｄ
）の密着性メタル１１２を３０００Ａの厚さに夫々スバ
ッタで形成する。As shown in FIG.
As 110, PSGIIl10+ was added to 1.0 μl. Nitriding 1
1102 is formed to have a thickness of 0.3 .mu.m, and the opening 10a is opened. Titanium (Ti) as metal layer 11 on the surface
Barrier metal 111 of 5000^, palladium (Pd
) are each formed by sputtering to a thickness of 3000A.
次に、レジスト１２を１０Ｉｉｍの厚さに塗布してパタ
ーニングを行ない、金メッキ液を用いてその開口部１２
ａに金メッキ配線層を形或する。この場合、最初に６ｌ
＾／ｄの高電流密度（メッキにおける通常条件は４１八
／ａＩ１程度→で５０００八の厚さに金メッ４：配線層
１３１を形成し、続いて０． ５ｍ＾／ａｉの低電流密
度で５μ一の厚さに金メッキ配線ＩＩ １ ３ ２を形
成する。このとき、最初に高電流密度で金メッキを行な
って金メッキ配線１１３１を形成しており、高電流密度
によるメッキはメッキレートが速くてアタック時間が短
かいので、密着性メタル１１２とレジスト１２との界面
における密着性が弱くても端部Ｂからメッキしみ込むこ
とはなく、いわば端部Ｂに金メッキ配線層１３１で蓋を
した形となる。Next, resist 12 is applied to a thickness of 10Iim and patterned, and the openings 12 are coated with gold plating solution.
A gold-plated wiring layer is formed on a. In this case, first 6l
A gold plated wiring layer 131 is formed to a thickness of 5000 m at a high current density of ＾/d (the usual conditions for plating is about 418/aI1 →), followed by a low current density of 0.5 m＾/ai. Gold-plated wiring II 1 3 2 is formed to a thickness of 5μ.At this time, gold plating is first performed at high current density to form gold-plated wiring 1131, and plating with high current density has a fast plating rate and is easy to attack. Since the time is short, even if the adhesion at the interface between the adhesive metal 112 and the resist 12 is weak, the plating will not seep in from the end B, so that the end B is covered with the gold-plated wiring layer 131, so to speak.
次に、レジスト１２を剥離し、第２図（Ｂ）に示す如く
、密着性メタル１１２及びバリアメタル１１１を過酸化
水素アンモニア及び王水でエッチング除去する。ここで
、高電流密度での金メッキ配線層１３１ （５０００
八の厚さ）及び低電流密度での金メッキ配線ｉ１１１１
３ｚ（５μ１厚さ〉でメッキ配線１ｉ１１３が構或され
、これは低電流密度で形成された金メッキ配線層１３２
が大部分を占めるため、低硬度で耐クラック性のある良
好な膜質の金メッキ配線層とすることができる。しかも
、密着性メタル１１２とレジスト１２との界面における
端部Ｂに高電流密度による金メッキ層１３１で蓋をした
ので低電流密度によるメッキのしみ込みが入ることはな
く、従来例のような配Ｉｌ層間のショートを生じるよう
なことはない。Next, the resist 12 is peeled off, and the adhesive metal 112 and barrier metal 111 are etched away using hydrogen peroxide ammonia and aqua regia, as shown in FIG. 2(B). Here, the gold-plated wiring layer 131 (5000
Gold-plated wiring i1111 with a thickness of 8 mm) and low current density
A plated wiring 1i 113 is constructed with 3z (5μ1 thickness), which is a gold plated wiring layer 132 formed at a low current density.
occupies a large portion of the gold-plated wiring layer, it is possible to obtain a gold-plated wiring layer with low hardness, crack resistance, and good film quality. Moreover, since the end B at the interface between the adhesive metal 112 and the resist 12 is covered with a gold plating layer 131 made of high current density, the plating does not seep in due to low current density, and the arrangement as in the conventional example is prevented. There is no possibility of short circuit between layers.
（発明の効果）
以上説明した如く、本発明によれば、高電流密度でメッ
キを行ない、続いて低電流密度でメッキを行なっている
ので、低硬度で耐クラック性のある良好な躾質のメッキ
配線層を得ることができ、しかも、レジストとメタル層
との界面部分の密着性が弱くてもしみ込みが起らず、配
ｌＩ間ショートのない高信頼性のメッキ配線層を得るこ
とができる。(Effects of the Invention) As explained above, according to the present invention, plating is performed at a high current density and then plating is performed at a low current density. It is possible to obtain a plated wiring layer, and moreover, it is possible to obtain a highly reliable plated wiring layer that does not seep in even if the adhesiveness of the interface between the resist and the metal layer is weak and does not cause short circuits between interconnects. can.
第１図は本発明の原理説明図、
第２図は本発明の一実施例の製造工程図、第３図は従来
の製造工程図である。
１２はレジスト、
１２ａはレジスト開口部、
１３はメッキ配劃１
１３１は高電流密度による金メッキ配線層、１３２は低
電流密度による金メッキ配ｗＡ層を示す。FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a manufacturing process diagram of an embodiment of the present invention, and FIG. 3 is a conventional manufacturing process diagram. 12 is a resist, 12a is a resist opening, 13 is a plating distribution 1, 131 is a gold-plated wiring layer with a high current density, and 132 is a gold-plated wiring layer with a low current density.
Claims (1)
、該配線（２）上に開口部（１０ａ）を有する層間絶縁
膜（１０）を形成する工程と、前記第１の開口部を含む
表面にメタル層（１１）を形成する工程と、更に該メタ
ル層表面に（２）上に該第１の開口部に対応する第２開
口部（１２ａ）を有するレジスト（１２）を塗布する工
程と、該メタル層（１１）を下地電極とするめっきによ
り該レジスト開口部（１２ａ）にメッキ配線層（１３）
を形成する工程とを含む半導体装置の製造方法において
、 上記第２の開口部（１２ａ）に、最初に高電流密度でメ
ッキ配線層（１３＿１）を所定厚さに形成し、続いてそ
の上に低電流密度でメッキ配線層（１３＿２）を形成す
る工程を含むことを特徴とする半導体装置の製造方法。[Claims] A step of selectively forming a wiring (2) on a substrate (1), and a step of forming an interlayer insulating film (10) having an opening (10a) on the wiring (2). forming a metal layer (11) on the surface including the first opening; and further forming a second opening (12a) on the surface of the metal layer (2) corresponding to the first opening. A plated wiring layer (13) is formed in the resist opening (12a) by applying a resist (12) having
In the method for manufacturing a semiconductor device, the plating wiring layer (13_1) is first formed at a predetermined thickness at a high current density in the second opening (12a), and then a plating wiring layer (13_1) is formed on the second opening (12a) to a predetermined thickness. A method for manufacturing a semiconductor device, comprising a step of forming a plated wiring layer (13_2) at a low current density.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1242453A JPH03104230A (en) | 1989-09-19 | 1989-09-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1242453A JPH03104230A (en) | 1989-09-19 | 1989-09-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104230A true JPH03104230A (en) | 1991-05-01 |
Family
ID=17089327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1242453A Pending JPH03104230A (en) | 1989-09-19 | 1989-09-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104230A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08255911A (en) * | 1994-12-30 | 1996-10-01 | Siliconix Inc | Longitudinal power mosfet with thick metallic layer for reducing distributed resistance, and its manufacture |
| JPH08264785A (en) * | 1994-12-30 | 1996-10-11 | Siliconix Inc | Integrated circuit die and its manufacture |
| JP2002526663A (en) * | 1998-10-05 | 2002-08-20 | セミトウール・インコーポレーテツド | Submicron metallization using electrochemical deposition |
| JP2013243387A (en) * | 2011-04-25 | 2013-12-05 | Samsung Electro-Mechanics Co Ltd | Package substrate and fabricating method thereof |
-
1989
- 1989-09-19 JP JP1242453A patent/JPH03104230A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08255911A (en) * | 1994-12-30 | 1996-10-01 | Siliconix Inc | Longitudinal power mosfet with thick metallic layer for reducing distributed resistance, and its manufacture |
| JPH08264785A (en) * | 1994-12-30 | 1996-10-11 | Siliconix Inc | Integrated circuit die and its manufacture |
| JP2008124516A (en) * | 1994-12-30 | 2008-05-29 | Siliconix Inc | Integrated circuit die and manufacturing method therefor |
| JP2002526663A (en) * | 1998-10-05 | 2002-08-20 | セミトウール・インコーポレーテツド | Submicron metallization using electrochemical deposition |
| JP2013243387A (en) * | 2011-04-25 | 2013-12-05 | Samsung Electro-Mechanics Co Ltd | Package substrate and fabricating method thereof |
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