JP2004103784A - Plating method for semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a depositing method which makes difference in the thickness of wiring within a chip or between chips in the same semiconductor wafer. <P>SOLUTION: This plating method for the semiconductor wafer forms a dummy pattern which is not related with electrical connection which has to be formed in a semiconductor chip within a wafer or within a chip in addition to a wiring pattern related with electrical connection, and simultaneously performs electroplating to the wiring pattern and the dummy pattern so as to make a difference in the thickness of plating layers to be formed on the wiring pattern within the chip or between the chips by using the difference of current density. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for plating a semiconductor wafer, and more specifically, to provide a plating method by providing a dummy pattern not related to electrical connection separately from a wiring pattern related to electrical connection in the same wafer to perform plating. The present invention relates to a method for plating a semiconductor wafer, which makes it possible to provide a difference.
[0002]
[Prior art]
In the same chip, for example, when it is desired to form wiring layers for different wiring capacities, such as a wiring requiring a large current and a wiring used as a signal, a large current can be applied without increasing the wiring width if the wiring can be made thicker. Therefore, an increase in chip area can be prevented.
[0003]
However, conventionally, when forming a wiring on a semiconductor wafer, even if a film is formed by a sputtering method or a vapor deposition method, a metal film is formed on the entire wafer, a resist is formed on the metal film, and patterning is performed. Wiring is formed by etching using a mask. In this case, the thickness of the metal film formed in the wafer is the same over the entire surface of the wafer. Further, the same result is obtained when a film is formed by a sputtering method or a vapor deposition method after a resist is previously patterned, and it is difficult to form wirings having different film thicknesses in a wafer.
[0004]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for forming a wiring layer on a semiconductor wafer, which makes it possible to provide a difference in wiring layer thickness within the same chip.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a dummy pattern that is not related to electrical connection in a wafer or a chip in a same wafer, separately from a wiring pattern related to electrical connection to be formed on a semiconductor chip. By simultaneously performing electrolytic plating on the wiring pattern and the dummy pattern, utilizing the difference in current density, making a difference in the thickness of the plating layer formed in the wiring pattern in the chip or between the chips. A method of plating a semiconductor wafer to be formed.
[0006]
The present inventor has paid attention to the formation of wiring on a wafer by electrolytic plating. That is, in the electroplating, a property that a difference in electric field concentration occurs depending on an area to be plated is used, and a dummy portion is formed on a portion of a wafer where a target wiring pattern is not formed or a portion that does not require functional wiring. By forming a pattern (plating resist opening), the area to be plated is intentionally changed, and the plating layer can be formed with a difference in the wiring thickness depending on the presence or absence of the dummy pattern. In addition, since the electric field concentration is controlled by the area (width and length) of the dummy pattern, the wiring can be changed to an arbitrary thickness. In this way, by providing a difference in the wiring thickness according to the current capacity flowing through the wiring, for example, even between a wiring requiring a large current and a wiring used as a signal, a signal system is collectively formed and a dummy pattern is formed therearound, By making a difference in electric field concentration, it is possible to reduce the thickness of the signal wiring layer and secure the thickness of the large current wiring.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
First, a conventional method for forming a wiring layer will be described with reference to FIG. The upper diagram (A) of FIG. 1 is a diagram of the semiconductor wafer 1 as viewed from above. The lower figure is a schematic cross-sectional view in the order of the wiring formation process of the semiconductor wafer. A metal layer 2 is formed on the entire surface of the wafer 1 by a sputtering method, a vapor deposition method or the like (FIG. 1 (A)), and then a resist film 3 is formed and patterned (FIG. 1 (U)). The metal layer 2 is patterned by etching the layer 2 (FIG. 1 (e)), and then the metal layer pattern 2 is obtained by removing the resist 3. In this method, the metal layer 2 having the same thickness is formed on the entire surface of the wafer (the entire surface of the chip) regardless of the wiring pattern (FIG. 1 (i)).
[0008]
On the other hand, an embodiment of the present invention will be described with reference to FIGS. Since electroplating is performed in the present invention, referring to FIG. 2, a plating pattern is formed by forming a plating base layer (for example, Cu / Cr or Cu / Ti) 12 on the entire surface of a wafer 11 and then forming a resist film 13 thereon. By forming an opening 14 in the resist film 13, a wiring pattern and a dummy pattern are formed by utilizing the property that the opening 14 becomes a region selectively plated with, for example, Cu, Ni, or Au. After selective plating is performed on the opening 14, the resist film 13 is removed to obtain a plating pattern 15. The wiring pattern and the dummy pattern in FIGS. 3 to 6 are openings of such a resist film or metal plating layers formed using the openings.
[0009]
Referring to FIG. 3, a large number of chips 21 and scribe lines 22 for dividing the chips are present in the semiconductor wafer, a wiring pattern 23 is formed in the chips 21, and a dummy pattern 24 is formed in the scribe lines 22. Is formed. Since the dummy pattern 24 is formed in the scribe line 22 as compared with the case where only the wiring pattern 23 in the normal chip 21 is used, the plating area and the density near the wiring pattern 23 increase, and the plating electric field concentration occurs. There to alleviate (or decreased), the thickness T ₁ of the plated layer formed on the wiring pattern 23 is thinner as compared with the case where the dummy patterns 24 are not formed T _{2 (FIG.} 4).
[0010]
In FIG. 3, the dummy pattern is formed on the scribe line. However, as shown in FIG. 5, the dummy pattern 26 may be formed in the chip or in a region which does not affect the wiring pattern 23. As a result, the plating electric field concentration on the wiring pattern 23 is relaxed (or decreased), the thickness T ₃ of the plating layer becomes thinner. Since the metal pattern layer 26 of the dummy pattern formed in this chip does not affect the wiring pattern 23, the chip (LSI) may be formed as it is, and if necessary, only the metal pattern layer 26 of the dummy pattern may be formed. May be selectively removed later.
[0011]
Further, referring to FIG. 6, when a wiring pattern 32 through which a large current is to flow and a signal wiring pattern 33 are present in one chip 31 of the semiconductor wafer, the large current wiring 32 is generally wide. In contrast to the pattern, the signal wiring pattern is a thin line pattern, so that the current capacity is different. Further, in the present invention, a dummy pattern 34 is formed near the signal-system wiring 33 to make the signal-system wiring region a dense pattern, and the large-current-system wiring 32 is separated from the signal-system wiring by a distance L, if necessary. Form as a pattern and perform electroplating. In this case, a difference occurs in the electric field concentration, and the current density increases in the coarse pattern region and the current density decreases in the dense pattern region. The layer can be formed thin. By forming the plating layer of the high-current wiring 32 thick, the thickness of the high-current wiring can be easily secured, so that the wiring density can be increased.
[0012]
The electroplating method itself may be a known method, and can be applied to any of copper plating, nickel plating, gold plating, and the like.
[0013]
【The invention's effect】
According to the present invention, the present inventor forms the wiring on the wafer by electrolytic plating, and a dummy is formed on a portion of the wafer where a desired wiring pattern is not formed or a portion that does not require functional wiring. By forming a pattern, intentionally changing the area to be plated, and forming a plating layer with a difference in wiring thickness depending on the presence or absence of the dummy pattern, wiring within a chip or between chips within the same wafer And a method for forming a wiring that makes the thickness of the wiring different. For example, even between a wiring requiring a large current and a wiring used as a signal, a signal system is collectively formed, a dummy pattern is formed therearound, and the thickness of the signal system wiring layer is reduced by making a difference in electric field concentration. Thus, the thickness of the large current wiring can be secured.
[Brief description of the drawings]
FIG. 1 shows a conventional wiring forming method.
FIG. 2 shows a wiring forming method by plating.
FIG. 3 is a diagram illustrating a plating method for providing a difference in plating thickness using a dummy pattern according to the present invention.
FIG. 4 is a view illustrating a plating method for providing a difference in plating thickness using a dummy pattern according to the present invention, in contrast to FIG. 3;
FIG. 5 is a diagram illustrating another plating method for providing a difference in plating thickness using a dummy pattern according to the present invention.
FIG. 6 is a view illustrating a plating method for providing a difference in plating thickness between a large current wiring and a signal wiring using a dummy pattern according to the present invention.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor wafer 2 metal layer 3 resist layer 11 semiconductor wafer 12 underlayer 13 resist layer 15 plating layer 21 semiconductor chip 22 scribe line 23 wiring pattern 24 dummy pattern 31 semiconductor chip 32 Large current system wiring 33 ... Signal system wiring 34 ... Dummy pattern

Claims (1)

In the same wafer, a dummy pattern not related to the electrical connection is provided in the wafer or chip separately from the wiring pattern related to the electrical connection to be formed on the semiconductor chip, and the wiring pattern and the dummy pattern are simultaneously electroplated. A method of making a difference in the thickness of a plating layer formed in a wiring pattern in a chip or between chips by utilizing a difference in current density.

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