JPH08125332A - Manufacture of multilayer circuit board - Google Patents

Abstract

PURPOSE: To prevent the residue of a photoresist in a viahole and to improve the yield of an interlayer connection by increasing the exposure diameter of the viahole larger than the design diameter of the viahole. CONSTITUTION: After a first layer wiring is obtained, a negative type inter layer insulating film 7 is formed. After the pattern of a viahole is exposed, it is developed to form viaholes 8a-8d. Thereafter, a second layer base conductor film 3b is formed, a positive type photoresist layer is formed thereon, a viahole having a design diameter X and a second layer wiring pattern are exposed, the viaholes 8a-8d are further exposed by using a positive type photomask 5d having larger exposure diameter Z than the diameter X, and developed to obtain a second layer wiring pattern. Then, after a second layer conductor 6b is formed, the part not formed with the conductor 6b of the photoresist 4 and the base conductor film 3b is removed to obtain a two-layer circuit board.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board used as a mounting board for electronic parts such as LSI.

[0002]

2. Description of the Related Art Recently, there is an increasing demand for higher density and higher speed in a circuit board on which electronic components such as LSI are mounted. In order to achieve this, a circuit wiring is formed using photolithography technology, a low dielectric constant organic polymer material is used for the interlayer insulating film, and a method of forming a multilayer wiring is used to connect the layers by via holes. Has been done. For forming the via hole, a method of dry and wet etching the interlayer insulating film, and a method of exposing and developing the photosensitive interlayer insulating film are adopted. Of these, a positive photoresist is often used for wiring formation, particularly when fine wiring is to be formed.

A method of manufacturing a multilayer wiring board in which a photosensitive organic polymer material is used as an interlayer insulating film and wiring is formed by a semi-additive method using a positive photoresist will be described below with reference to the drawings. FIG. 2 is a cross-sectional view showing the manufacturing process of the multilayer wiring board.

First, as shown in FIG. 2A, a first-layer underlying conductor film 3a is formed on an insulating film 2 made of an organic polymer material on a substrate 1, and a positive photoresist is formed thereon. After forming the layer 4, a positive type photomask 5 for the first layer
The wiring pattern of the first layer is exposed using a. Next, this is developed to obtain a first-layer wiring pattern, and then an electrolytic plating film is deposited on the exposed underlying conductor film 3a to form a first-layer conductor 6a (semi-additive method). After that, the photoresist layer 4 and the portion of the underlying conductor film 3a where the conductor 6a is not formed are removed, and
The wiring of the first layer shown in (b) is obtained.

Next, as shown in FIG. 2C, after forming an interlayer insulating film 7 made of a negative photosensitive organic polymer material, a via hole pattern is formed using a negative photomask 5b. To expose. After that, this is developed, and FIG.
The via hole 8 shown in (d) is formed.

Thereafter, similarly, as shown in FIG. 2 (e), a second-layer base conductor film 3b is formed, a positive photoresist layer 4 is formed thereon, and then the second-layer base conductor film 3b is formed. The wiring pattern of the second layer is exposed using the positive type photomask 5c. Next, as shown in FIG. 2F, the via hole portion is further exposed using a positive-type photomask 5d for multiple exposure, and the photoresist in the via hole is irradiated with light. Then, this is developed to obtain a second layer wiring pattern as shown in FIG.

Next, an electrolytic plating film is deposited on the exposed second underlying conductor film to form a second conductor 6b.
After that, the photoresist 4 and the portion of the underlying conductor film 3b where the conductor 6b is not formed are removed, and
The two-layer wiring board shown in (h) is obtained. When the number of layers is further increased, the same operation is repeated thereafter.

[0008]

The problems of the conventional method for manufacturing a multilayer wiring board will be described with reference to the drawings. FIG.
2 (a), 2 (b), 2 (c), and 2 (d) are cross-sectional views showing the manufacturing process of the multilayer wiring board, respectively.
It is a detailed sectional view corresponding to (f), (g), and (h).
In FIG. 3, 8a, 8b, 8c, and 8d are via holes having different cross-sectional shapes, X is a design diameter of the via hole, Y is irradiation light, Z is exposure diameter, and 4a is light of a positive photoresist layer. The portion 4b which is not exposed is a positive type photoresist layer which remains in the via hole after development. Since the other parts are the same as those in FIG.
Description is omitted.

In the conventional method for manufacturing a multilayer wiring board, the photoresist 4 is used in forming the wirings for the second and subsequent layers.
When forming a wiring pattern by using a via hole 8a formed in the interlayer insulating film 7 made of a photosensitive organic polymer material,
Since 8b, 8c, and 8d are one step deeper than the surface portion of the interlayer insulating film 7, it is difficult for light to reach the deepest portion. Therefore, a measure is taken to prevent the photoresist 4 from remaining in the via holes 8a, 8b, 8c, 8d by exposing the via holes 8a, 8b, 8c, 8d separately for a long time (multiple exposure).

However, as the interlayer insulating film 7 made of a photosensitive organic polymer material becomes thicker, the via hole formed becomes a vertical hole with respect to the design diameter X of the via hole, as shown in FIG. 3 (a). The taper type via hole 8b in which the upper part of the vertical hole becomes large, the reverse taper type via hole 8c in which the lower part of the vertical hole becomes large, the spindle type via hole 8d in which the central part of the hole expands, and the vertical type via hole 8a becomes It becomes difficult to be formed. This is considered to be because as the thickness of the interlayer insulating film becomes thicker, the scattering of irradiation light in the interlayer insulating film cannot be ignored, and the actual exposure range fluctuates particularly in the thickness direction of the interlayer insulating film. To be

Further, even when the via hole is formed in the interlayer insulating film made of an organic polymer material by a dry or wet etching method, as the thickness of the interlayer insulating film becomes thicker, the substantial etching range becomes the interlayer insulating film. Since it fluctuates in the thickness direction of the film, it becomes difficult to form a vertical type via hole.

Therefore, when the multiple exposure is carried out subsequently to the exposure of the wiring pattern as in the conventional case, the exposure diameter Z of the multiple exposure is changed to the design diameter X of the via hole as shown in 3 (b).
In the case of the same size as above, the positive type photoresist layer 4 has a portion 4a which is not irradiated with light, and as shown in FIG. 3C, the photoresist layer 4b remains in that portion after development. Therefore, there is a problem in that electrolytic plating does not deposit on that portion, and as shown in FIG. 3D, the conductor 6b of the second layer is not connected to the conductor 6a of the first layer. .

Therefore, an object of the present invention is to prevent the photoresist from remaining inside the via hole and improve the yield of interlayer connection in the production of a multilayer wiring substrate using an organic polymer material as an interlayer insulating film. It is to provide a manufacturing method.

[0014]

In order to achieve the above object, the method for manufacturing a multilayer wiring board of the present invention comprises the following steps. (A) A step of forming an insulating film made of an organic polymer material on the substrate and then forming a first-layer wiring on the insulating film. (B) An organic film is formed on the substrate on which the first-layer wiring is formed. Step of forming an interlayer insulating film made of a molecular material (c) Step of forming a via hole in the interlayer insulating film (d) After forming a base conductor film in the interlayer insulating film and the via hole portion, a positive photoresist layer is formed. Step of forming (e) Step of exposing wiring pattern to positive type photoresist layer using photomask (f) Further exposure of via hole portion using photomask having exposure diameter larger than via hole design diameter Step (g) The positive photoresist layer is developed to form a wiring pattern, and a conductor is formed on the exposed underlying conductor film.
Step of forming the wiring of the layer (h) Step of removing the photoresist and the underlying conductor film on which the conductor is not formed.

The via hole is formed by exposing and developing an interlayer insulating film made of a photosensitive organic polymer material, or by dry or wet etching the interlayer insulating film made of an organic polymer material. It is characterized by being formed.

The wiring is characterized by being formed by a semi-additive method or a full-additive method.

Further, the exposure diameter when the positive photoresist of the via hole portion is exposed is characterized by being 1% to 50% larger than the design diameter of the via hole.

Further, the interlayer insulating film has a film thickness of 5 μm to 10 μm.
It is characterized by being a photosensitive polyimide of 0 μm.

[0019]

According to the method of manufacturing a multilayer substrate of the present invention, the exposure diameter when the photoresist in the via hole portion is subjected to multiple exposure is made larger than the design diameter of the via hole, so that the conventional exposure cannot be performed. Taper type,
It is also possible to expose the portion of the photoresist in the via hole of the inverse taper type or the spindle type. Therefore, the photoresist in the via hole can be almost completely removed by the development.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a multilayer wiring board according to the present invention will be described below with reference to the drawings. 1 (a), (b),
FIGS. 2D, 2F, 2G, and 2H are cross-sectional views showing the manufacturing process of the multilayer wiring board, respectively.
It is a detailed sectional view corresponding to. In the figure, since each part is the same as that in FIG. 3, the same reference numerals are given and description thereof is omitted.

First, the first layer wiring was formed by the same method as the conventional method. That is, on the substrate 1 made of alumina having a purity of 99.5%, the insulating film 2 made of polyimide (for example, Photo Nice manufactured by Toray Industries, Inc .: trade name) and having a film thickness after curing of 20 μm was formed. Then, on the surface of the insulating film 2 surface-treated with hydrazine and catalytically activated with palladium,
An electroless Cu plating film having a film thickness of 500 angstrom was formed as the underlying conductor film 3a using a copper sulfate plating solution.

Next, a positive photoresist layer (for example, AZ4620 manufactured by Hoechst Co .:
After forming the product name), the first layer wiring pattern was exposed using a positive type photomask for the first layer. Next, this is developed to obtain a first-layer wiring pattern, and then electrolytic Cu plating using a Cu sulfate plating solution is used to form an electrolytic plating film having a thickness of about 5 μm on the exposed underlying conductor film 3a. The conductor 6a was formed by precipitation. Then, the photoresist layer 4,
Then, a portion of the underlying conductor film 3a where the conductor 6a was not formed was removed to obtain a first layer wiring.

Next, after forming an interlayer insulating film 7 made of polyimide, which is a negative photosensitive organic polymer material, with a film thickness of 20 μm, the via hole pattern was exposed using a negative photomask. After that, this is developed and shown in FIG.
The via holes 8a, 8b, 8c and 8d shown in (a) were formed. The shape of the obtained via hole is the taper type via hole 8b in which the upper part of the vertical hole is larger than the design diameter X of the via hole, conversely the reverse taper type via hole 8c in which the lower part of the vertical hole is large, Most of the spindle-shaped via holes 8d having a swelled central portion were considered to be affected by the scattering of irradiation light in the interlayer insulating film, and the vertical-type via holes 8a were few.

Thereafter, in the same manner, a second-layer base conductor film 3b is formed, a positive photoresist layer 4 is formed thereon, and then a second-type positive photomask (not shown). Was used to expose a via hole having a design diameter of X and a second layer wiring pattern. Subsequently, as shown in FIG. 1 (b), 12.5 to 50 is larger than the design diameter X of the via hole.
%, The via holes 8a, 8b, 8c and 8d were further exposed (multiple exposure) using a positive type photomask 5d having a large exposure diameter Z. That is, conventionally, the taper type via hole 8b and the reverse taper type via hole 8 are used.
The portion of the spindle c or the spindle-shaped via hole 8d that could not be exposed was also irradiated with light. Then, this was developed to obtain a second-layer wiring pattern as shown in FIG. 1 (c). Next, an electrolytic plating film was deposited on the exposed second-layer underlying conductor film to form a second-layer conductor 6b. Then, the photoresist 4 and the portion of the underlying conductor film 3b where the conductor 6b was not formed were removed to obtain a two-layer wiring board shown in FIG. 1 (d).

By the above method, a two-layer wiring board having six via holes in series for one wiring was manufactured. Table 1 shows the relationship between the multiple exposure diameter and the wiring yield (the number of non-defective wirings / the number of wirings) with respect to the design diameter of the via hole. The quality of the wiring yield was determined by whether or not the wiring was conductive.

[0026]

[Table 1]

As shown in Table 1, by making the multiple exposure diameter larger than the design diameter of the via hole, the number of non-defective wirings increased rapidly and the wiring yield was significantly improved.

Although an alumina substrate having a purity of 99.5% is used as the substrate in the above embodiment, the substrate is not limited to this and various materials can be used as long as smoothness can be obtained. Can be used.

Although an electroless Cu plating film is used as the underlying conductor film formed on the organic polymer layer, the present invention is not limited to this, and a metal thin film or the like formed by sputtering or vapor deposition can be selected. Various materials that can be peeled off can be used.

As the interlayer insulating film, polyimide, which is a photosensitive organic polymer material, is used and exposed and developed to form a via hole, but an organic polymer material having no photosensitivity is used. Alternatively, the via hole can be formed by forming a via hole pattern with a photoresist and dry or wet etching.

Further, in the above embodiment, the range of increasing the multiple exposure diameter is 1 with respect to the design diameter of the via hole.
Although it is set to 2.5 to 50%, it can be narrowed when the variation in via hole diameter is small. In general, the larger the design diameter of the via hole, the closer the via hole is to a vertical shape. Further, the thinner the thickness of the organic polymer layer as the interlayer insulating film, the more nearly vertical via holes can be obtained.

In the above examples, the film thickness of the organic polymer layer was set to 20 μm, but the effect of this manufacturing method can be expected within the range of 5 to 100 μm. Therefore, the lower limit of the range in which the multiple exposure diameter is made larger than the design diameter of the via hole is 1% or more, and the upper limit is not limited as long as it does not affect the densification of the wiring circuit. For example, when the line width / space width = 1: 1 and the multiple exposure diameter is made twice the design diameter of the via hole, some portions will short-circuit with the adjacent wiring. Therefore, depending on the size of the via hole, the wiring circuit can be made higher in density by decreasing the upper limit value.

Further, in the above embodiment, electrolytic Cu plating is used as the electrolytic plating, but the present invention is not limited to this, and a known conductor such as Ni or Au can be appropriately used.

Although the semi-additive method of forming electroplated wiring on electroless plating is used as the method of forming the wiring of the first layer, it is also possible to use the additive method of wiring by electroless plating. That is, after conducting a catalyst activation treatment on the surface of the organic polymer layer, the electroless plated film may be grown to a desired film thickness to form a conductor.

Furthermore, the method for manufacturing a multilayer wiring board of the present invention is also effective for removing the photoresist inside the vertical type via hole formed larger than the designed diameter.

[0036]

As is apparent from the above description, according to the method for manufacturing a multilayer wiring board of the present invention, the multiple exposure diameter when exposing the photoresist in the via hole portion is larger than the design diameter of the via hole. By doing so, even when the shape of the via hole is not formed vertically such as a taper type, an inverse taper type, and a spindle type, the entire photoresist in the via hole can be exposed. Therefore, the photoresist in the via hole can be almost completely removed by the development, continuous plating wiring can be formed in the upper and lower conductor layers in the via hole, and the yield of the connection between the layers of the multilayer wiring board can be improved. Can be improved.

[Brief description of drawings]

FIG. 1 is a detailed cross-sectional view showing a manufacturing process of a multilayer wiring board according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a multilayer wiring board.

FIG. 3 is a detailed cross-sectional view showing a manufacturing process of a conventional multilayer wiring board.

[Explanation of symbols]

 1 Substrate 2 Insulating Film 3a, 3b Base Conductor Film 4, 4a, 4b Positive Photoresist Layer 5a, 5b, 5c, 5d Photomask 6a, 6b Conductor 7 Interlayer Insulating Film 8, 8a, 8b, 8c, 8d Via Hole X Designed diameter of via hole Y Irradiation light Z Exposure diameter

Claims (8)

[Claims] 1. A method for manufacturing a multilayer wiring board, which comprises the following steps. (A) A step of forming an insulating film made of an organic polymer material on the substrate and then forming a first-layer wiring on the insulating film. (B) An organic film is formed on the substrate on which the first-layer wiring is formed. Step of forming an interlayer insulating film made of a molecular material (c) Step of forming a via hole in the interlayer insulating film (d) After forming a base conductor film in the interlayer insulating film and the via hole portion, a positive photoresist layer is formed. Step of forming (e) Step of exposing wiring pattern to positive type photoresist layer using photomask (f) Further exposure of via hole portion using photomask having exposure diameter larger than via hole design diameter Step (g) The positive photoresist layer is developed to form a wiring pattern, and a conductor is formed on the exposed underlying conductor film.
Step of forming the wiring of the layer (h) Step of removing the photoresist and the underlying conductor film on which the conductor is not formed 2. The method for producing a multilayer wiring board according to claim 1, wherein an interlayer insulating film made of a photosensitive organic polymer material is exposed and developed to form a via hole. 3. The method of manufacturing a multilayer wiring board according to claim 1, wherein an interlayer insulating film made of an organic polymer material is dry or wet etched to form a via hole. 4. The method for manufacturing a multilayer wiring board according to claim 1, wherein the wiring is formed by a semi-additive method. 5. The method for manufacturing a multilayer wiring board according to claim 1, wherein the wiring is formed by a full additive method. 6. The exposure diameter when exposing the positive photoresist in the via hole portion is 1% to 50% larger than the design diameter of the via hole.
A method for manufacturing the multilayer wiring board described. 7. The film thickness of the interlayer insulating film is 5 μm to 100 μm.
2. The method for manufacturing a multilayer wiring board according to claim 1, wherein 8. The method of manufacturing a multilayer wiring board according to claim 1, wherein the interlayer insulating film is photosensitive polyimide.