JPH08250857A - Manufacture of multilayer interconnection board - Google Patents

Manufacture of multilayer interconnection board

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Publication number
JPH08250857A
JPH08250857A JP4739895A JP4739895A JPH08250857A JP H08250857 A JPH08250857 A JP H08250857A JP 4739895 A JP4739895 A JP 4739895A JP 4739895 A JP4739895 A JP 4739895A JP H08250857 A JPH08250857 A JP H08250857A
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Patent type
Prior art keywords
interconnection
film
formed
layer
board
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
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JP4739895A
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Japanese (ja)
Inventor
Shunjiro Imagawa
Makoto Miyazaki
Kazuhiko Yamano
俊次郎 今川
信 宮崎
和彦 山野
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Murata Mfg Co Ltd
株式会社村田製作所
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Abstract

PURPOSE: To reduce the uneven surface of a multilayer interconnection board by forming an insulating film made of organic polymer material having a thickness substantially equal to that of the interconnection except the interconnection part on the board. CONSTITUTION: An insulating film 2 20μm thick after curing is formed on a board 1; the surface is treated, activated by a catalyst; and an electroless plated copper film is formed on the front surface of the film 2 as a substrate conductor film 3a. Thereafter, a positive photoresist layer is formed on the film 3a, the first layer interconnection pattern is exposed with a photomask, developed to obtain the first layer interconnection pattern, and then a conductor 4a is formed on the exposed substrate film 3a. Thereafter, the part of the film 3a in which the conductor 4a of the photoresist layer is not formed is removed to obtain a first layer interconnection. Then, a flattened insulating film 10a made of an organic polymer material having the thickness substantially equal to that of the interconnection is formed except the interconnection on the board formed with the first layer interconnection.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、LSIなどの電子部品の実装基板として用いられる多層配線基板の製造方法に関する。 The present invention relates to a method for manufacturing a multilayer wiring board is used as a mounting board for electronic components such as LSI.

【0002】 [0002]

【従来の技術】最近、LSIなどの電子部品を実装する回路基板において、高密度化・高速度化の要請が高まっている。 Recently, in a circuit board for mounting electronic parts such as LSI, there is an increasing demand for high density and speeds. これを実現するために、フォトリソグラフィーの技術を用いて回路配線を形成し、層間絶縁膜には低誘電率の有機高分子材料を用い、バイアホールによって層間を接続する多層配線の形成方法が実施されている。 To achieve this, to form a circuit wiring by using a photolithography technique, the interlayer insulating film using an organic polymer material having a low dielectric constant, the method of forming the multi-layer wiring for connecting the interlayer by via holes performed It is. このバイアホールの形成には、層間絶縁膜をドライおよびウエットのエッチングをする方法や、感光性の層間絶縁膜を露光、現像する方法が採用されている。 This formation of the via hole, and a method of dry and wet etching the interlayer insulating film, exposing the photosensitive interlayer insulating film, a method of developing is employed. その中で、 inside that,
特に微細な配線を形成しようとするときには、配線形成にポジ型のフォトレジストを用いる場合が多い。 When attempting to form a particularly fine wiring is often used positive photoresist forming wiring.

【0003】以下、感光性の有機高分子材料を層間絶縁膜に用い、ポジ型のフォトレジストを用いてセミアディティブ法により配線を形成する多層配線基板の製造方法を図面に基づき説明する。 [0003] Hereinafter, a photosensitive organic polymer material in the interlayer insulating film, will be described with reference to the drawings a method for manufacturing a multilayer wiring board forming the wiring by the semi-additive method using a positive photoresist. 図3は多層配線基板の製造工程を示す断面図である。 Figure 3 is a cross-sectional view showing a manufacturing process of the multilayer wiring board.

【0004】まず、図3(a)に示すように、基板上に1層目の配線を形成する。 [0004] First, as shown in FIG. 3 (a), to form a first wiring layer on the substrate. 即ち、基板1上の有機高分子材料からなる絶縁膜2の全面に1層目の下地導体膜3a That is, the first layer of the base conductor film 3a on the entire surface of the insulating film 2 made of an organic polymeric material on the substrate 1
を形成し、その上にポジ型のフォトレジスト層を形成した後、1層目用のポジ型のフォトマスクを用いて1層目の配線パターンを露光する。 Forming a, after forming the on the positive photoresist layer thereon, and exposing the first wiring pattern using a positive photomask for the first layer. その後、これを現像して1 Then, by developing the this one
層目の配線パターンを得た後、露出した下地導体膜3a After obtaining a layer of wiring patterns, the exposed underlying conductive film 3a
の上に電解めっき膜を析出させて1層目の導体4aを形成する(セミアディティブ法)。 Precipitating electrolytic plating film on the forming the first layer conductor 4a are (semi-additive method). その後、フォトレジスト層、および下地導体膜3aのうちで導体4aが形成されていない部分を除去して図3(a)に示す1層目の配線を得る。 Then, to obtain a photoresist layer, and the underlying conductive film 3a by removing the portion which is not the conductor 4a is formed among the first-layer wiring shown in FIG. 3 (a).

【0005】次に、図3(b)に示すように、1層目の配線を形成した基板上に、有機高分子材料からなる層間絶縁膜を形成し、この層間絶縁膜にバイアホールを形成する。 [0005] Next, as shown in FIG. 3 (b), on a substrate to form a wiring of the first layer, an interlayer insulating film comprising an organic polymer material, forming via holes in the interlayer insulating film to. 即ち、1層目の配線を形成した基板上全面にネガ型の感光性の有機高分子材料からなる層間絶縁膜5を形成した後、ネガ型のフォトマスクを用いてバイアホールのパターンを露光する。 That is, after forming an interlayer insulating film 5 made of a negative type photosensitive organic polymer material on the entire surface of the substrate formed with wiring for the first layer, to expose a pattern of via holes using a negative type photomask . その後、これを現像して、図3 Then developed, 3
(b)に示すバイアホール6を形成する。 Forming via holes 6 shown in (b).

【0006】その後、図3(c)に示すように、層間絶縁膜5およびバイアホール6に下地導体膜3bを形成した後、ポジ型のフォトレジスト層7を形成する。 [0006] Thereafter, as shown in FIG. 3 (c), after forming the base conductor layer 3b in the interlayer insulating film 5 and the via holes 6, a photoresist layer 7 positive type.

【0007】次に、図3(d)に示すように、2層目の配線パターンを形成する。 [0007] Next, as shown in FIG. 3 (d), to form a second wiring pattern. 即ち、ポジ型のフォトマスクを用いてポジ型のフォトレジスト層7に2層目の配線パターンを露光する。 That is, to expose the second wiring pattern in the photoresist layer 7 positive type using a positive photomask. さらに、多重露光用のポジ型のフォトマスクを用いてポジ型のフォトレジスト層7のバイアホール6の部分をさらに露光する。 Moreover, further exposing the portion of the via hole 6 of the photoresist layer 7 positive type using a positive photomask for multiple exposure. そして、これを現像して、図3(d)に示す2層目配線パターンを得る。 Then, by developing it, obtain a second layer interconnection pattern shown in Figure 3 (d).

【0008】次に、図3(e)に示すように、露出した2層目の下地導体膜3b上に電解めっき膜を析出させて2層目の導体4bを形成する。 [0008] Next, as shown in FIG. 3 (e), on the underlying conductive film 3b of the second layer exposed to precipitate the electrolytic plated film to form a second layer conductor 4b by. その後、フォトレジスト7、および下地導体膜3bのうちで導体4bが形成されていない部分を除去して、図3(f)に示す2層配線基板を得る。 Thereafter, by removing the portion which is not the conductor 4b is formed within the photoresist 7, and the underlying conductive film 3b, to obtain a two-layer wiring board shown in FIG. 3 (f). さらに多層化する場合は、以降同様の操作を繰り返す。 If an additional multilayer repeats the subsequent same operations.

【0009】 [0009]

【発明が解決しようとする課題】従来の多層配線基板の製造方法においては、2層目以降の配線を形成する際に、1層目配線上の層間絶縁膜が配線の厚さの分だけ盛り上がってしまう。 In THE INVENTION Problems to be Solved by the conventional method of manufacturing a multilayer wiring board, in forming the second layer and subsequent lines, only the interlayer insulating film on the first wiring layer is corresponding to the thickness of the wiring raised and will. 以後、積層を繰り返すと、この起伏の影響が引き継がれて基板表面の平滑性が益々失われてしまう。 Thereafter, repeating the lamination, the smoothness of the substrate surface is taken over the effect of the undulations will be increasingly lost. このため、フォトリソグラフの工程で寸法精度が悪くなるなどの不具合が生じて歩留まりが低下するという問題点を有していた。 Therefore, trouble caused the yield of such dimensional accuracy is deteriorated by the photolithography process has a problem of a decrease.

【0010】また、電子部品を実装した多層配線基板の動作の高速化のためには、多層配線基板の配線の厚さを厚くすることが有効であるが、厚くするにしたがって上述のように基板表面の平滑性が失われて歩留まりが低下するため、厚くするにも限界があった。 Further, in order to speed up the operation of the multi-layer wiring board mounted with electronic components, the substrate, as described above in accordance with it it is effective to increase the thickness of the multilayer wiring board interconnection, thickening since the smoothness of the surface is yield decreases lost, there is a limit in thickness.

【0011】そこで、本発明の目的は、配線基板表面の凹凸を低減させた多層配線基板の製造方法を提供することにある。 [0011] Therefore, an object of the present invention is to provide a method for manufacturing a multilayer wiring board with reduced unevenness of wiring substrate surface.

【0012】 [0012]

【課題を解決するための手段】上記目的を達成するため、本発明の多層配線基板の製造方法は次の工程よりなる。 To achieve the above object, according to an aspect of manufacturing method for a multilayer wiring board of the present invention consists of the following steps. (a)基板上に有機高分子材料からなる絶縁膜を形成した後、該絶縁膜上に1層目の配線を形成する工程、 (A) after forming an insulating film comprising an organic polymer material on a substrate, forming a first wiring layer on the insulating film,
(b)基板上の1層目の配線部分以外に、該配線とほぼ等しい厚さの有機高分子材料からなる平坦化用絶縁膜を形成する工程、(c)1層目の配線および絶縁膜を形成した基板上に、有機高分子材料からなる層間絶縁膜を形成し、該層間絶縁膜にバイアホールを形成する工程、 (B) in addition to the first wiring portion on the substrate, forming a planarizing insulating film made of an organic polymer material substantially equal thickness as the wiring, (c) a first wiring layer and the insulating film process the formed on a substrate, an interlayer insulating film comprising an organic polymer material to form a via hole in the interlayer insulating film,
(d)層間絶縁膜およびバイアホール部分に、下地導体膜を形成した後フォトレジスト層を形成する工程、 (D) in the interlayer insulating film and the via hole portions, forming a photoresist layer after forming the base conductor layer,
(e)フォトマスクを用いてフォトレジスト層を露光、 (E) exposing the photoresist layer using a photo mask,
現像して配線パターンを形成する工程、(f)配線パターンに導体を形成して2層目の配線を形成する工程、 Forming a developing the wiring pattern, forming a wiring in the second layer to form a conductor (f) the wiring pattern,
(g)フォトレジスト、および導体の形成されていない下地導体膜を除去する工程。 (G) photoresist, and removing the underlying conductive film is not formed in the conductor.

【0013】また、バイアホールは、感光性の有機高分子材料からなる層間絶縁膜を露光、現像して形成するか、または、有機高分子材料からなる層間絶縁膜をドライまたはウエットのエッチングをして形成することを特徴とする。 Further, via holes, exposing the interlayer insulating film made of a photosensitive organic polymer material, or is formed by development, or, an interlayer insulating film comprising an organic polymer material to etching of the dry or wet and forming Te.

【0014】また、配線は、セミアディティブ法またはフルアディティブ法で形成することを特徴とする。 Further, the wiring is characterized in that to form a semi-additive method or a full additive method.

【0015】さらに、層間絶縁膜は感光性ポリイミドであることを特徴とする。 Furthermore, an interlayer insulating film is characterized in that it is a photosensitive polyimide.

【0016】 [0016]

【作用】本発明の多層配線基板の製造方法によれば、基板上の配線部分以外に、配線とほぼ等しい厚さの有機高分子材料からなる絶縁膜を形成する。 According to the method for manufacturing a multilayer wiring board of the present invention, in addition to the wiring portion on the substrate, an insulating film made of an organic polymer material substantially equal in thickness to the wiring. したがって、従来のように、配線上の層間絶縁膜が配線の厚さの分だけ盛り上がることがなく、多層配線基板表面の凹凸が低減される。 Therefore, as in the conventional interlayer insulating film on the wiring without rise by the amount of thickness of the wiring, the unevenness of the multilayer wiring board surface is reduced.

【0017】 [0017]

【実施例】 【Example】

(実施例)以下、本発明の多層配線基板の製造方法の実施例を図面に基づいて説明する。 (Example) will be described below with reference to examples of a method for manufacturing a multilayer wiring board of the present invention with reference to the drawings. 図1は、本発明の多層配線基板の製造工程を示す断面図であ。 Figure 1 is a sectional view showing a manufacturing process of the multilayer wiring board of the present invention. 同図において、 In the figure,
10aは基板上の配線部分以外に、配線とほぼ等しい厚さで形成された有機高分子材料からなる平坦化用絶縁膜である。 10a is other than the wiring portion on the substrate, a planarizing insulating film made of an organic polymer material which is formed by the thickness approximately equal to the wiring. その他の部分は図3と同一であるので、同一符号を付して説明は省略する。 Since other portions are the same as FIG. 3, are denoted by the same reference numerals will be omitted.

【0018】まず、図1(a)に示すように、基板上に1層目の配線を形成した。 [0018] First, as shown in FIG. 1 (a), to form a first wiring on the substrate. 即ち、純度99.5%のアルミナ製の基板1の上に、感光性ポリイミド(例えば、東レ社製フォトニース:商品名)からなり硬化後の膜厚が20μmの絶縁膜2を形成した。 That is, on the purity of 99.5% of alumina substrate 1, photosensitive polyimide (e.g., manufactured by Toray Industries, Inc. PHOTONEECE: trade name) film thickness after curing consists was formed an insulating film 2 of 20 [mu] m. その後、ヒドラジンで表面処理しパラジウムで触媒活性化処理を行なった絶縁膜2の全面に、硫酸銅めっき液を用いて膜厚500オングストロームの無電解銅めっき膜を下地導体膜3aとして形成した。 Thereafter, the surface treatment of the insulating film 2 was subjected to catalytic activation treatment with palladium whole surface with hydrazine, an electroless copper plating film having a thickness of 500 Å was formed as the underlying conductor film 3a with a copper sulfate plating solution. その後、下地導体膜3aの上に、ポジ型のフォトレジスト層(例えば、ヘキスト社製AZ462 Then, on the underlying conductive film 3a, positive photoresist layer (e.g., Hoechst AZ462
0:商品名)を形成した後、1層目用のポジ型のフォトマスクを用いて1層目配線パターンを露光した。 0: After forming a trade name), was exposed first-layer wiring pattern using a positive photomask for the first layer. 次に、 next,
これを現像して1層目の配線パターンを得た後、硫酸銅めっき液を用いた電解銅めっきによって、露出した下地導体膜3aの上に膜厚約5μmの電解銅めっき膜を析出させて導体4aを形成した。 After obtaining the first wiring pattern and developed, by electrolytic copper plating using a copper sulfate plating solution, to precipitate an electrolytic copper plated film having a thickness of about 5μm on the exposed underlying conductive film 3a forming a conductor 4a. その後、フォトレジスト層、および下地導体膜3aのうち導体4aが形成されていない部分を除去して図1(a)に示す1層目の配線を得た。 Then, to obtain a photoresist layer, and the conductor 4a of the underlying conductive film 3a is to remove a portion not formed a first wiring shown in FIG. 1 (a).

【0019】次に、図1(b)に示すように、1層目の配線を形成した基板上の配線部分以外に、この配線とほぼ等しい厚さの有機高分子材料からなる平坦化絶縁膜を形成した。 Next, as shown in FIG. 1 (b), other than the wiring portion on the substrate formed with wiring for the first layer, planarizing insulating film made of an organic polymer material substantially equal thickness as the wiring It was formed. 即ち、1層目の配線を形成した基板上全面に膜厚5μmのネガ型の感光性の有機高分子材料であるポリイミドからなる絶縁膜を形成した後、ネガ型のフォトマスクを用いて1層目の配線部分以外を露光した。 That is, after forming an insulating film made on the substrate to form a wiring of the first layer over the entire surface from an organic polymeric material of the negative type photosensitive film thickness 5μm polyimide, one layer by using a negative photomask It was exposed to light other than the eyes of the wiring portion. その後、これを現像して、図1(b)に示す平坦化用絶縁膜10aを形成した。 Then developed, to form a planarization insulating film 10a shown in FIG. 1 (b).

【0020】その後、図1(c)に示すように、1層目の配線および平坦化用絶縁膜を形成した基板上に、有機高分子材料からなる層間絶縁膜を形成し、この層間絶縁膜にバイアホールを形成した。 [0020] Thereafter, as shown in FIG. 1 (c), on a substrate formed with the first wiring and the flattening insulating film, an interlayer insulating film comprising an organic polymer material, the interlayer insulating film the formation of the via holes to. 即ち、1層目の配線および平坦化用絶縁膜10aを形成した基板上全面に膜厚2 That is, the film thickness 2 on the substrate to form the first wiring and the planarizing insulating film 10a over the entire surface
0μmのネガ型の感光性の有機高分子材料であるポリイミドからなる絶縁膜5を形成した後、ネガ型のフォトマスクを用いてバイアホールのパターンを露光した。 After forming the insulating film 5 made of polyimide is an organic polymer material of the negative type photosensitive 0 .mu.m, and exposing a pattern of via holes using a negative photomask. その後、これを現像して、図1(c)に示すバイアホール6 Then developed, via holes 6 shown in FIG. 1 (c)
を形成した。 It was formed.

【0021】その後、図1(d)に示すように、層間絶縁膜5およびバイアホール6に下地導体膜3bを形成した後、その上にポジ型のフォトレジスト層7(例えば、 [0021] Thereafter, as shown in FIG. 1 (d), after forming the base conductor layer 3b in the interlayer insulating film 5 and the via-hole 6, the photoresist layer 7 on the positive thereof (eg,
ヘキスト社製AZ4620:商品名)を形成した。 Hoechst AZ4620: to form a trade name).

【0022】その後、図1(e)に示すように、2層目の配線パターンを形成した。 [0022] Thereafter, as shown in FIG. 1 (e), to form a second wiring pattern. 即ち、ポジ型のフォトマスクを用いてポジ型のフォトレジスト層7に2層目の配線パターンを露光した。 That is, by exposing the second wiring pattern in the photoresist layer 7 positive type using a positive photomask. さらに、多重露光用のポジ型のフォトマスクを用いてポジ型のフォトレジスト層7のバイアホール6の部分を露光した。 Furthermore, the exposed portions of the via hole 6 of the photoresist layer 7 positive type using a positive photomask for multiple exposure. そして、これを現像して、図3(e)に示す2層目配線パターンを得た。 Then, by developing this, obtained was a two-layer wiring pattern shown in FIG. 3 (e).

【0023】次に、図3(f)に示すように、硫酸銅めっき液を用いた電解銅めっきで、露出した2層目の下地導体膜3b上に膜厚約5μmの電解銅めっき膜を析出させて2層目の導体4bを形成した。 Next, as shown in FIG. 3 (f), precipitating an electrolytic copper plated film of the electrolytic copper plating, a film thickness of about 5μm on the underlying conductive film 3b of the second layer which is exposed using a copper sulfate plating solution to form a second layer conductor 4b by. その後、フォトレジスト7、および下地導体膜3bのうちで導体4bが形成されていない部分を除去して、図3(f)に示す2層配線基板を得た。 Thereafter, by removing the portion which is not the conductor 4b is formed within the photoresist 7, and the underlying conductive film 3b, to give a two-layer wiring board shown in FIG. 3 (f).

【0024】さらに、同様の操作を繰り返して3層配線基板を得た。 Furthermore, to obtain a three-layered wiring board by repeating the same operation. 得られた配線基板の断面図を図2に示す。 The cross section of the obtained wiring board shown in FIG.
なお、同図において、4cは3層目の配線、15は2層目と3層目との配線間の層間絶縁膜、10bは2層目の配線とほぼ等しい厚さの有機高分子材料からなる平坦化絶縁膜であり、下地導体膜は省略している。 In the figure, 4c is 3-layer wiring, 15 second and third layers and an interlayer insulating film between wirings, 10b from an organic polymer material substantially equal thickness as the second wiring layer a planarization insulating film made, the underlying conductive film is omitted. その他の部分は、図1と同様であるので、同一の符号を付す。 Other portions are the same as in FIG. 1, the same reference numerals.

【0025】(比較例)比較のため、従来方法によって、実施例と同様の3層配線基板を得た。 [0025] Comparative Example For comparison, by conventional methods, to obtain a 3-layer wiring board similar to the embodiment. 従来の多層配線基板の製造工程を示す断面図の図3に基づいて説明する。 It will be described with reference to Figure 3 a cross-sectional view showing a manufacturing process of a conventional multilayer wiring board.

【0026】即ち、まず、図3(a)に示すように、実施例と同様にして、基板上に1層目の配線を形成した。 [0026] That is, first, as shown in FIG. 3 (a), in the same manner as in Example, to form a first wiring on the substrate.

【0027】次に、図3(b)に示すように、平坦化絶縁膜を形成せずにその他は実施例と同様にして、1層目の配線を形成した基板上に、有機高分子材料からなる層間絶縁膜5を形成し、この層間絶縁膜5にバイアホール6を形成した。 Next, as shown in FIG. 3 (b), the other without forming the planarization insulating film in the same manner as in Example, on a substrate formed with wiring for the first layer, an organic polymer material an interlayer insulating film 5 made of, to form via holes 6 in the interlayer insulating film 5.

【0028】その後、図3(c)に示すように、実施例と同様にして、層間絶縁膜5およびバイアホール6に下地導体膜3bを形成した後、ポジ型のフォトレジスト層7(例えば、ヘキスト社製AZ4620:商品名)を形成した。 [0028] Thereafter, as shown in FIG. 3 (c), in the same manner as in Example, after forming the base conductor layer 3b in the interlayer insulating film 5 and the via-hole 6, positive photoresist layer 7 (e.g., Hoechst AZ4620: to form a trade name).

【0029】その後、図3(d)に示すように、実施例と同様にして、2層目の配線パターンを形成した。 [0029] Thereafter, as shown in FIG. 3 (d), in the same manner as in Example to form a second wiring pattern.

【0030】次に、図3(e)に示すように、実施例と同様にして、露出した2層目の下地導体膜3b上に2層目の導体4bを形成した。 Next, as shown in FIG. 3 (e), in the same manner as in Example to form a second layer conductor 4b on the exposed second layer of the underlying conductive film 3b. その後、フォトレジスト7、 Thereafter, the photoresist 7,
および下地導体膜3bのうちで導体4bが形成されていない部分を除去して、図3(f)に示す2層配線基板を得た。 And the underlying conductive film 3b by removing a portion which is not the conductor 4b is formed among obtain a two-layer wiring board shown in FIG. 3 (f).

【0031】さらに、同様の操作を繰り返して3層配線基板を得た。 Furthermore, to obtain a three-layered wiring board by repeating the same operation. 得られた配線基板の断面図を図4に示す。 The cross section of the obtained wiring board shown in FIG.
なお同図において、4cは3層目の配線、15は2層目と3層目との配線間の層間絶縁膜であり、下地導体膜は省略している。 Note In the figure, 4c is 3-layer wiring, 15 denotes an interlayer insulating film between wirings of the second layer and the third layer, the underlying conductive film is omitted. その他の部分は、図3と同様であるので、同一の符号を付す。 Other portions are the same as in FIG. 3, the same reference numerals.

【0032】以上得られた実施例および従来例の多層配線基板について、その表面の凹凸を表面粗さ計で測定した。 The multilayer wiring board of the above obtained in Examples and Conventional Example were measured unevenness of its surface with a surface roughness meter. その結果、基板表面の最も高い部分と最も低い部分の高低差(r)は、従来例の場合の25μmに対して実施例の場合は20μmを示し、多層配線基板表面の凹凸を低減することができた。 As a result, the height difference between the lowest portion and the highest portion of the substrate surface (r) is the case of Example with respect to 25μm in the case of the conventional example shows a 20 [mu] m, it is possible to reduce the unevenness of the multilayer wiring substrate surface did it.

【0033】なお、上記実施例において、基板として純度99.5%のアルミナ基板を用いているが、これに限定されることはなく、平滑性の得られるものであれば種々の材質のものを用いることができる。 [0033] In the above embodiment uses a purity of 99.5% alumina substrate as the substrate is not limited thereto, any of various materials as long as it is obtained smoothness it can be used.

【0034】また、有機高分子層の上に形成する下地導体膜として、無電解銅めっき膜を用いているが、これに限定されることはなく、スパッタあるいは蒸着によって形成した金属薄膜などの選択的な剥離が可能な種々のものを用いることができる。 Moreover, as an underlying conductive film formed on the organic polymer layer, but using an electroless copper plating film is not limited to this, the selection of a metal thin film formed by sputtering or vapor deposition it can be used specific peeling of the various possible.

【0035】また、層間絶縁膜として、感光性の有機高分子材料であるポリイミドを用いそれを露光、現像してバイアホールを形成しているが、感光性を有しない有機高分子材料を用いて、フォトレジストによるバイアホールパターンの形成とドライまたはウエットのエッチングによってバイアホールを形成することもできる。 Further, as an interlayer insulating film, exposing it with a polyimide which is an organic polymeric material of the light-sensitive, but to form a via hole and developed using an organic polymer material having no photosensitivity , it is also possible to form a via hole by etching forming a dry or wet of the via hole pattern by the photoresist.

【0036】また、配線形成方法として無電解めっきの上に電解めっき配線をするセミアディティブ法を用いているが、無電解めっきで配線するアディティブ法によることも可能である。 Further, although using a semi-additive method using electrolytic plating routed over the electroless plating as a wiring forming method, it is also possible according to the additive method for wiring by electroless plating. 即ち、有機高分子層の表面の触媒活性化処理を行なった後、無電解めっき膜を所望の膜厚まで成長させて導体を形成させればよい。 That is, after performing the catalyst activation treatment of the surface of the organic polymer layer, an electroless plated film it is sufficient to form a conductor is grown to a desired thickness.

【0037】さらに、本実施例では、ポリイミドの膜厚を20μmとしたが、5〜100μmの範囲で本製造方法の効果を期待できる。 Furthermore, in this embodiment, the thickness of the polyimide was 20 [mu] m, it can be expected the effect of the manufacturing method in the range of 5 to 100 [mu] m.

【0038】 [0038]

【発明の効果】以上の説明で明らかなように、本発明の多層配線基板の製造方法によれば、基板上の配線部分以外に、配線とほぼ等しい厚さの有機高分子材料からなる絶縁膜を形成するため、従来のように、配線上の層間絶縁膜が配線の厚さの分だけ盛り上がることがなく、多層配線基板表面の凹凸を低減させることができる。 As is apparent from the foregoing description, according to the method of manufacturing the multilayer wiring board of the present invention, in addition to the wiring portion on the substrate, an insulating film made of an organic polymer material substantially equal in thickness to the wiring to form a, as in the prior art, an amount corresponding rise that no interlayer insulating film thickness of the wiring on the wiring, it is possible to reduce the unevenness of the multilayer wiring substrate surface.

【0039】したがって、多層配線基板の製造において、フォトリソグラフの工程での寸法精度が悪くなるなどの不具合を防止して歩留まりを向上させることができる。 [0039] Thus, it is possible in the production of multi-layer wiring board, to improve the yield and prevent problems such as dimensional accuracy in the photolithography process becomes poor.

【0040】また、従来、歩留まりが低下して困難であった、多層配線基板の配線の厚さを厚くして電子部品を実装したときの動作の高速化を図ることも可能となる。 Further, conventionally, the yield has been difficult to decrease, it is possible to by increasing the thickness of the multilayer wiring board interconnection speeded up operation when an electronic component is mounted.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の多層配線基板の製造工程を示す断面図である。 1 is a cross-sectional view showing a manufacturing process of the multilayer wiring board of the present invention.

【図2】本発明の製造方法により得られた多層配線基板の断面図である。 2 is a cross-sectional view of a multilayer wiring substrate obtained by the production method of the present invention.

【図3】従来の多層配線基板の製造工程を示す断面図である。 3 is a cross-sectional view showing a manufacturing process of a conventional multilayer wiring board.

【図4】従来の製造方法により得られた多層配線基板の断面図である。 4 is a cross-sectional view of a multilayer wiring board obtained by the conventional manufacturing method.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 基板 2 絶縁膜 3a,3b 下地導体膜 4a,4b,4c 導体 5,15 層間絶縁膜 6 バイアホール 7 フォトレジスト層 10a,10b 平坦化絶縁膜 1 substrate 2 insulating film 3a, 3b underlying conductive film 4a, 4b, 4c conductors 5,15 interlayer insulating film 6 via holes 7 photoresist layer 10a, 10b planarization insulating film

Claims (6)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 次の工程よりなる多層配線基板の製造方法。 1. A method for manufacturing a multilayer wiring substrate made of the next step. (a)基板上に有機高分子材料からなる絶縁膜を形成した後、該絶縁膜上に1層目の配線を形成する工程、 (b)基板上の1層目の配線部分以外に、該配線とほぼ等しい厚さの有機高分子材料からなる平坦化用絶縁膜を形成する工程、 (c)1層目の配線および平坦化用絶縁膜を形成した基板上に、有機高分子材料からなる層間絶縁膜を形成し、 After forming an insulating film comprising an organic polymer material on the (a) substrate, forming a first wiring layer on the insulating film, other than (b) the first wiring portion on the substrate, wherein forming a planarizing insulating film made of an organic polymer material substantially equal in thickness to the wiring, on a substrate formed with (c) 1-layer wiring and the planarizing insulating film made of an organic polymer material an interlayer insulating film,
    該層間絶縁膜にバイアホールを形成する工程、 (d)層間絶縁膜およびバイアホール部分に、下地導体膜を形成した後フォトレジスト層を形成する工程、 (e)フォトマスクを用いてフォトレジスト層を露光、 Forming a via hole in the interlayer insulating film, in (d) of the interlayer insulating film and the via hole portions, forming a photoresist layer after forming the base conductor layer, the photoresist layer using (e) the photomask exposure to,
    現像して配線パターンを形成する工程、 (f)配線パターンに導体を形成して2層目の配線を形成する工程、 (g)フォトレジスト、および導体の形成されていない下地導体膜を除去する工程。 Forming a developing the wiring pattern, to remove the (f) step of forming a conductive wiring pattern to form the wiring of the second layer, (g) the photoresist, and the conductive underlying conductive film is not formed process.
  2. 【請求項2】 感光性の有機高分子材料からなる層間絶縁膜を露光、現像してバイアホールを形成することを特徴とする請求項1記載の多層配線基板の製造方法。 Wherein exposing the interlayer insulating film made of a photosensitive organic polymer material, a method for manufacturing a multilayer wiring board according to claim 1, wherein the via holes are formed and developed.
  3. 【請求項3】 有機高分子材料からなる層間絶縁膜をドライまたはウエットのエッチングをしてバイアホールを形成することを特徴とする請求項1記載の多層配線基板の製造方法。 3. A method for manufacturing a multilayer wiring board according to claim 1, wherein the via holes are formed interlayer insulating film by the etching of the dry or wet a made of an organic polymer material.
  4. 【請求項4】 セミアディティブ法により配線を形成することを特徴とする請求項1記載の多層配線基板の製造方法。 4. A method for manufacturing a multilayer wiring board according to claim 1, wherein the forming the wiring by the semi-additive method.
  5. 【請求項5】 フルアディティブ法により配線を形成することを特徴とする請求項1記載の多層配線基板の製造方法。 5. A method for manufacturing a multilayer wiring board according to claim 1, wherein the forming the wiring by full additive method.
  6. 【請求項6】 層間絶縁膜は感光性ポリイミドであることを特徴とする請求項1記載の多層配線基板の製造方法。 6. An interlayer insulating film is a method for manufacturing a multilayer wiring board according to claim 1, wherein the a photosensitive polyimide.
JP4739895A 1995-03-07 1995-03-07 Manufacture of multilayer interconnection board Granted JPH08250857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4739895A JPH08250857A (en) 1995-03-07 1995-03-07 Manufacture of multilayer interconnection board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4739895A JPH08250857A (en) 1995-03-07 1995-03-07 Manufacture of multilayer interconnection board

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Publication Number Publication Date
JPH08250857A true true JPH08250857A (en) 1996-09-27

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JP4739895A Granted JPH08250857A (en) 1995-03-07 1995-03-07 Manufacture of multilayer interconnection board

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998027798A1 (en) * 1996-12-19 1998-06-25 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
JP2005225228A (en) * 2004-01-13 2005-08-25 Ube Ind Ltd Polyimide metal laminate and circuit substrate
JP2009038390A (en) * 2008-09-29 2009-02-19 Ibiden Co Ltd Method for manufacturing multilayer printed wiring board
JP2009076934A (en) * 1997-12-29 2009-04-09 Ibiden Co Ltd Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
US7737366B2 (en) 1998-02-26 2010-06-15 Ibiden Co., Ltd. Multilayer printed wiring board with filled viahole structure

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Publication number Priority date Publication date Assignee Title
US7712212B2 (en) 1996-12-19 2010-05-11 Ibiden Co., Ltd. Method for manufacturing printed wiring board
US6835895B1 (en) 1996-12-19 2004-12-28 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US6930255B2 (en) 1996-12-19 2005-08-16 Ibiden Co., Ltd Printed circuit boards and method of producing the same
USRE43509E1 (en) 1996-12-19 2012-07-17 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US7361849B2 (en) 1996-12-19 2008-04-22 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US7371976B2 (en) 1996-12-19 2008-05-13 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US7385146B2 (en) 1996-12-19 2008-06-10 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US7388159B2 (en) 1996-12-19 2008-06-17 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US7449791B2 (en) 1996-12-19 2008-11-11 Ibiden Co., Ltd. Printed circuit boards and method of producing the same
US7585541B2 (en) 1996-12-19 2009-09-08 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
WO1998027798A1 (en) * 1996-12-19 1998-06-25 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US7615162B2 (en) 1996-12-19 2009-11-10 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
JP4522471B2 (en) * 1997-12-29 2010-08-11 イビデン株式会社 Method for manufacturing a multilayer printed wiring board and multilayer printed wiring board
JP2009076934A (en) * 1997-12-29 2009-04-09 Ibiden Co Ltd Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
US7737366B2 (en) 1998-02-26 2010-06-15 Ibiden Co., Ltd. Multilayer printed wiring board with filled viahole structure
US8115111B2 (en) 1998-02-26 2012-02-14 Ibiden Co., Ltd. Multilayer printed wiring board with filled viahole structure
US8987603B2 (en) 1998-02-26 2015-03-24 Ibiden Co,. Ltd. Multilayer printed wiring board with filled viahole structure
JP4529695B2 (en) * 2004-01-13 2010-08-25 宇部興産株式会社 Polyimide-metal laminate and polyimide circuit board
JP2005225228A (en) * 2004-01-13 2005-08-25 Ube Ind Ltd Polyimide metal laminate and circuit substrate
JP2009038390A (en) * 2008-09-29 2009-02-19 Ibiden Co Ltd Method for manufacturing multilayer printed wiring board

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