JP2777020B2 - Wiring layer flattening method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for flattening a wiring layer for high-speed signal transmission.

[0002]

2. Description of the Related Art With the increase in the degree of integration and the scale of LSIs, the area required for wiring to be formed on a chip has increased, and it has become increasingly important to provide multilayer wiring and finer patterns. The horizontal dimensions of patterns such as wiring and connection holes are miniaturized according to the scaling rule, while the vertical dimensions such as the thickness of wiring and insulating films are determined by wiring resistance, stray capacitance, dielectric strength and dielectric strength. It is necessary to maintain the reliability such as the migration property, and it is difficult to miniaturize as much as in the horizontal direction. In addition, since the patterns of the wirings and the connection holes are formed by highly anisotropic etching for miniaturization, the shape of the end face of the pattern becomes steep. Further, since the wiring is multi-layered, the surface of the wiring layer is inevitably uneven. Such irregularities on the surface
This leads to a decrease in processing accuracy, disconnection of wiring, and a reduction in reliability. Further, the aspect ratio of the connection hole connecting the wirings is also increased, so that the connection hole is disconnected and the reliability is reduced. As a means for solving such a problem, flattening technology of an insulating film and flattening of wiring are indispensable technologies for the development of a next-generation thin-film multilayer substrate.

Conventionally, there are a polishing method and a dry etching method described below as a planarization technique for a wiring layer.

FIGS. 7 and 8 show manufacturing process diagrams for explaining flattening of wiring and insulating layers by conventional polishing. Substrate 10 (for example, alumina, polyimide, etc.)
The upper surface is previously subjected to a surface treatment such as roughening (FIG. 7A).

Next, a current film 1 is placed on a substrate 10.
2 is formed by a vacuum evaporation method, an electroless plating method, or the like (FIG. 7B).

The current film 12 is used as a current supply conductor when formed by electrolytic plating, and is formed as a thin film as compared with a wiring conductor layer described later.

Next, a resist pattern 14 (14) is used as a plating mask for forming the wiring conductor layer into a predetermined shape.
a to 14d) are formed. At this time, the resist pattern is formed by forming a resist film once by spin coating of a photosensitive liquid resist, and then performing predetermined exposure and development to form a resist opening 16a corresponding to the wiring conductor layer pattern. To 16c (FIG. 7C).
The plating mask 14 may be formed by laminating a photosensitive dry film and then etching.

Here, the plating masks 14a to 14c
Is to change the viscosity of the liquid resist to be used, the number of rotations during spin coating, or the film thickness of the dry film to absorb variations in electrolytic plating when forming the wiring conductor layer, and to improve the resist opening. The wiring conductor layer deposited in 16a to 16c is formed by controlling so as not to exceed the resist film thickness.

Next, wiring conductor films 18a to 18c are formed by electrolytic plating. ((D) of FIG. 7). Usually, the thickness of the wiring conductor films 18a to 18c formed by plating varies within the substrate, and further varies depending on the size of the substrate and the density of the wiring. Therefore, when the required wiring conductor is formed only by electrolytic plating, as shown in FIG. 7D, the thickness of the desired wiring conductor layers 18a to 18c varies, and the surface of the conductor film has irregularities. Occur.

For this reason, in the conventional example, in order to remove the variation of the conductor layer and the unevenness of the surface in a polishing step described later,
The wiring conductor layers 18a to 18c are formed in advance with a margin for polishing (FIG. 7D).

Next, the plating masks 14a to 14d are removed, and subsequently, the portions of the current film 12 exposed in the openings 16a to 16c on the substrate 10 are removed by etching. In this case, the wiring conductor layers 18a to 18a
8c formed under the current film 8c.
The portion 2c remains as it is (FIG. 7E). Note that, as a material of the current film, for example, a laminate of chromium (Cr) and copper (Cu) is used, and as a wiring conductor, copper (Cu) or the like is used.

Next, a preliminary insulating film 20 is applied so as to fill the remaining current films 12a to 12c and the wiring conductor films 18a to 18c formed on the substrate. At this time, an appropriate method such as a bar coating method, a printing method, and a spin coating method is used.

Thereafter, the material applied by a suitable method is cured to form an insulating layer preliminary film 20. The preliminary film 20 for the insulating layer has irregularities depending on the presence or absence of the underlying wiring conductor films 18a to 18c (FIG. 8A).

Next, in order to flatten the wiring conductor films 18a to 18c and the insulating layer preliminary film 20, the insulating layer preliminary film 20 is formed.
Is polished and flattened until the surface of the wiring conductor film embedded therein is exposed. At this time, the entire surface of the preliminary film for the insulating layer is always cut with the same dimensions as the substrate 10 except for the uneven portions of the conductor layer formed initially using a polishing platen. For this reason, a constant frictional force always acts on the surface. Therefore, in order to control the film thickness after polishing, the exposed state of the wiring conductor layer is visually checked during polishing. Further, the thickness of the insulating layer was measured by optical means. At this time, polishing scratches 22 are formed on the insulating layers 20a to 20c formed by polishing. When the current film 12 is further formed on the surface having such polishing flaws 22 to form the upper conductor layer 26, there is a problem that irregularities of the polishing flaws 22 appear as irregularities on the surface of the upper conductor layer 26 as they are. there were. Furthermore, there is a problem that it is difficult to flatten the surface due to an extreme difference in hardness between the wiring conductor layer and the insulating layer preliminary film, and the metal portion becomes convex.

FIGS. 9 and 10 show an example of a manufacturing process for flattening a wiring conductor layer and an insulating layer using a conventional dry etching method.

First, a substrate 10 is prepared (FIG. 9A), and a current film 12 is formed on the substrate 10 by a vacuum evaporation method or an electroless plating method (FIG. 9B). ).

Thereafter, after a resist material is applied, openings 16a to 16c and resist patterns 14a to 14c for forming a wiring conductor layer are formed by forming a resist pattern.
14d is formed (FIG. 9C).

Next, plating is deposited by electrolytic plating or the like so as to have a thickness substantially equal to the thickness of the resist pattern, thereby forming wiring conductor layers 19a to 19c.

The manufacturing process up to this point is the same as the above-mentioned polishing method.

Next, thin-film metal layers 17a to 17c are formed on the wiring conductor layers 19a to 19c. This thin metal layer 1
7a to 17c are performed for the purpose of ensuring adhesion to the insulating layer film 20 described later and preventing surface oxidation of the wiring conductor. The thin film metal layers 17a to 17c are formed by using an electrolytic plating method, a lift-off method, or the like (FIG. 9D).

Next, the resist patterns 14a to 14d are removed by etching, and the resist patterns 14a to 14d of the current film 12 formed on the substrate are further removed.
The portion located below 4d is removed by etching. At this time, the current films 12a to 12c formed below the wiring conductor films 19a to 19c remain as they are (FIG. 9E).

Next, a resin 20a for an insulating layer is coated by a bar coating method so as to embed the current films 12a to 12c, the conductor films 19a to 19c for wiring, and the thin film metal layers 17a to 17c formed on the substrate 10. , A printing method, a spin coating method and the like. After that, the insulating layer resin 20a is cured by a desired method to form the insulating film 20 (FIG. 10A).

Next, after an etch-back resist is applied on the insulating layer film 20, it is dried to form a flattening sacrificial film 21 (FIG. 10B).

Thereafter, the flattening sacrificial film 21 and the insulating layer film 20 are etched from the surface by a dry etching method using oxygen plasma or the like. At this time, the etching amount is controlled so that the desired thickness h of the insulating layer is obtained. The surface of the insulating layer can be flattened by maintaining the surface flatness by making the etching rates of the flattening sacrificial film 21 and the insulating layer film 20 equal (FIG. 10C).

At this time, if the thickness of the wiring conductor layers 19a to 19c is not uniform, when the upper conductor layer 23 is formed,
As shown by a circle in the figure, a poor connection portion 24 and a convex portion of the wiring occur.

[0026]

In the above-mentioned conventional method of flattening an insulating layer by polishing, polishing is performed after formation of a film for an insulating layer. It is difficult to determine the minimum value of the film thickness in the wiring conductor layer. Further, there is a problem that it is difficult to control the film thickness of the insulating layer to a constant value because the film thickness of the wiring conductor layer by plating varies. In addition, polishing flaws are liable to occur on the surface of the insulating layer due to polishing, and in the case of forming a multilayer thin film layer by laminating upper wiring conductor layers, there is a problem that unevenness of polishing flaws is accumulated. Furthermore, since the surface is polished after the formation of the insulating layer film, the thin film metal of the adhesive film is scraped off. Therefore, when it is necessary to form the thin film metal layer again on the wiring conductor film, there is also a problem that the thin film metal layer cannot be formed because there is no current film.

Next, in the above-described conventional etch-back method by dry etching, there is a variation in the thickness of the wiring conductor layer which occurs at the time of pattern plating, and a flattening sacrificial film is formed as it is. In addition, when the etch back is performed, a portion where the wiring conductor layer is not exposed from the insulating layer and a portion where the wiring conductor layer is excessively exposed occur.

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to make the thickness of a wiring conductor layer uniform, remove surface flaws generated on an insulating layer,
An object of the present invention is to evenly flatten the surfaces of a wiring conductor layer and an insulating layer by an etch-back method.

[0029]

According to the present invention, there is provided, according to the present invention, a step of: (a) forming a plating base conductor on a base substrate; and (b) forming a plating base conductor on the plating base conductor. A step of forming a resist pattern; (c) a step of burying openings other than the resist pattern to form a wiring preliminary conductor layer having a thickness larger than the thickness of the resist pattern; and (d) a step of forming the resist pattern. Polishing the portion of the wiring preliminary conductor layer protruding from the resist pattern while leaving the resist pattern substantially, thereby forming a wiring conductor layer having a flattened top portion; and (e) forming the resist pattern. Forming a wiring layer by removing the lower part of the resist pattern in the portion of the underlying conductor for plating, and then providing a preliminary film for an insulating layer covering the wiring layer on the underlying substrate. , (F) etch Using click method, characterized by comprising a step of planarizing the entire surface by etching the preliminary film for the insulating layer to the top of the wiring layer.

The step (d) preferably includes a step of selectively forming another wiring conductor layer on the top of the flattened wiring conductor layer.

[0031]

According to the above-described method for manufacturing a multilayer wiring board of the present invention, the underlying conductor for plating is formed on the underlying substrate. Therefore, a wiring conductor layer formed by plating or another wiring conductor layer (also referred to as a thin film metal layer) can be provided. Further, a resist pattern is formed on the underlying conductor for plating. The resist pattern at this time
By setting the thickness of the wiring layer to a value close to the thickness of the wiring conductor layer to be formed in a later step, the thickness of the wiring conductor layer can be easily determined. Also, resist pattern
The wiring preliminary conductor layer formed by burying the opening between the electrodes may be formed to be thicker than the resist pattern film thickness, so that the plating can be easily controlled. In addition, the portion of the wiring spare conductor layer protruding from the resist pattern is polished while substantially leaving the resist pattern, to form a wiring conductor layer having a flattened top. Therefore, even if polishing scratches generated during polishing are on the surface of the resist pattern which is a soft material, the resist pattern will be removed in a later step, so that there is no problem. After the resist pattern is removed, the unnecessary current film is removed, and the remaining current film and the wiring conductor layer are called a wiring layer. A preliminary film for an insulating layer covering the wiring layer is provided. At this time, since the preliminary film for the insulating layer is formed on the wiring layer having the irregularities, the surface of the preliminary film for the insulating layer is also irregularly influenced by the underlayer. In order to flatten this, the wiring layer can be exposed from the preliminary film for the insulating layer by using an etch-back method. The preliminary film for the insulating layer formed by this etch back is called an insulating layer. At this time, flat surfaces are formed on both the wiring layer and the insulating layer.

Further, by covering the wiring conductor layer with a thin-film metal layer, it is possible to prevent the wiring conductor layer from being oxidized, and to measure the adhesion to the insulating layer. The multilayer wiring board formed by laminating the wiring layer and the insulating layer on the wiring layer and the insulating layer thus formed as a base can further increase the number of layers as compared with the related art.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. The drawings merely schematically show the dimensions, shapes, and arrangements of the components to the extent that these inventions can be understood. Further, in the following description, specific materials and conditions will be described, but these materials and conditions are only one suitable example, and therefore, the present invention is not limited to these.

FIGS. 1 to 4 show a manufacturing process in an embodiment of the present invention.

Next, the outline of the manufacturing process of this embodiment is shown in FIG.
This will be described with reference to FIG.

First, in the present invention, a plating base conductor 12 is formed on a base substrate 10. In this embodiment, a substrate 10 is prepared as a base. Then, an underlayer for plating (this is called a current film) 1 on the substrate 10.
Form 2 Resist patterns 31a to 31d are formed on the current film 12 by photolithography. At this time, an opening for plating out the wiring conductor layer is formed.

Subsequently, a resist pattern is formed by plating.
Resist pattern 31a so as to fill the opening outside the pattern.
The preliminary conductor layers 32a to 32c for wiring are formed by performing plating thicker than the film thickness of the wirings 31d to 31d (FIG. 1A).

Thereafter, the resist patterns 31a to 31d
Is substantially polished, and the protruding portions of the wiring preliminary conductor layers 32a to 32c are polished to the height of the film thickness. Thus, the polished resist patterns 33a to 33d (the polished resist patterns are also referred to as plating mask resists) and the wiring conductor layer 35 having a flattened top portion.
a to 35c are formed (FIG. 1B).

Subsequently, according to the present invention, after removing the resist patterns 33a to 33d and the underlying portion of the plating underlying conductor 12, a preliminary insulating film for the insulating layer covering the wiring conductor layers 35a to 35c is used as the underlying layer. Provided on the substrate 10. Therefore, in this embodiment, first, the resist patterns 33a to 33a to
Using the current film 12 on the wiring conductor layers 35a to 35c with the 33d remaining, other wiring conductor layers (also referred to as thin film metal layers) 36a to 36c are formed by electrolytic plating, respectively.

Thereafter, the resist patterns 33a to 33d
Is removed, and the current film 12 on the substrate 10 is removed.
Is removed by any suitable etching. At this time, the current film portions 12a to 12c formed between the substrate 10 and the wiring conductor layers 35a to 35c are left as they are. Subsequently, the current films 12a to 12c, the wiring conductor layers 35a to 35c, and the thin film metal layers 36a to 36c formed on the substrate 10 are buried in the preliminary film for the insulating layer. This preliminary film is made of, for example, an insulating resin such as polyimide.

Subsequently, for example, on this insulating layer preliminary film,
After laminating a planarizing sacrificial film such as a resist, the preliminary film for the insulating layer is planarized by the etch-back method, and the top of the conductor layer for wiring is removed from the preliminary film for the insulating layer. Layers 36a to 36c or wiring conductor layer 35
a to 35c are exposed (FIG. 1C). At this time,
The remaining portions of the preliminary film are insulating layers 40a, 40b, 4
0c and 40d.

Next, the manufacturing process of the present invention will be described in detail with reference to FIGS.

As the substrate 10, for example, a substrate formed by applying a polyimide resin on a ceramic substrate or the like is used, and a current film 12 is formed on the substrate by a vacuum evaporation method or an electroless plating method. At this time, it is preferable to perform a surface treatment such as roughening on the substrate 10 as necessary (FIG. 2A). Current film 12
Is a current supply conductor (electrode) for forming a wiring conductor by electrolytic plating, and is formed as a thin film as compared with the wiring conductor. As a material of the current film 12, for example, a laminate of chromium (Cr) and copper (Cu) or a single copper (Cu) is used (FIG. 2B).

Next, a plating mask resist for forming the wiring conductor layer to a desired film thickness is applied to the entire surface of the substrate 10 (not shown). The application of the resist is preferably performed by spin coating of a photosensitive resist. After the application of the resist, exposure and development are performed under suitable conditions to form resist patterns 31a to 31d for wiring patterns. At this time, resist openings 16a to 16c for exposing the plating base and forming the wiring conductor layer are formed (FIG. 2C). In addition,
Instead of this resist pattern, a photosensitive dry film may be laminated and patterned to obtain a pattern.

Next, all the wiring conductors are made of resist patterns.
Electroplating is performed which is thicker than the film thickness of the electrodes 31a to 31d. At this time, since the resist openings 16a to 16c have different shapes, it is necessary to set plating conditions in accordance with the plating conditions of the slowest deposition portion. The surface of the wiring spare conductor layer formed in this way has irregularities (FIG. 2D). In addition, it is preferable to use, for example, copper (Cu) as the plating metal.

Next, the wiring auxiliary conductor layer deposited by electrolytic plating in the wiring auxiliary conductor layer forming step protrudes from the surface of the resist pattern. This protruding portion is cut using a polishing platen. At this time, since the frictional resistance rapidly increases when the resist pattern comes into contact with the surface, the polishing can be easily completed on the resist pattern surface. Accordingly, the thickness of the wiring conductor layers 35a to 35c after polishing is about the thickness h of the resist patterns 31a to 31c. Also,
This polishing can reduce the variation in the film thickness of the wiring conductor layers 35a to 35c. Further, polishing scratches 34 are generated on the polished resist patterns 33a to 33d by polishing (FIG. 2E). However, this polishing scratch 34
There is no problem because the polishing flaw is removed at the same time when the resist pattern is removed in a later step (see FIG. 3B).

Next, the other wiring conductor layers 36a to 36c
(This is called a thin metal film.)
35A (FIG. 3A). The formation of the thin metal films 36a to 36c is performed by an electrolytic plating method or a lift plating method.
This is performed using the off method. These thin metal films 36a to 36c
Is performed to secure adhesion to an insulating layer formed in a later step and to prevent surface oxidation of the wiring conductor layers 35a to 35c. Therefore, when a wiring conductor layer which has good adhesion to the insulating layer and does not cause surface oxidation is used, this step is omitted (see FIGS. 5 and 6).

Next, after removing the resist patterns 33a to 33d, the current film 1 on the substrate 10 is further removed.
2 is removed by any suitable etching. As a result, the current films 12a to 12
c, wiring conductor layers 35a to 35c and thin film metal film 36
Wiring layers 37a to 37c including a to 36d are formed (FIG. 3C).

Next, a varnish resin, for example, a polyimide precursor or the like is applied so as to cover the wiring conductor layers 37a to 37c formed on the substrate 10. At this time, any one of a bar coating method, a printing method, a spin coating method and the like is used.
Then, after the varnish resin is cured by any suitable method, a preliminary film 20 for an insulating layer is formed (FIG. 3D).

The surface of the insulating layer preliminary film 20 has irregularities depending on the presence or absence of the lower wiring conductor layer 37. The unevenness formed on this surface causes the wiring conductor layer to vary in the subsequent process of forming the upper wiring layer. Therefore, in the embodiment of the present invention, it is preferable to use an etch-back method as a method of flattening the preliminary film 20 for an insulating layer.

Next, the flattening of the insulating layer preliminary film 20 by the etch back method will be described.

An etch-back resist film 38 (also referred to as a flattening sacrificial film) is coated on the insulating layer preliminary film 20 having irregularities on the surface by a spin coating method or the like.
To go. The flattening sacrificial film 38 has a small film loss when dried, and its surface flatness is not affected by the lower insulating layer preliminary film 20 due to drying after coating.

After the flattening sacrificial film 38 is formed, etching is performed by adjusting the etching rates of the flattening sacrificial film 38 and the preliminary film for insulating layer 20 to be equal using a dry etching method using oxygen plasma. And the insulating layer 4
0a to 40c are formed.

At this time, the etching is performed until the tops of the wiring conductor layers 37a to 37c are exposed on the surface of the insulating layer preliminary film 20. Insulating layers 40a to 40c formed by etch back
The surface of the surface 40c does not have any surface flaws caused by polishing.

When forming a multilayer wiring, the above-described manufacturing steps are repeated.

In the above-mentioned manufacturing process, the pattern plating of the wiring conductor layer mainly using the electroplating method has been described, but the wiring conductor layer may be formed using electroless plating or the like.
In the case of electroless plating, instead of the underlying conductor for plating, a catalyst nucleus for depositing a metal is adsorbed on the substrate, and the substrate may be immersed in any other suitable plating solution to perform desired plating.

In this embodiment, an inorganic material is used as the material of the substrate 10, but the same effect can be obtained by using a resin.

<Modification of First Embodiment> This modification is a case where it is not necessary to form other wiring conductor layers 36a to 36c (thin film metal layers) in the first embodiment.

FIGS. 5 and 6 show the thin film metal layers 36a to 36c.
FIG. 9 is a diagram for explaining a manufacturing process when no is used.

The manufacturing process up to (A) of FIG.
2A to 2D of FIG. 2 are omitted because they are the same.

FIG. 5A shows the substrate 10, the current film 12, the resist patterns 33a to 33d, and the wiring conductor layers 35a to 35c formed by polishing. Next, the resist patterns 33a to 33d are removed by using any suitable method. Subsequently, the current film 12 exposed on the substrate 10 is further etched to leave the remaining current films 12a to 12a on the substrate 10.
c and the wiring conductor layers 35a to 35c are formed. In this modification, a combination of the current films 12a to 12c and the wiring conductor layers 35a to 35c is used as the wiring conductor layer 42.
((C) in FIG. 5).

Next, after coating and drying and curing the varnish-like insulating resin so as to cover the wiring conductor layer 42, a preliminary film 20 for the insulating layer is formed (FIG. 5D).

Next, a flattening sacrificial film 38 is coated on the insulating layer preliminary film 20, and the insulating layer preliminary film 20 is planarized by a dry etching method using oxygen plasma or the like to form insulating layers 40a to 40d. (FIGS. 6A and 6B).

The manufacturing method of FIGS. 5A to 5D and FIGS. 6A and 6B may be performed in the same manner as in the first embodiment.

[0065]

As is clear from the above description, according to the method for planarizing a wiring layer of the present invention, a resist pattern is formed after forming a plating base conductor on a substrate. For this reason, the thickness of the plating can be easily controlled by filling the resist opening and forming a wiring preliminary conductor layer thicker than the thickness of the resist pattern.

Further, since the film thickness of the wiring conductor layer is made uniform by polishing, a defective connection between the wiring conductor layers is eliminated in the subsequent manufacturing process of the etch back method.

In the present invention, polishing flaws generated when the wiring preliminary conductor layer is polished to the resist pattern surface remove the resist pattern, so that polishing flaws remain on the surface of the insulating layer. There is no.

Accordingly, no polishing flaws remain, the thickness of the wiring conductor layer is uniform, and the surface of the insulating layer can be formed flat. Further, as shown in the modified example, when the material of the wiring conductor layer has good adhesion to the insulating layer and the conductor layer material is resistant to oxidation, the process of the thin film metal layer can be omitted.
Therefore, workability is also improved.

[Brief description of the drawings]

1 (A) to 1 (C) are process diagrams illustrating basic processes of the present invention.

FIGS. 2A to 2E are process diagrams for explaining a manufacturing process of this embodiment.

3 (A) to 3 (D) are process diagrams for explaining a manufacturing process of this embodiment following FIG. 2;

4 (A) and 4 (B) are process diagrams for explaining a manufacturing process of this embodiment following FIG. 3;

FIGS. 5A to 5D are process diagrams for describing a manufacturing process diagram showing a modification of the first embodiment; FIGS.

FIGS. 6A and 6B are process diagrams following the process of FIG. 5;

FIGS. 7A to 7E are process diagrams for explaining a manufacturing process by a conventional polishing method.

8 (A) to 8 (C) are manufacturing process diagrams by a conventional polishing method following the process of FIG. 7;

FIGS. 9A to 9E are manufacturing process diagrams by a conventional etch-back method.

FIGS. 10A to 10D are manufacturing process diagrams by a conventional etch-back method following the process of FIG. 9;

[Explanation of symbols]

 10: substrate 12, 12a to 12c: current film 16a to 16c: resist opening 20: preliminary film for insulating layer 31a to 31d: resist pattern 32a to 32c: preliminary conductor layer for wiring 33a to 33d: resist pattern after polishing -34: Polishing flaws 35a to 35c: Wiring conductor layers 36a to 36c: Thin metal layers 37a to 37c: Wiring conductor layers 38: Flattening sacrificial films 40a to 40d: Insulating layers

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-54-149867 (JP, A) JP-A-3-268392 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H05K 3/46 H05K 3/22

Claims (2)

(57) [Claims] 1. A step of forming a base conductor for plating on a base substrate, a step of forming a resist pattern on the base conductor for plating, and a step of forming a resist pattern other than the resist pattern. Forming a wiring preliminary conductor layer having a thickness greater than the thickness of the resist pattern by filling the opening; and (d) wiring protruding from the resist pattern with the resist pattern substantially remaining. Forming a wiring conductor layer having a flattened top by polishing a portion of the auxiliary conductor layer for wiring, and (e) a portion of the resist pattern and the portion of the base conductor for plating below the resist pattern. (C) providing a preliminary film for an insulating layer covering the wiring layer on the undersubstrate after removing the portion to form a wiring layer; and (f) removing the preliminary film for the insulating layer using an etch-back method. To the top of the wiring layer Planarization method of the wiring layer, which comprises a step of planarizing the entire surface by etching. 2. The method for planarizing a wiring layer according to claim 1, wherein the step (d) includes a step of selectively forming another wiring conductor layer on top of the flattened wiring conductor layer. A method for planarizing a wiring layer, comprising: