JPH05218645A - Manufacture of thin multilayer wiring board - Google Patents

Abstract

PURPOSE:To get a flat surface layer without restriction on design of pattern. CONSTITUTION:A via hole 5 is made in the insulating layer 3 overlaid on an insulating substrate 1 where a conductor pattern 2 is made, and a protective layer 6 is made all over the surface, and then the copper being a conductive material is grown into a film by electrolytic plating until the via hole 5 is stopped completely and further the surface is flattened, and then the needless copper is removed as far as the amount of the wiring on the insulating layer 3, thus a desired shape is gotten.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film multilayer wiring board.

[0002]

2. Description of the Related Art In a thin film multilayer wiring board, particularly in a thin film multilayer wiring board in which polyimide is an insulating layer and copper is a conductor layer, when a via hole is provided in an insulating layer to connect upper and lower conductor layers, the polyimide and copper react with each other. Therefore, there is a problem that the conductor layer is peeled off from the insulating layer. Therefore, as shown in FIG. 4, a protective layer 15 and a cover layer 16 which are hard to react with polyimide such as Cr or Ni are formed between the insulating layer 13 made of polyimide and the conductor layer 12 made of copper, and insulation is performed. It was necessary to prevent deterioration due to the reaction between the layer 13 and the conductor layer 12. In FIG. 4, 14 is a via hole.

[0003]

However, when the protective layer 15 and the cover layer 16 are formed between the insulating layer 13 and the conductor layer 12 as described above, the conductor layer 12 is usually formed by sputtering. Therefore, it is difficult to form pillars, and the conductor layer 12 is formed in the via hole 14 only by the thickness of the wiring layer. Therefore, in the case of multilayering as shown in FIG. 4, it is necessary to shift the position further from the upper or lower via hole 14, and if the via holes 14 are stacked vertically, the aspect ratio becomes large and there is a risk of disconnection. However, there was a problem that there were restrictions on pattern design. In addition, the insulating layer 13 is formed in the concave portion in the via hole 14.
Therefore, the flatness of the surface is poor as shown in FIG. 4, and it is difficult to form a fine conductor pattern.

The object of the present invention is to solve the above problems,
An object of the present invention is to provide a method for manufacturing a thin-film multilayer wiring board that can obtain a flat surface layer without any restrictions on pattern design.

[0005]

According to a method of manufacturing a thin film multilayer wiring board of the present invention, a via hole is formed in an insulating layer adhered to an insulating board on which a conductor pattern is formed, and a protective layer is formed on the entire upper surface thereof. After the formation, copper, which is a conductor material, is formed by electrolytic plating until the via holes are sufficiently filled and the surface is flattened, and then unnecessary copper is removed to the wiring portion on the insulating layer. It is characterized by obtaining a desired shape.

[0006]

In the above-mentioned structure, a thickness of 10 to 50 μm made of, for example, polyimide provided by means such as spin coating
A protective layer made of Cr, Ni, Ti, Mo, etc. on the insulating layer and in the via hole with a diameter of 10 to 100 μm, and then copper, which is a conductor material, is electroplated on the protective layer instead of sputtering as in the conventional method. The film can be formed until the inside of the via hole is sufficiently filled and the surface is flattened. As a result, the via holes can be provided at the same position, the restriction on the pattern design can be eliminated, and the surface can be made flat.

[0007]

1 (a) to 1 (g) are views showing an example of a method of manufacturing a thin film multilayer wiring board according to the present invention in the order of steps. First,
As shown in FIG. 1A, a conductor layer 2 having a three-layer structure of chromium (protective layer 6) -copper-nickel (cover layer 8) is formed on the upper surface of an insulating substrate 1 made of ceramics by sputtering, electrolytic plating, and electroless plating. It is formed by a method such as plating. The conductor layer 2 has a thickness of about 5 to 10 μm. Next, as shown in FIG. 1B, an insulating layer 3 made of non-photosensitive polyimide is formed, and aluminum is formed on the insulating layer 3 and patterned to form a mask 4. The thickness of the insulating layer 3 is 10 to 50.
It is about μm. Next, as shown in FIG. 1C, a via hole 5 having a taper angle of 45 ° to 135 ° is formed by anisotropic etching of reactive ion etching using the mask 4. The diameter of the via hole 5 is about 10 to 100 μm.

Next, the mask 4 is removed by wet or dry etching, and chromium is deposited as a protective layer 6 by sputtering as shown in FIG. 1 (d). Further, as a protective layer 6 made of chromium and an adhesive layer of plated copper, copper is deposited on the protective layer 6 by sputtering so as to have a diameter and a thickness of the via holes 5 on the insulating layer, and then, as shown in FIG. As shown in, copper 7 is plated by electrolytic plating until the surface becomes flat. Finally, as shown in FIG. 1 (f), copper is etched to a desired thickness by wet etching, and as shown in FIG. 1 (g), patterning is performed using a mask to form a further wiring board. Then, by repeating the above steps, a thin film multilayer wiring board of the present invention as an example of which is shown in FIG. 2 is obtained.

As for the flatness of the electrolytically plated copper 7, as shown in FIG. 3A, d is the via diameter, and H is H.
Is defined as the via depth, T is the plated copper thickness, and h is the flatness, and h is flat when h ≦ H / 5. For example, if T is about d / 2 as shown in FIG.
Is not flat because it does not satisfy the above condition,
As shown in (c), when T is about d / 2 + α (α = d / 2), it is determined that h satisfies the above condition and is flat.

In the above embodiment, the conductor layer 2
The three-layer structure of chrome-copper-nickel forming the above may be any structure of chrome-copper-chromium, titanium-copper-nickel and titanium-copper-chromium.
4 such as copper-nickel, titanium-molybdenum-copper-chromium
It may have a layered structure. In addition, as the material of the insulating layer 3,
Photosensitive polyimide can also be used. Further, the aluminum used as the mask 4 may be a resist, nickel, chromium, titanium, molybdenum, or tungsten, and may be SiO ₂ or Si ₃ N ₄ .

Further, the reactive ion etching for forming the via hole 5 may be reactive ion beam etching, excimer laser etching, or magnetron etching. The anisotropic etching at this time may be wet etching, isotropic etching such as O ₂ plasma etching, or a photosensitive polyimide developing step. In this case, the taper angle may be 0 ° to 90 °. Further, chromium as the protective layer 6 may be formed by vapor deposition, and may be nickel, titanium, tungsten, aluminum, or an alloy thereof in addition to chromium. Further, the copper of the adhesive layer may be formed by an electroless plating method. Further, the etching of copper may be dry etching.

[0012]

As is apparent from the above description, according to the present invention, a via hole having a protective layer is provided with copper by electrolytic plating until the inside of the via hole is sufficiently filled and the surface is flattened. Since unnecessary copper is removed, it is possible to obtain a flat via hole with a vaporized surface completely filled with copper, and it is possible to stack via holes at the same position, and there are no restrictions on pattern design. A thin film multilayer wiring board having a flat surface can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a method of manufacturing a thin film multilayer wiring board according to the present invention in the order of steps.

FIG. 2 is a diagram showing an example of a thin film multilayer wiring board of the present invention.

FIG. 3 is a diagram for explaining the flatness of the copper plating 7 in the present invention.

FIG. 4 is a diagram showing an example of a conventional thin-film multilayer wiring board.

[Explanation of symbols]

 1 Insulating Substrate 2 Conductor Layer 3 Insulating Layer 4 Mask 5 Via Hole 6 Protective Layer 7 Copper 8 Cover Layer

Claims (1)

[Claims] 1. A via hole is formed in an insulating layer adhered to an insulating substrate on which a conductor pattern is formed, a protective layer is formed on the entire upper surface of the via hole, and then copper, which is a conductive material, is electroplated. Manufacture of a thin film multilayer wiring board characterized by forming a film until the via holes are sufficiently filled and the surface is flattened, and then unnecessary copper is removed up to the wiring on the insulating layer to obtain a desired shape Method.