JPS62188343A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62188343A JPS62188343A JP61028853A JP2885386A JPS62188343A JP S62188343 A JPS62188343 A JP S62188343A JP 61028853 A JP61028853 A JP 61028853A JP 2885386 A JP2885386 A JP 2885386A JP S62188343 A JPS62188343 A JP S62188343A
- Authority
- JP
- Japan
- Prior art keywords
- base metal
- metal
- layer
- bump
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 67
- 239000002184 metal Substances 0.000 claims abstract description 67
- 239000010953 base metal Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000009713 electroplating Methods 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims description 22
- 239000010931 gold Substances 0.000 claims description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 13
- 238000007772 electroless plating Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010949 copper Substances 0.000 abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052802 copper Inorganic materials 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 6
- 239000010409 thin film Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Electroplating Methods And Accessories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は突起型金属電極（金属バンプ）を有する半導体
装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having a protruding metal electrode (metal bump).
従来、半導体装置を外部に電気接続するための端子とし
て基板表面に突出形成した金属バンプが用いられている
。この金属バンプの形成方法としては、第２図に示す方
法が提案されている。Conventionally, metal bumps protruding from the surface of a substrate have been used as terminals for electrically connecting a semiconductor device to the outside. As a method for forming this metal bump, a method shown in FIG. 2 has been proposed.
即ち、第２図（ａ）のように、シリコン基板１１上に設
けたシリコン酸化膜等の絶縁膜１２上にアルミニウム等
の金属膜からなる配線を形成し、その一部をパッド１３
として構感する。そして、この上にＣＶＤシリコン酸化
膜等の絶縁膜１４を被覆形成しかつこれに窓１５を開設
してパソ！″１３を開口する。That is, as shown in FIG. 2(a), a wiring made of a metal film such as aluminum is formed on an insulating film 12 such as a silicon oxide film provided on a silicon substrate 11, and a part of the wiring is formed on a pad 13.
I think of it as. Then, an insulating film 14 such as a CVD silicon oxide film is formed on top of the insulating film 14, and a window 15 is formed thereon. Open ``13.''
次いで、同図（ｂ）のように複数の下地金属層１６．１
７等を全面に被着する。また、これら下地金属層１６．
１７上に感光性樹脂膜１８を形成しかつこれをパターニ
ングして、前記パッド１３及び窓１５を含む領域を開口
する。そして、前記下地金属層１６．１７を共通電極と
して銅（Ｃｕ）等を前記パッド１３上に電着し、マツシ
ュルーム型の金属バンプ１９を形成する。Next, as shown in the same figure (b), a plurality of base metal layers 16.1
7 grade is applied to the entire surface. In addition, these base metal layers 16.
A photosensitive resin film 18 is formed on the photosensitive resin film 17 and patterned to open a region including the pad 13 and the window 15. Then, using the underlying metal layers 16 and 17 as a common electrode, copper (Cu) or the like is electrodeposited on the pad 13 to form a mushroom-shaped metal bump 19.
その後、同図（Ｃ）のように感光性樹脂膜１８を除去し
、続いて金属バンプ１９をマスクとして下地金属層１６
．１７を順次エツチング除去する。Thereafter, the photosensitive resin film 18 is removed as shown in FIG.
．． 17 is removed by etching in sequence.
そして、同図（ｄ）のように金属バンプ１９の表面に無
電解めっきを施して金（Ａｕ）等のめっき層２０を形成
することにより、最終的に金属バンプが完成される。Then, as shown in FIG. 2D, the surface of the metal bump 19 is electrolessly plated to form a plating layer 20 of gold (Au) or the like, thereby finally completing the metal bump.
上述した従来の製造方法では、基板上の異なる箇所に夫
々形成された金属バンプ１９は、パッド１３を介して夫
々固有の抵抗値でシリコン基板１１の拡散層に接続され
、さらに拡散層から基板１１の内部を通して基板裏面に
接続されることになる。そして、金属バンプ材料とシリ
コンとのイオン化傾向の差によって電池効果が影響し、
金属バンプとシリコンとの間に電流が流れるが、このよ
うに各金属バンプ１９が固有の抵抗値を有していると、
各金属ハンプ１９に流れる電流も夫々相違することにな
る。In the conventional manufacturing method described above, the metal bumps 19 formed at different locations on the substrate are connected to the diffusion layer of the silicon substrate 11 via the pads 13 with respective resistance values, and are further connected to the diffusion layer of the silicon substrate 11 from the diffusion layer. It will be connected to the back side of the board through the inside of the board. The battery effect is affected by the difference in ionization tendency between the metal bump material and silicon.
A current flows between the metal bumps and silicon, but if each metal bump 19 has its own resistance value,
The current flowing through each metal hump 19 is also different.
このため、金属ハンプ１９の表面に無電解めっき法によ
り金めつき層２０を形成する前記した従来方法では、各
金属バンプ１９を接続する共通電極が存在していないた
め、前記しためっき時の電流の相違が原因して各金属バ
ンプ１９における金めつき層２０の厚さが夫々異なる厚
さに形成されることになる。つまり、入力保護用の数に
Ωの抵抗が入っている金属バンプでは無電解めっき時に
めっき電流が流にくくなって金めつき層２０が薄くなり
、下地の金属バンプ１９が露呈され易くなる。Therefore, in the conventional method described above in which the gold plating layer 20 is formed on the surface of the metal hump 19 by electroless plating, there is no common electrode connecting each metal bump 19, so the current during the plating is Due to this difference, the gold plating layer 20 of each metal bump 19 is formed to have a different thickness. In other words, in the case of a metal bump in which a resistance of Ω is included in the number for input protection, the plating current becomes difficult to flow during electroless plating, the gold plating layer 20 becomes thin, and the underlying metal bump 19 is easily exposed.
このため、金めつき層２０の厚さが薄い金属バンプでは
金属バンプ１９表面の露呈によってボンディング特性や
導電特性等の信頼性の低下を招く恐れがあり、また多数
の金属バンプが存在する半導体装置では各金属バンプ１
９における金めつき層２０の厚さの相違によって各金属
バンプの高さがばらつき、実装時におけるボンディング
条件を均一に管理できないという問題が生じる。For this reason, in the case of a metal bump in which the gold plating layer 20 is thin, the surface of the metal bump 19 may be exposed, leading to a decrease in reliability such as bonding characteristics and conductive characteristics. Now each metal bump 1
The height of each metal bump varies due to the difference in the thickness of the gold plating layer 20 in 9, which causes a problem that bonding conditions during mounting cannot be uniformly controlled.
本発明の半導体装置の製造方法は、金属バンプ表面にお
けるめっき層を各金属バンプにおいて夫々均一な厚さに
形成し、半導体装置の信頼性の向上を図るものである。The method for manufacturing a semiconductor device of the present invention aims to improve the reliability of the semiconductor device by forming a plating layer on the surface of each metal bump to have a uniform thickness.
本発明の半導体装置の製造方法は、金属バンプの配設位
置を含む領域に第１及び第２の下地金属層を形成した上
で、これらを共通電極として金属バンプを形成し、その
後第２の下地金属層のみを除去しかつ残された第１の下
地金属層の表面を酸化して絶縁膜を成長させ、その上で
この第１の下地金属層を共通電極とした無電解めっき法
により金属バンプにめっき層を施し、その後に第１の下
地金属層を除去して金属バンプを完成する工程を含むも
のである。In the method for manufacturing a semiconductor device of the present invention, first and second base metal layers are formed in a region including a metal bump arrangement position, and then a metal bump is formed using these as a common electrode. Only the base metal layer is removed and the surface of the remaining first base metal layer is oxidized to grow an insulating film, and then metal is deposited by electroless plating using the first base metal layer as a common electrode. The method includes the steps of applying a plating layer to the bump and then removing the first base metal layer to complete the metal bump.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｆ）は本発明の一実施例を工程順に示
す断面図である。FIGS. 1(a) to 1(f) are cross-sectional views showing an embodiment of the present invention in the order of steps.
先ず、第１図（ａ）のように、シリコン基板１上に設け
たシリコン酸化膜等の絶縁膜２上にアルミニウム等の金
属膜を例えば１．０μｍ程度の厚さに被着し、これを所
定パターンに形成して回路配線を形成し、その一部をパ
ッド３として構成する。First, as shown in FIG. 1(a), a metal film such as aluminum is deposited to a thickness of about 1.0 μm on an insulating film 2 such as a silicon oxide film provided on a silicon substrate 1. A circuit wiring is formed by forming a predetermined pattern, and a part thereof is configured as a pad 3.
そして、この上にＣＶＤ法によりシリコン酸化膜等の絶
縁膜４を被覆形成しかつこれを選択エツチングして窓５
を開設し、前記パッド３の金属バンプ形成領域を開口す
る。Then, an insulating film 4 such as a silicon oxide film is formed on this by CVD method and selectively etched to form a window 5.
Then, the metal bump forming region of the pad 3 is opened.
次いで、同図（ｂ）のようにスパッタ法を用いて第１及
び第２の下地金属層６，７を順次全面に被着する。これ
らの下地金属層６．７にはチタン。Next, as shown in FIG. 6B, first and second base metal layers 6 and 7 are sequentially deposited over the entire surface using a sputtering method. These underlying metal layers 6.7 are made of titanium.
パラジウム、クロム、銅等の材料が使用されるが、ここ
では下側の第１の下地金属層６には表面に絶縁性の酸化
膜を形成し易いチタン、クロムを選択し、上側の第２の
下地金属層７にはめっき金属の接着性の良いパラジウム
、銅を選択している。Materials such as palladium, chromium, and copper are used. Here, titanium and chromium, which easily form an insulating oxide film on the surface, are selected for the lower first base metal layer 6, and the upper second For the base metal layer 7, palladium and copper, which have good adhesion to plating metal, are selected.
次に、同図（ｃ）のように前記第１及び第２の下地金属
層６．７上に感光性樹脂膜８を形成しかつこれをバター
ニングして、前記パッド３及び窓５を含む領域を開口す
る。そして、前記第１及び第２の下地金属層６．７を共
通電極とする電気めっき法により前記パッド３上に銅を
電着し、マツシュルーム型の金属バンプ９を形成する。Next, as shown in FIG. 3(c), a photosensitive resin film 8 is formed on the first and second base metal layers 6.7, and this is buttered to include the pad 3 and the window 5. Open the area. Copper is then electrodeposited on the pad 3 by electroplating using the first and second base metal layers 6.7 as common electrodes to form a mushroom-shaped metal bump 9.
このとき、金属バンプ９は第２の下地金属層７上に形成
されるために、その接着性は良好である。なお、金属バ
ンプ９の材質としては半田、ニッケル等を用いることも
できる。At this time, since the metal bumps 9 are formed on the second base metal layer 7, their adhesion is good. Note that solder, nickel, or the like can also be used as the material for the metal bumps 9.
その後、同図（ｄ）のように感光性樹脂膜８を除去し、
続いて金属バンプ９をマスクとして第２の下地金属層７
のみをエツチング除去し、第１の下地金属層６はそのま
ま残しておく。例えば、第２の下地金属層７が銅の場合
にはエツチング液に塩化第２銅を採用すれば、第１の下
地金属層６をエツチングすることはない。After that, the photosensitive resin film 8 is removed as shown in FIG.
Next, using the metal bumps 9 as a mask, a second base metal layer 7 is formed.
Only the first base metal layer 6 is removed by etching, and the first base metal layer 6 is left as it is. For example, when the second base metal layer 7 is made of copper, if cupric chloride is used as the etching solution, the first base metal layer 6 will not be etched.
その上で、この残された第１の下地金属層６の表面を酸
素プラズマ処理し、表面に薄い絶縁性の酸化膜６ａを成
長させる。なお、第１の下地金属膜６がチタンやクロム
の場合には大気中でも自然酸化膜が成長されるが、前記
酸素プラズマ処理により確実に酸化膜６ａを成長できる
。Then, the surface of the remaining first base metal layer 6 is treated with oxygen plasma to grow a thin insulating oxide film 6a on the surface. Note that when the first base metal film 6 is made of titanium or chromium, a natural oxide film is grown even in the atmosphere, but the oxygen plasma treatment allows the oxide film 6a to grow reliably.
その後、前工程での酸素プラズマ処理によって前記酸化
膜６ａと同時に金属バンプ９表面に成長された酸化薄膜
（図示せず）を通常のめっき前処理工程で除去し、その
上で同図（ｅ）のように、前記第１の下地金属層６を共
通電極として金属バンプ９の表面に無電解めっきを施し
、耐酸化性及び耐薬品性に優れた厚さ０．３μｍ程度の
金めつき層１０を形成する。このとき、第１の下地金属
層６の表面には酸化膜６ａが残存しているため、この表
面に金めつき層が形成されることはない。After that, the oxide thin film (not shown) that was grown on the surface of the metal bump 9 at the same time as the oxide film 6a by the oxygen plasma treatment in the previous step is removed in a normal plating pretreatment step, and then the same oxide film (e) is removed. As shown, electroless plating is applied to the surface of the metal bump 9 using the first base metal layer 6 as a common electrode to form a gold plating layer 10 having a thickness of about 0.3 μm and having excellent oxidation resistance and chemical resistance. form. At this time, since the oxide film 6a remains on the surface of the first base metal layer 6, no gold plating layer is formed on this surface.
しかる後、金めっきした金属バンプ９をマスクとして前
記第１の下地金属層６をエツチング除去し、同図（ｆ）
のように金属バンプを完成する。Thereafter, the first base metal layer 6 is removed by etching using the gold-plated metal bumps 9 as a mask, as shown in FIG.
Complete the metal bump as shown.
したがって、この製造方法では、金属バンプ９の表面の
金めつき層１０の形成に際しては、第１の下地金属層６
を共通電極とした無電解めっき法を用いているため、多
数個の金属バンプに対して同時にめっきを施す場合にも
、各金属バンプ９におけるシリコン基板１との間の抵抗
値が相違していても夫々等しい電流が流れ、各金属バン
プに等しい厚さの金めつき層１０を形成することができ
る。勿論、第１の下地金属層６は最終的に除去するため
、半導体装置を構成する上での障害になることはない。Therefore, in this manufacturing method, when forming the gold plating layer 10 on the surface of the metal bump 9, the first base metal layer 6
Since an electroless plating method is used with a common electrode, even when plating a large number of metal bumps at the same time, the resistance value between each metal bump 9 and the silicon substrate 1 is different. Since the same current flows through each bump, it is possible to form the gold plating layer 10 of the same thickness on each metal bump. Of course, since the first base metal layer 6 is ultimately removed, it does not become an obstacle in constructing a semiconductor device.
このため、各金属バンプ９におけるボンディング等にば
らつきが生じることはなく、夫々において信顧性の高い
機械的及ｄ電気的なボンディングを実現できる。また、
各金属バンプ９において高さの相違が生じることもなく
、実装時における管理を容易化できる。Therefore, there is no variation in the bonding between the metal bumps 9, and highly reliable mechanical and electrical bonding can be achieved. Also,
There is no difference in height between the metal bumps 9, and management at the time of mounting can be facilitated.
ここで、本発明における第１．第２の各下地金属層や金
属バンプの材質は、前記実施例に限られるものではなく
、種々の材質のものを適用できる。Here, the first aspect of the present invention. The materials of each of the second base metal layers and the metal bumps are not limited to those in the embodiments described above, and various materials may be used.
勿論、めっき材も金に限られるものではない。Of course, the plating material is not limited to gold.
以上説明したように本発明は、第１及び第２の下地金属
層を形成した上で、これらを共通電極として金属バンプ
を形成し、その後第２の下地金属層のみを除去し、残さ
れた第１の下地金属層の表面を酸化して絶縁膜を成長さ
せ、その上でこの第１の下地金属層を共通電極とした無
電解めっき法により金属バンプにめっき層を施し、その
後に第１の下地金属層を除去しているので、条件の相違
する多数個の金属バンプに対しても等しい厚さのめっき
層を形成することができ、各金属バンプにおけるボンデ
ィングの信顛性を向上して良好な半導体装置の実装を実
現できる。As explained above, the present invention forms a first and second base metal layer, forms a metal bump using these as a common electrode, and then removes only the second base metal layer, leaving the remaining metal bump. The surface of the first base metal layer is oxidized to grow an insulating film, and then a plating layer is applied to the metal bump by electroless plating using the first base metal layer as a common electrode. Since the underlying metal layer is removed, it is possible to form a plating layer of the same thickness even on a large number of metal bumps with different conditions, improving the reliability of bonding for each metal bump. Good mounting of semiconductor devices can be achieved.
第１図（ａ）〜（ｆ）は本発明の一実施例を工程順に示
す断面図、第２図＜ａ＞〜（ｄ）は従来方法を工程順に
示す断面図である。
１．１１・・・シリコン基板、２，１２・・・シリコン
酸化膜、３．１３・・・パッド、４，１４・・・シリコ
ン酸化膜、５．１５・・・窓、６・・・第１の下地金属
層、６ａ・・・絶縁性酸化膜、７・・・第２の下地金属
層、８゜１８・・・感光性樹脂膜、９，１９・・・金属
バンプ、１０．２０・・・金めつき層、１６．１７・・
・下地金属層。FIGS. 1(a) to 1(f) are sectional views showing an embodiment of the present invention in the order of steps, and FIGS. 2(a) to 2(d) are sectional views showing a conventional method in the order of steps. 1.11...Silicon substrate, 2,12...Silicon oxide film, 3.13...Pad, 4,14...Silicon oxide film, 5.15...Window, 6...No. 1 Base metal layer, 6a... Insulating oxide film, 7... Second base metal layer, 8°18... Photosensitive resin film, 9, 19... Metal bump, 10.20.・・Gold plated layer, 16.17・・
・Base metal layer.
Claims (1)
る半導体装置の製造方法において、前記半導体基板上の
前記金属バンプの配設位置を含む領域に第１及び第２の
下地金属層を形成する工程と、これら第１及び第２の下
地金属層上に金属バンプに相当する領域を開口したマス
クを形成する工程と、前記第１及び第２の下地金属層を
共通電極とした電気めっき法により金属バンプを形成す
る工程と、前記第２の下地金属層のみを除去する一方残
された第１の下地金属層の表面を酸化して絶縁膜を成長
させる工程と、この第１の下地金属層を共通電極とした
無電解めっき法により前記金属バンプ表面にめっき層を
形成する工程と、前記第１の下地金属層を除去する工程
とを備えることを特徴とする半導体装置の製造方法。(1) In a method of manufacturing a semiconductor device including a metal bump having a plating layer of gold or the like on the surface, first and second base metal layers are formed in a region including the placement position of the metal bump on the semiconductor substrate. a step of forming a mask having an opening in a region corresponding to a metal bump on the first and second base metal layers; and an electroplating method using the first and second base metal layers as a common electrode. forming a metal bump by removing only the second base metal layer and oxidizing the surface of the remaining first base metal layer to grow an insulating film; A method for manufacturing a semiconductor device, comprising the steps of: forming a plating layer on the surface of the metal bump by electroless plating using the layer as a common electrode; and removing the first base metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61028853A JPS62188343A (en) | 1986-02-14 | 1986-02-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61028853A JPS62188343A (en) | 1986-02-14 | 1986-02-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62188343A true JPS62188343A (en) | 1987-08-17 |
Family
ID=12259935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61028853A Pending JPS62188343A (en) | 1986-02-14 | 1986-02-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62188343A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1003209A1 (en) * | 1998-11-17 | 2000-05-24 | Shinko Electric Industries Co. Ltd. | Process for manufacturing semiconductor device |
| JP2006005321A (en) * | 2004-05-18 | 2006-01-05 | Sony Corp | Convex electrode and its manufacturing method |
-
1986
- 1986-02-14 JP JP61028853A patent/JPS62188343A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1003209A1 (en) * | 1998-11-17 | 2000-05-24 | Shinko Electric Industries Co. Ltd. | Process for manufacturing semiconductor device |
| JP2006005321A (en) * | 2004-05-18 | 2006-01-05 | Sony Corp | Convex electrode and its manufacturing method |
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