JPS5811113B2 - electronic circuit equipment - Google Patents

electronic circuit equipment

Info

Publication number
JPS5811113B2
JPS5811113B2 JP52114296A JP11429677A JPS5811113B2 JP S5811113 B2 JPS5811113 B2 JP S5811113B2 JP 52114296 A JP52114296 A JP 52114296A JP 11429677 A JP11429677 A JP 11429677A JP S5811113 B2 JPS5811113 B2 JP S5811113B2
Authority
JP
Japan
Prior art keywords
support
resin film
substrate
insulating resin
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52114296A
Other languages
Japanese (ja)
Other versions
JPS5448074A (en
Inventor
藤本博昭
野依正晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP52114296A priority Critical patent/JPS5811113B2/en
Priority to US05/882,152 priority patent/US4246595A/en
Priority to GB8586/78A priority patent/GB1588377A/en
Priority to CA298,234A priority patent/CA1108305A/en
Priority to DE2810054A priority patent/DE2810054C2/en
Publication of JPS5448074A publication Critical patent/JPS5448074A/en
Priority to US06/168,418 priority patent/US4356374A/en
Publication of JPS5811113B2 publication Critical patent/JPS5811113B2/en
Expired legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 本発明は、多数の電子部品を高密度こ実装した薄型電子
回路装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin electronic circuit device in which a large number of electronic components are mounted in high density.

従来から電子部品を高密度に実装しようとする技術とし
ていわゆるハイブリッドIC技術が用いられているが、
この技術は基板がセラミック材料でコストが高く、また
LSI等はワイヤボンディングによる接続が必要で、特
に複雑な回路では多層配線が必要であるが、この場合の
コストは非常に高いものとなっていた。
So-called hybrid IC technology has traditionally been used to package electronic components at high density.
This technology requires high costs because the substrate is made of ceramic material, and LSIs require connections using wire bonding, and especially complex circuits require multilayer wiring, but the costs in this case are extremely high. .

一方上記の作業性の悪いワイヤボンディングを用いない
方法として、基板をポリイミド等の樹脂フィルムとし、
ビームリードにLSIの電極を接合するミニモツド法も
実用化されている。
On the other hand, as a method that does not use wire bonding, which has poor workability, the substrate is made of a resin film such as polyimide,
The minimod method, which connects LSI electrodes to beam leads, has also been put into practical use.

しかしミニモツド法ではビームリードの形成された部分
に配線層を形成できないことから高密度化に限度がある
こと、強度の面からかなり厚いポリイミドフィルムが必
要で、コストが高いこと等の欠点があった。
However, the mini-Motsudo method has drawbacks such as the inability to form a wiring layer in the area where the beam leads are formed, which limits the ability to increase density, and the need for a fairly thick polyimide film for strength, resulting in high cost. .

本出願人は既に、非常に薄いフィルムを用いて多数の素
子を高密度に相互配線するために好適な方法を特願昭5
0−92773号をはじめ数件の明細書において提案し
た。
The applicant has already filed a patent application for a method suitable for interconnecting a large number of devices with high density using a very thin film.
It was proposed in several specifications including No. 0-92773.

例えば上記特願昭50−92773号明細書には絶縁樹
脂フィルムに必要な貫通孔を設け、素子を絶縁樹脂フィ
ルムの一生面側から、その電極と上記貫通孔が一致する
ように接着し、他の主面側に配線層を設けると同時に上
記貫通孔を用いて素子の電極と配線とを接続した装置が
記されている。
For example, in the above-mentioned Japanese Patent Application No. 50-92773, necessary through-holes are provided in an insulating resin film, and the element is adhered from the entire surface side of the insulating resin film so that the electrodes and the through-holes coincide with each other. A device is described in which a wiring layer is provided on the main surface side of the device, and at the same time, the electrodes of the device and the wiring are connected using the through holes.

この装置の特徴的な製造方法は特願昭51−30159
号明細書等に、さらに配線層を多層化した装置は特願昭
52−7478号明細書に述べである。
The characteristic manufacturing method of this device is disclosed in Japanese Patent Application No. 51-30159.
Furthermore, a device having multiple wiring layers is described in Japanese Patent Application No. 7478/1983.

ここで提案された装置ではいずれもフィルム基板が従来
の%〜也と非常に薄いため、他のパッケージに収める時
などの取扱いを考慮したものが特願昭52−25603
号明細書に記載した装置で、これはフィルム基板に補強
のための支持体例えば枠体等を設置したものである。
In all of the devices proposed here, the film substrate is extremely thin, 100% to 100% thinner than the conventional one, so a device that takes into consideration handling when fitting it into another package is proposed in Japanese Patent Application No. 52-25603.
This is the device described in the specification, in which a support such as a frame for reinforcement is provided on a film substrate.

本発明は上記のような研究成果を踏まえた上で、フィル
ム基板を補強する金属製の支持体の一部を配線として用
い、非常に薄いフィルム基板を使用しながら十分な強度
を有し、さらに容易こ多層化配線が形成されて電子部品
を高密度に実装した電子回路装置である。
Based on the above research results, the present invention uses a part of the metal support that reinforces the film substrate as wiring, and has sufficient strength while using a very thin film substrate. This is an electronic circuit device in which multilayer wiring is easily formed and electronic components are mounted at high density.

以下に本発明の一実施例を図面とともに説明する。An embodiment of the present invention will be described below with reference to the drawings.

第1図は完成した状態の電子回路装置、第2図には金属
等からなる支持体を示す。
FIG. 1 shows a completed electronic circuit device, and FIG. 2 shows a support made of metal or the like.

1はポリアミドフィルム等の絶縁樹脂フィルム、2は絶
縁樹脂フィルム1の一面に設けられた金属の支持体、3
゜4.5は電子部品で第1図では絶縁樹脂フィルム1の
裏面側から装着されており3はLSI等の半導体素子、
4はチップ抵抗、5はチップコンデンサである。
1 is an insulating resin film such as a polyamide film; 2 is a metal support provided on one side of the insulating resin film 1; 3 is a metal support provided on one side of the insulating resin film 1;
゜4.5 is an electronic component, which is mounted from the back side of the insulating resin film 1 in Fig. 1, and 3 is a semiconductor element such as an LSI;
4 is a chip resistor, and 5 is a chip capacitor.

6は絶縁樹脂フィルム1の表面側に形成された配線パタ
ーンで、絶縁樹脂フィルム1の要所に設けた貫通孔γこ
より配線パターン6と支持体2の一部、半導体素子3の
電極等が接続されている。
6 is a wiring pattern formed on the surface side of the insulating resin film 1, and the wiring pattern 6, a part of the support 2, the electrodes of the semiconductor element 3, etc. are connected through the through holes γ provided at key points of the insulating resin film 1. has been done.

なお第3図は第1図の要部を破断した拡大斜視図、第4
図は第3図中のV−V線による断面図である。
Note that Figure 3 is an enlarged perspective view of the main part of Figure 1, and Figure 4
The figure is a sectional view taken along line V-V in FIG. 3.

これらの図面を参照しながら本装置の製造の手順に沿っ
てさらに詳しく説明する。
The manufacturing procedure of this device will be explained in more detail with reference to these drawings.

絶縁樹脂フィルムは耐熱性かつ可撓性を有する材料がよ
く、従来の約1/10〜1/2の厚さにあたる10μ〜
50μのポリイミドフィルムが適当である。
The insulating resin film is preferably made of a material that is heat resistant and flexible, and has a thickness of 10 μm or more, which is about 1/10 to 1/2 the thickness of conventional films.
A 50μ polyimide film is suitable.

この絶縁樹脂フィルム1の一方の面にFBP樹脂やエポ
キシ樹脂等からなる接着層8を設け、ニッケルステンレ
スまたはコバール等で第2図のように形成した約150
μ厚の支持体2を約300℃で熱圧着により接着する。
An adhesive layer 8 made of FBP resin, epoxy resin, etc. is provided on one side of this insulating resin film 1, and approximately 1500 ml of adhesive layer 8 made of nickel stainless steel, Kovar, etc. is formed as shown in FIG.
A μ-thick support 2 is bonded by thermocompression at about 300°C.

このとき支持体2こ比べ絶縁樹脂フィルム1の膨張係数
が犬であるため、接着後に常温に戻った際絶縁樹脂フィ
ルムが収縮しいわゆる「たわみのない」表面が得られる
At this time, since the expansion coefficient of the insulating resin film 1 is lower than that of the support 2, the insulating resin film contracts when the temperature returns to room temperature after bonding, and a so-called "flexible" surface is obtained.

これは以後の製作にとって極めて重要である。This is extremely important for subsequent production.

次に要所を選択的にケミカルエツチング、プラズマエツ
チングして絶縁樹脂フィルム1および接着層8にテーパ
を有する貫通孔7を形成する。
Next, tapered through holes 7 are formed in the insulating resin film 1 and the adhesive layer 8 by selectively chemical etching and plasma etching at important points.

そして半導体素子3、チップ抵抗4等を接着層8側から
熱圧着する。
Then, the semiconductor element 3, chip resistor 4, etc. are bonded by thermocompression from the adhesive layer 8 side.

このとき基板である絶縁樹脂フィルム1は透明であるた
め、貫通孔7と半導体素子3の電極等の位置合せが非常
に容易で作業性も向上している。
At this time, since the insulating resin film 1 serving as the substrate is transparent, alignment of the through holes 7 and the electrodes, etc. of the semiconductor element 3 is very easy, and workability is improved.

なお支持体2の厚さは50μ〜250μ程度にすること
ができ厚さが大である方が強度的にもよいことはいうま
でもないが、上記実施例のように支持体2と半導体素子
3等の電子部品が同一の接着層8側にある場合は、支持
体2の厚さが電子部品の厚さ以下である方が作業上望ま
しい。
Note that the thickness of the support 2 can be approximately 50μ to 250μ, and it goes without saying that the greater the thickness, the better the strength. When electronic components such as No. 3 are placed on the same adhesive layer 8 side, it is desirable for the thickness of the support body 2 to be less than or equal to the thickness of the electronic components in terms of work.

さらに絶縁樹脂フィルム1の、支持体2等のない表面の
全面にわたってCr、Cuを連続蒸着し、場合によって
はメッキ処理を施してもよい。
Furthermore, Cr and Cu may be continuously vapor-deposited over the entire surface of the insulating resin film 1 without the support 2, etc., and may be subjected to plating treatment as the case may be.

この時上記で設けた貫通孔7を介して半導体素子3の電
極、チップ抵抗4の端子、一部の支持体2と蒸着層とが
接続される。
At this time, the electrodes of the semiconductor element 3, the terminals of the chip resistor 4, a part of the support 2, and the vapor deposition layer are connected through the through hole 7 provided above.

次にフォトエツチングにより配線パターン6を形成する
Next, a wiring pattern 6 is formed by photoetching.

ここでは貫通孔7を介して絶縁樹脂フィルム1の表裏を
接続するのに蒸着法を用いたが、半田や導電性ペースト
、無電界メッキ等でもよい。
Here, a vapor deposition method was used to connect the front and back sides of the insulating resin film 1 via the through holes 7, but solder, conductive paste, electroless plating, etc. may also be used.

上記で明らかなように配線パターン6となるべき蒸着層
の形成時に電極等はもちろん配線となる一部の支持体2
にも同時に接続され、容易に多層配線構造を得ることが
できる。
As is clear from the above, during the formation of the vapor deposited layer that will become the wiring pattern 6, not only electrodes etc. but also a part of the support 2 that will become the wiring.
It is also possible to easily obtain a multilayer wiring structure.

なお本実施例ではLSI等の半導体素子3の電極にバン
プ状電極等の特殊な形状を必要とせず、半導体素子3を
そのまま用いることができ、貫通孔7の大きさも50μ
平方で十分であり、従来に比べて電極とその接続に要す
る面積を著しく小さくすることが可能となった。
Note that in this embodiment, the electrodes of the semiconductor element 3 such as LSI do not require a special shape such as a bump-like electrode, and the semiconductor element 3 can be used as is, and the size of the through hole 7 is also 50 μm.
A square is sufficient, making it possible to significantly reduce the area required for the electrodes and their connections compared to the past.

上記で支持体2は、第2図のような最外周が枠となった
形状に形成しておけば厚さが少し薄いものでも強度を保
つことができ以上の製造工程での取扱いが容易となる。
If the support 2 above is formed into a shape with the outermost periphery as a frame as shown in Figure 2, it will maintain its strength even if it is a little thin and will be easier to handle in the above manufacturing process. Become.

そして工程の最後に上記枠の適当な所で切断すれば第1
図のような装置が得られる。
Then, at the end of the process, if you cut the frame at an appropriate place, the first
The device shown in the figure is obtained.

第1図からも明らかなように支持体2の一部は絶縁樹脂
フィルム1より外方へ突出し、また配線パターン6と接
続されていることから、この装置の引出端子として用い
ることができ非常に便利である。
As is clear from FIG. 1, a part of the support 2 protrudes outward from the insulating resin film 1 and is connected to the wiring pattern 6, so it can be used as a lead-out terminal of this device and is extremely useful. It's convenient.

なお電子部品側にンリコンゴム等の被覆膜を形成すれば
耐湿性も十分となる。
Note that moisture resistance will be sufficient if a coating film such as silicone rubber is formed on the electronic component side.

上記実施例では、支持体2が製造時の補強枠であること
はもちろん、その一部を配線として用いているため、特
に半導体素子3が多数ある場合に不可欠な多層配線が可
能で、容易に高密度の実装が実現できる。
In the above embodiment, the support body 2 not only serves as a reinforcing frame during manufacturing, but also uses a part of it as wiring, so multilayer wiring, which is essential especially when there are a large number of semiconductor elements 3, is possible and easy. High-density packaging can be achieved.

またその多層配線構造も、絶縁樹脂フィルム1の一方の
面に蒸着層を形成するとき、貫通孔7を介して互いの接
続が同時に行なわれるため、従来のように何度もマスク
を替えたり蒸着やエツチングを繰り返すこともなく、極
めて簡単にかつ正確こ形成できる。
Moreover, when forming the vapor deposition layer on one side of the insulating resin film 1, the multilayer wiring structure is also possible because mutual connections are made simultaneously through the through holes 7, which eliminates the need to change the mask many times and deposit the vapor deposition layer. It can be formed extremely easily and accurately without repeating etching or etching.

そして上記支持体2は枠から切り離した後も絶縁樹脂フ
ィルム1の一面に複雑な形状で接着されているため、第
1図の状態の装置でも十分な強度があり、従来のように
取扱い時に曲がったり破れたりすることもない。
Since the support 2 is adhered to one side of the insulating resin film 1 in a complicated shape even after being separated from the frame, it has sufficient strength even in the device shown in FIG. It won't crack or tear.

また支持体2の一部がこの装置の引出端子となっている
ことも大変実用的である。
It is also very practical that a part of the support body 2 serves as a lead-out terminal of this device.

なお、上記実施例では支持体2が絶縁樹脂フィルム1の
一方の面にのみ形成した場合を述べたが以下のようにし
てこの支持体2を両面に設けることも可能である。
In the above embodiment, the case where the support 2 was formed only on one side of the insulating resin film 1 was described, but it is also possible to provide the support 2 on both sides as follows.

絶縁樹脂フィルム1の両面にFEP樹脂等の接着層を設
けておく。
Adhesive layers such as FEP resin are provided on both sides of the insulating resin film 1.

裏面には第2図のようなニッケル等の支持体2を接着す
る。
A support 2 made of nickel or the like as shown in FIG. 2 is adhered to the back surface.

一方表面には全面に薄い銅箔を圧着し、エツチングによ
り上面支持体を形成する。
On the other hand, a thin copper foil is pressure-bonded to the entire surface, and an upper surface support is formed by etching.

次にプラズマエツチングを行なって上面支持体のない部
分の上面側の接着層を除去する。
Next, plasma etching is performed to remove the adhesive layer on the upper surface side of the portion where the upper surface support is not present.

貫通孔7の形成以後の工程は上記の実施例と同様である
The steps after forming the through hole 7 are the same as those in the above embodiment.

この後者の実施例では上記第1図の実施例よりさらに次
のような効果がある。
This latter embodiment has the following effects more than the embodiment shown in FIG.

後者では上面支持体を特こ長い距離の配線または装置の
外周に近い引出端子付近の配線に用いる。
In the latter case, the upper surface support is used for particularly long wiring or wiring near the lead terminal near the outer periphery of the device.

フィルム裏面の電値部品との接続は貫通孔と蒸着による
配線パターンであるから、この配線パターンを電子部品
付近の細かな相互配線に用いる。
Since the electrical components on the back side of the film are connected to each other through a through hole and a wiring pattern formed by vapor deposition, this wiring pattern is used for fine mutual wiring near the electronic components.

このことにより、第1図の実施例では蒸着およびフォト
エツチングをフィルム全面にわたって一度に行なうこと
から、時として配線パターンにショート等の不良が起こ
ることもあったが後者の実施例では部分ごとにフォトエ
ツチングしてゆくことも可能で、微細な配線パターンを
出すことができ、より高密度な装置となる。
As a result, in the embodiment shown in FIG. 1, vapor deposition and photoetching were performed over the entire surface of the film at once, which sometimes caused defects such as short circuits in the wiring pattern, but in the latter embodiment, the photoetching was carried out separately for each part. It is also possible to perform etching to produce fine wiring patterns, resulting in higher-density devices.

即ち、第1図の実施例では従来より高密度実装が量産的
に可能であるという特徴を有し、後者の実施例ではさら
に高密度に実装した装置が得られることに特徴がある。
That is, the embodiment shown in FIG. 1 has the feature that higher-density packaging is possible in mass production than in the past, and the latter embodiment has the feature that it is possible to obtain a device with even higher density packaging.

以上のように本発明は絶縁樹脂フィルム基板の少なくと
も一生面に選択的こ設置された前記基板を補強する金属
製の支持体と、前記支持体と重ならないように前記基板
の前記−主面に固定されたLSI等の電子部品と、前記
基板の他の主面に選択的に形成された配線層とからなり
、前記電子部品の端子と前記配線層とが前記基板こ設け
られた貫通孔を介して接続されるとともに、前記支持体
の一部に前記電子部品の端子または配線層が接続され前
記支持体が電気的配線の一部なものであり、非常に薄い
基板を用いてコストを引き下げ、一方十分な強度を保障
し、さらこ多層配線構造を容易に形成することができ、
電子部品を高密度に実装することが可能な電子回路装置
を提供するものである。
As described above, the present invention includes a metal support selectively installed on at least one surface of an insulating resin film substrate and reinforcing the substrate, and a metal support on the main surface of the substrate so as not to overlap with the support. It consists of a fixed electronic component such as an LSI and a wiring layer selectively formed on the other main surface of the substrate, and the terminal of the electronic component and the wiring layer are connected to the through hole provided in the substrate. At the same time, a terminal or a wiring layer of the electronic component is connected to a part of the support, and the support is part of the electrical wiring, and a very thin substrate is used to reduce costs. On the other hand, it guarantees sufficient strength and can easily form a flat multilayer wiring structure.
An object of the present invention is to provide an electronic circuit device in which electronic components can be mounted with high density.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の電子回路装置の一実施例を示す斜視図
、第2図は上記実施例に用いる支持体の斜視図、第3図
は要部破断拡大斜視図、第4図は第3図V−V線による
断面図である。 1・・・・・・絶縁樹脂フィルム、2・・・・・・支持
体、3・・・・・・半導体素子、6・・・・・・配線パ
ターン、7・・・・・・貫通孔。
FIG. 1 is a perspective view showing an embodiment of the electronic circuit device of the present invention, FIG. 2 is a perspective view of a support used in the above embodiment, FIG. 3 is an enlarged perspective view of a main part cut away, and FIG. FIG. 3 is a sectional view taken along line V-V in FIG. DESCRIPTION OF SYMBOLS 1...Insulating resin film, 2...Support, 3...Semiconductor element, 6...Wiring pattern, 7...Through hole .

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁樹脂フィルム基板の少なくとも一生面に選択的
に設置された前記基板を補強する金属製の支持体と、前
記支持体と重ならないように前記基板の前記−主面に固
定されたLSI等の電子部品と、前記基板の他の主面に
選択的に形成された配線層とからなり、前記電子部品の
端子と前記配線層とが前記基板に設けられた貫通孔を介
して接続されるとともに、前記支持体の一部に前記電子
部品の端子または配線層が接続され前記支持体が電気的
配線の一部をなすことを特徴とする電子回路装置。
1 A metal support for reinforcing the insulating resin film substrate selectively placed on at least one whole surface of the substrate, and a metal support such as an LSI fixed to the main surface of the substrate so as not to overlap with the support. It consists of an electronic component and a wiring layer selectively formed on the other main surface of the substrate, and the terminal of the electronic component and the wiring layer are connected through a through hole provided in the substrate. . An electronic circuit device, wherein a terminal or a wiring layer of the electronic component is connected to a part of the support, and the support forms a part of the electrical wiring.
JP52114296A 1977-03-08 1977-09-21 electronic circuit equipment Expired JPS5811113B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP52114296A JPS5811113B2 (en) 1977-09-21 1977-09-21 electronic circuit equipment
US05/882,152 US4246595A (en) 1977-03-08 1978-02-28 Electronics circuit device and method of making the same
GB8586/78A GB1588377A (en) 1977-03-08 1978-03-03 Electronic circuit devices and methods of making the same
CA298,234A CA1108305A (en) 1977-03-08 1978-03-06 Electronic circuit device and method of making the same
DE2810054A DE2810054C2 (en) 1977-03-08 1978-03-08 Electronic circuit arrangement and method for its manufacture
US06/168,418 US4356374A (en) 1977-03-08 1980-07-10 Electronics circuit device and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52114296A JPS5811113B2 (en) 1977-09-21 1977-09-21 electronic circuit equipment

Publications (2)

Publication Number Publication Date
JPS5448074A JPS5448074A (en) 1979-04-16
JPS5811113B2 true JPS5811113B2 (en) 1983-03-01

Family

ID=14634304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52114296A Expired JPS5811113B2 (en) 1977-03-08 1977-09-21 electronic circuit equipment

Country Status (1)

Country Link
JP (1) JPS5811113B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55145390A (en) * 1979-04-27 1980-11-12 Fujitsu Ltd Method of fabricating printed board unit
JPS55145393A (en) * 1979-04-30 1980-11-12 Matsushita Electric Works Ltd Method of mounting electronic component
JPS57145354A (en) * 1980-11-21 1982-09-08 Gao Ges Automation Org Carrier element for ic module
JPH0134360Y2 (en) * 1981-06-04 1989-10-19

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4975374A (en) * 1972-11-22 1974-07-20

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5159867U (en) * 1974-11-06 1976-05-11

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4975374A (en) * 1972-11-22 1974-07-20

Also Published As

Publication number Publication date
JPS5448074A (en) 1979-04-16

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