JPS6331138A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6331138A JPS6331138A JP61174769A JP17476986A JPS6331138A JP S6331138 A JPS6331138 A JP S6331138A JP 61174769 A JP61174769 A JP 61174769A JP 17476986 A JP17476986 A JP 17476986A JP S6331138 A JPS6331138 A JP S6331138A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- resist film
- pattern
- opening part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 12
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- 239000004020 conductor Substances 0.000 abstract description 4
- 238000009713 electroplating Methods 0.000 abstract description 4
- 238000007747 plating Methods 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 239000010949 copper Substances 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241000406668 Loxodonta cyclotis Species 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910020658 PbSn Inorganic materials 0.000 description 1
- 101150071746 Pbsn gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【発明の詳細な説明】
［概要］
金属バンプの形成方法であって、半導体基板上に電極膜
とバリヤメタル膜との積層膜をパターンニングして電極
部を形成する。その上に、絶縁膜を被着してパターンニ
ングし、更に、その上に、導電体膜を被着し、導電体膜
を導電層にして金属バンプを鍍金する。次いで、導電体
膜をエツチング除去する。DETAILED DESCRIPTION OF THE INVENTION [Summary] A method of forming a metal bump, in which an electrode portion is formed by patterning a laminated film of an electrode film and a barrier metal film on a semiconductor substrate. An insulating film is deposited thereon and patterned, a conductive film is further deposited thereon, and metal bumps are plated using the conductive film as a conductive layer. Next, the conductive film is removed by etching.
そうすると、金属バンプの接着力が強くなる。This will strengthen the adhesive strength of the metal bumps.
［産業上の利用分野］
本発明は金属バンプを有する半導体装置の製造方法に関
する。[Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device having metal bumps.
金属バンプを有する半導体装置は、ワイヤーをボンディ
ングする必要がないために、半導体容器の厚みを薄くで
き、且つ、半導体チップのポンディングパッド（電極領
域）も小さくできて、半導体容器を偏平な形状にしてＩ
Ｃカードに組み込んだり、また、半導体装置自体を高集
積化できる利点がある。更に、複数の半導体チップを回
路基板に配置して複合デバイスに形成できるから、電子
回路を高密度実装できる利点があり、このような金属バ
ンプを設けた半導体装置は、従前より良く知られている
構造であるが、最近、その高密度化の面から新たに見立
されている半導体装置の構造である。Semiconductor devices with metal bumps do not require wire bonding, so the thickness of the semiconductor container can be made thinner, and the bonding pad (electrode area) of the semiconductor chip can also be made smaller, allowing the semiconductor container to have a flat shape. I
It has the advantage that it can be incorporated into a C card, and that the semiconductor device itself can be highly integrated. Furthermore, since multiple semiconductor chips can be arranged on a circuit board to form a composite device, there is an advantage that electronic circuits can be mounted in high density, and semiconductor devices provided with such metal bumps have been well known for some time. This is a structure of semiconductor devices that has recently received new attention from the perspective of higher density.
しかし、金属バンプ自体は電極と十分な接着性をもって
いることが要望されている。However, the metal bump itself is required to have sufficient adhesion to the electrode.
［従来の技術］
従来、このような金属バンプの製造法として、第２図（
ａｌ〜（ｅ）に示すような形成方法が知られている。そ
の概要を説明すると、まず、同図（ａｌに示すように、
半導体基板１上にアルミニウム電極２を設け、そのアル
ミニウム電極２を含む基板全面に、化学気相成長（ＣＶ
Ｄ）法で燐シリケートガラス（Ｐ Ｓ Ｃ）膜３（絶縁
膜）を成長する。なお、このＰＳＧＳ２Ｏ２わりに、酸
化シリコン（Ｓｉ０２）膜を用いる場合もある。[Prior art] Conventionally, as a manufacturing method for such metal bumps, the method shown in Fig. 2 (
Forming methods shown in al to (e) are known. To explain the outline, first, as shown in the same figure (al),
An aluminum electrode 2 is provided on a semiconductor substrate 1, and the entire surface of the substrate including the aluminum electrode 2 is subjected to chemical vapor deposition (CVV).
A phosphorus silicate glass (PSC) film 3 (insulating film) is grown by method D). Note that a silicon oxide (Si02) film may be used instead of PSGS2O2.
次いで、第２図（ｂｌに示すように、ＰＳＧＳ２Ｏ２に
第１のレジスト膜を塗布し、露光・現像して電極上の所
定位置を開口した第１のレジスト膜パターン４を設け、
そのレジスト膜パターン４をマスクにしてＰＳＧＳ２Ｏ
２ツチングして、電極上に開口部５を形成する。Next, as shown in FIG. 2 (bl), a first resist film was applied to PSGS2O2, exposed and developed to form a first resist film pattern 4 with openings at predetermined positions on the electrodes,
Using the resist film pattern 4 as a mask, PSGS2O
Double punching is performed to form an opening 5 on the electrode.
次いで、レジスト膜パターン４を除去した後、第２図（
Ｃ）に示すように、開口部５を含むＰＳＧ膜３上に、チ
タン（Ｔｆ）と銅（Ｃｕ）とニアケル（Ｎｉ）の３層か
らなるバリヤメタル膜６ （膜厚１〜２μｍ程度）をス
パッタ法で被着する。次いで、同図（ｄｌに示すように
、その上に第２のレジスト膜を塗布し、露光・現像して
前記開口部５の位置に開口部よりやや広い窓部を有する
第２のレジスト膜パターン７を設け、そのレジスト膜パ
ターンをマスクにして、窓部に半田（ＰｂＳｎ）バンプ
８を鍍金（メッキ）法で被着する。その時、バリヤメタ
ル膜６は電気鍍金のための導電層として利用される。Next, after removing the resist film pattern 4, as shown in FIG.
As shown in C), a barrier metal film 6 (film thickness of about 1 to 2 μm) consisting of three layers of titanium (Tf), copper (Cu), and Niacel (Ni) is sputtered on the PSG film 3 including the opening 5. covered by law. Next, as shown in FIG. 7, and using the resist film pattern as a mask, solder (PbSn) bumps 8 are deposited on the windows by plating.At this time, the barrier metal film 6 is used as a conductive layer for electroplating. .
次いで、第２図（ｅ）に示すように、レジスト膜パター
ン７を除去し、更に、半田バンプ電極８をマスクにして
、露出したバリヤメタル膜６を除去する。このバリヤメ
タル膜６の除去には硝酸と燐酸の混液にッケル、銅の除
去）と燐酸（チタンの除去）のウェットエツチングをお
こなうが、それはドライエツチングではバンプ電極がエ
ツチングされるから、ウェットエツチングをおこなうも
のである。Next, as shown in FIG. 2(e), the resist film pattern 7 is removed, and the exposed barrier metal film 6 is further removed using the solder bump electrode 8 as a mask. To remove this barrier metal film 6, wet etching is performed using a mixed solution of nitric acid and phosphoric acid (removal of copper) and phosphoric acid (removal of titanium), but wet etching is performed because the bump electrodes are etched in dry etching. It is something.
次いで、図示していないが、熱処理して半田バンプを溶
融し、球状とする。尚、半田バンプの代わりに、金（Ａ
ｕ）バンプ８を形成する場合があるが、その形成方法も
ほぼ同様である。Next, although not shown, heat treatment is performed to melt the solder bumps and make them spherical. In addition, instead of solder bumps, gold (A
u) Although bumps 8 may be formed, the method for forming them is almost the same.
〔発明が解決しようとする問題点］
ところで、このような金属バンプの形成方法において、
バリヤメタル膜６は電極とバンプとが直接接触して反応
しないように介在させるものであるが、このバリヤメタ
ル膜６はまた、上記のように電気鍍金のための導電層と
しても利用されている。[Problems to be solved by the invention] By the way, in this method of forming metal bumps,
The barrier metal film 6 is interposed to prevent the electrodes and bumps from directly contacting and reacting, but this barrier metal film 6 is also used as a conductive layer for electroplating as described above.
そうして、最後に、第２図（Ｑ）で説明したように、半
田バンプ電極８をマスクとして、露出したバリヤメタル
膜６をエツチング除去する。Finally, as explained with reference to FIG. 2(Q), the exposed barrier metal film 6 is removed by etching using the solder bump electrode 8 as a mask.
しかし、そのエツチングの際に、半田バンプの下層まで
サイドエツチングが進んで（第２図（ｂｌ参、照）、半
田バンプと電極との接着力が弱くなり、半田バンプが外
れ易いと云う欠点がある。However, during etching, side etching progresses to the lower layer of the solder bump (see Figure 2 (bl)), which weakens the adhesion between the solder bump and the electrode, making it easy for the solder bump to come off. be.
本発明は、このような重要な欠点を解消させて、金属バ
ンプを設けた半導体装置の信鎖性を高める形成方法を提
案するものである。The present invention proposes a manufacturing method that eliminates these important drawbacks and improves the reliability of semiconductor devices provided with metal bumps.
［問題点を解決するための手段］
その目的は、半導体基板上に電極膜とバリヤメタル膜と
を積層被着して電極部を形成した後、全面に絶縁膜を被
着し、パターンニングして電極部を開口する工程、次い
で、全面に導電体膜を被着し、パターンニングして電極
部を開口する工程、次いで、該開口部に金属バンプを形
成した後、前記導電体膜をエツチング除去する工程が含
まれる製造方法によって達成される。[Means for solving the problem] The purpose is to form an electrode part by depositing an electrode film and a barrier metal film on the semiconductor substrate, and then depositing an insulating film on the entire surface and patterning it. A step of opening an electrode portion, then a step of depositing a conductive film on the entire surface and patterning it to open an electrode portion, then forming a metal bump in the opening, and then etching away the conductive film. This is accomplished by a manufacturing method that includes the steps of:
［作用コ
即ち、本発明は、予め、半導体基板上に電極膜とバリヤ
メタル膜との積層膜をパターンニングした電極部を形成
し、その上に絶縁膜を被着し、更に、バリヤメタル膜と
異質の導電体膜を被着し、その導電体膜を導電層にして
金属バンプを鍍金する。最後に、導電体膜をエツチング
除去する。[In other words, in the present invention, an electrode portion is formed by patterning a laminated film of an electrode film and a barrier metal film on a semiconductor substrate in advance, an insulating film is deposited on the electrode portion, and an insulating film that is different from the barrier metal film is formed on the semiconductor substrate. A conductive film is deposited, and a metal bump is plated using the conductive film as a conductive layer. Finally, the conductive film is removed by etching.
そうすれば、サイドエツチングがなくなって、金属バン
プの接着力が強くなり、半導体装置の信顧性が向上する
。This eliminates side etching, strengthens the adhesive strength of the metal bumps, and improves the reliability of the semiconductor device.
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図＋ａｌ〜（ｇ）は本発明にかかる形成方法の工程
順断面図を示している。まず、同図（ａ）に示すように
、半導体基板１１上にアルミニウム膜（膜厚１〜２μｍ
）と、チタン（Ｔｉ）と銅（Ｃｕ）とニッケル（Ｎｉ）
との３層からなるバリヤメタル膜（合計膜厚０．５〜１
μｍ程度）をスパッタ法で被着し、これをレジスト膜パ
ターン（図示せず）をマスクにしてエツチングして、バ
リヤメタル膜１２を被覆したアルミニウム電極１３とし
、更に、その上に、ＣＶＤ法でＰＳＧ膜１４（膜厚１μ
ｍ程度）を成長する。FIGS. 1+al to (g) show step-by-step cross-sectional views of the forming method according to the present invention. First, as shown in FIG.
), titanium (Ti), copper (Cu), and nickel (Ni)
Barrier metal film consisting of three layers (total film thickness 0.5 to 1
micrometer) by sputtering, etching this using a resist film pattern (not shown) as a mask to form the aluminum electrode 13 covered with the barrier metal film 12, and then layering PSG on top of it by CVD. Membrane 14 (film thickness 1μ
m).
次いで、第１図（ｂｌに示すように、ＰＳＧ膜１４の上
に第１のレジスト膜を塗布し、露光・現像して電極上の
所定位置を開口した第１のレジスト膜パターン４を設け
、そのレジスト膜パターン１５をマスクにしてＰＳＧ膜
１４をエツチングして、電極に開口部１６を形成する。Next, as shown in FIG. 1 (bl), a first resist film is coated on the PSG film 14, exposed and developed to form a first resist film pattern 4 with openings at predetermined positions on the electrodes, Using the resist film pattern 15 as a mask, the PSG film 14 is etched to form an opening 16 in the electrode.
次いで、レジスト膜パターン１５を除去した後、第１図
（Ｃ）に示すように、開口部１６を含むＰＳＧ膜１膜上
４上ルミニウム膜１７（膜厚３０００〜６０００人）を
スパッタ法で被着する。次いで、同図（ｄ）に示すよう
に、その上に第２のレジスト膜を塗布し、露光・現像し
て前記開口部１６の位置に開口部よりやや狭い窓部を有
する第２のレジスト膜パターン１８を設け、そのレジス
ト膜パターンをマスクにして、開口部１６のアルミニウ
ム膜１７をエツチング除去する。Next, after removing the resist film pattern 15, as shown in FIG. 1(C), a aluminum film 17 (thickness: 3000 to 6000) is coated on the PSG film 1 and 4 including the opening 16 by sputtering. wear it. Next, as shown in FIG. 2D, a second resist film is applied thereon, exposed and developed to form a second resist film having a window slightly narrower than the opening at the position of the opening 16. A pattern 18 is provided, and the aluminum film 17 in the opening 16 is removed by etching using the resist film pattern as a mask.
次いで、レジスト膜パターン１８を除去した後、第１図
（ｅ）に示すように、その上面に第３のレジスト膜を塗
布し、露光・現像して前記開口部１６の位置に開口部よ
りやや広い窓部を有する第３のレジスト膜パターン１９
を設け、そのレジスト膜パターンをマスクにして、窓部
に膜厚１００〜１５０μｍの厚い半田バンプ２０を鍍金
法で被着する。その時、アルミニウム膜１７を電気鍍金
のための導電層として用いる。Next, after removing the resist film pattern 18, as shown in FIG. Third resist film pattern 19 having a wide window
A thick solder bump 20 having a film thickness of 100 to 150 μm is deposited on the window portion by a plating method using the resist film pattern as a mask. At that time, the aluminum film 17 is used as a conductive layer for electroplating.
次いで、レジスト膜パターン１９を除去した後、第１図
（ｆ）に示すように、アルミニウム膜１７を熱硫酸液で
エツチング除去する。この時、バリヤメタル膜１２は熱
硫酸ではエツチングされない。次いで、同図（幻に示す
ように、３００℃程度に加熱して、球状の半田バンブ２
０を完成する。Next, after removing the resist film pattern 19, the aluminum film 17 is removed by etching with a hot sulfuric acid solution, as shown in FIG. 1(f). At this time, the barrier metal film 12 is not etched with hot sulfuric acid. Next, as shown in the figure (phantom), it was heated to about 300°C and a spherical solder bump 2
Complete 0.
このような形成方法を採れば、パイヤメタル膜のサイド
エツチングがなくなり、金属バンプの接着性が強化され
て、金属バンプの外れを防止することができ、半導体装
置が高信頬化される。If such a formation method is adopted, side etching of the piezo metal film is eliminated, the adhesion of the metal bumps is strengthened, the metal bumps can be prevented from coming off, and the reliability of the semiconductor device can be improved.
なお、この形成方法の要旨は、金バンプを形成する半導
体装置にも適用できることは云うまでもない。It goes without saying that the gist of this formation method can also be applied to semiconductor devices in which gold bumps are formed.
［発明の効果］
以上の実施例の説明から明らかなように、本発明によれ
ば金属バンプの接着力が強くなって、金属バンプを設け
る半導体装置の信頬性向上に大きな効果があるものであ
る。[Effects of the Invention] As is clear from the above description of the embodiments, the present invention increases the adhesive strength of the metal bumps and has a great effect on improving the reliability of semiconductor devices provided with the metal bumps. be.
第１図（ａ）〜（ｇ）は本発明にかかる形成方法の工程
順断面図、
第２図（ａ）〜（Ｑ）は従来の形成方法の工程順断面図
である。
図において、
１．１１は半導体基板、
２．１３はアルミニウム電極、
３．１４はＰＳＧ膜、
４、 ７．１５．１８．１９はレジスト膜パターン、５
．１６は開口部、
６．１２はバリヤメタル膜、
８．２０は半田バンブ、
１７はアルミニウム膜（導電体膜）
を示している。
４発時に１・ひＳＯハ′万迂シエ裸象灯面の第１図
半謬θ１４ ｔ＝ ｖ−Ｐｊ形賎方ｊりｌ若ｌゆ酎面図
第１図1(a) to (g) are step-by-step sectional views of a forming method according to the present invention, and FIGS. 2(a)-(Q) are step-by-step sectional views of a conventional forming method. In the figure, 1.11 is a semiconductor substrate, 2.13 is an aluminum electrode, 3.14 is a PSG film, 4, 7.15.18.19 is a resist film pattern, 5
．． 16 is an opening, 6.12 is a barrier metal film, 8.20 is a solder bump, and 17 is an aluminum film (conductor film). Figure 1 of the bare elephant light surface when 4 shots are fired.
Claims (1)
して電極部を形成した後、全面に絶縁膜を被着し、該絶
縁膜をパターンニングして電極部を開口する工程、 次いで、全面に導電体膜を被着し、該導電体膜をパター
ンニングして電極部を開口する工程、次いで、該開口部
に金属バンプを形成した後、前記導電体膜をエッチング
除去する工程が含まれてなることを特徴とする半導体装
置の製造方法。[Claims] After an electrode portion is formed by laminating and depositing an electrode film and a barrier metal film on a semiconductor substrate, an insulating film is deposited on the entire surface, and the insulating film is patterned to form an electrode portion. Next, a step of depositing a conductive film on the entire surface and patterning the conductive film to open an electrode portion; Next, after forming a metal bump in the opening, etching the conductive film. A method for manufacturing a semiconductor device, comprising a step of removing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61174769A JPS6331138A (en) | 1986-07-24 | 1986-07-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61174769A JPS6331138A (en) | 1986-07-24 | 1986-07-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6331138A true JPS6331138A (en) | 1988-02-09 |
Family
ID=15984346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61174769A Pending JPS6331138A (en) | 1986-07-24 | 1986-07-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6331138A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0661742A1 (en) * | 1993-12-29 | 1995-07-05 | Dow Corning Corporation | Integrated circuits with passivation and metallization for hermetic protection |
| WO1996021944A1 (en) * | 1995-01-13 | 1996-07-18 | National Semiconductor Corporation | Method and apparatus for capping metallization layer |
| EP0485151B1 (en) * | 1990-11-05 | 1999-05-12 | Fujitsu Limited | Surface acoustic wave device |
| US6111317A (en) * | 1996-01-18 | 2000-08-29 | Kabushiki Kaisha Toshiba | Flip-chip connection type semiconductor integrated circuit device |
| US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
| US8323765B2 (en) | 2007-05-03 | 2012-12-04 | Pilepro, Llc | Arrangement of multiple sheet pile components and welding profile therefor |
-
1986
- 1986-07-24 JP JP61174769A patent/JPS6331138A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0485151B1 (en) * | 1990-11-05 | 1999-05-12 | Fujitsu Limited | Surface acoustic wave device |
| EP0661742A1 (en) * | 1993-12-29 | 1995-07-05 | Dow Corning Corporation | Integrated circuits with passivation and metallization for hermetic protection |
| WO1996021944A1 (en) * | 1995-01-13 | 1996-07-18 | National Semiconductor Corporation | Method and apparatus for capping metallization layer |
| US6111317A (en) * | 1996-01-18 | 2000-08-29 | Kabushiki Kaisha Toshiba | Flip-chip connection type semiconductor integrated circuit device |
| US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
| US8323765B2 (en) | 2007-05-03 | 2012-12-04 | Pilepro, Llc | Arrangement of multiple sheet pile components and welding profile therefor |
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