JP2016086044A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2016086044A
JP2016086044A JP2014216781A JP2014216781A JP2016086044A JP 2016086044 A JP2016086044 A JP 2016086044A JP 2014216781 A JP2014216781 A JP 2014216781A JP 2014216781 A JP2014216781 A JP 2014216781A JP 2016086044 A JP2016086044 A JP 2016086044A
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electrode pad
plating layer
plating
semiconductor device
electrode
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JP6450560B2 (en
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石原　誠一
Seiichi Ishihara
誠一 石原
薫 宮越
Kaoru Miyakoshi
薫 宮越
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New Japan Radio Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a bump electrode with no large projections like lumps without an additional manufacturing step, and to provide a method of manufacturing the same.SOLUTION: A bump electrode formed on an electrode pad 3 with a probe trace 6 is configured to include a first plated layer 9a and a second plated layer 9b. The first plated layer is formed on the electrode pad with a probe trace at a substantially uniform film thickness by adjusting a current density when being plated. The second plated layer is formed thickly on the first plated layer in a condition where the current density is set to be high.SELECTED DRAWING: Figure 1

Description

この発明は半導体装置およびその製造方法に関し、特に製造工程中に電気特性検査工程を含み、その際形成されるプローブ痕を有する電極パッド上に電解メッキ法によりバンプ電極が形成される半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including an electrical characteristic inspection step in the manufacturing process, and bump electrodes formed on the electrode pads having probe marks formed by electrolytic plating. It relates to a manufacturing method.

半導体装置の製造工程では、半導体装置の電気特性検査がおこなわれる。この電気特性検査は、半導体装置の入出力端子となる電極パッドにテストプローブを接触させて行われる。ところで一般的に電極パッドは、金（Ａｕ）、アルミニウム（Ａｌ）、銅（Ｃｕ）等の金属で構成され、一方テストプローブは、先鋭な先端形状を有し、電極パッドを構成する金属より堅い材料で構成されている。そのため、テストプローブが接触した電極パッドの表面には、凹凸状に変形したプローブ痕が形成される。   In the manufacturing process of the semiconductor device, the electrical characteristics of the semiconductor device are inspected. This electrical characteristic inspection is performed by bringing a test probe into contact with an electrode pad serving as an input / output terminal of the semiconductor device. By the way, generally an electrode pad is comprised with metals, such as gold | metal | money (Au), aluminum (Al), copper (Cu), while a test probe has a sharp tip shape and is harder than the metal which comprises an electrode pad. Consists of materials. For this reason, probe marks deformed in an uneven shape are formed on the surface of the electrode pad in contact with the test probe.

図３は一般的な半導体装置の電極パッドにテストプローブを接触させた場合の断面図を示す。図３において、１は半導体装置が形成されている半導体基板、２は絶縁膜、３は半導体装置の入出力端子となる電極パッド、４は電極バッド３表面の一部を露出するように形成された表面保護膜、５は半導体装置の電気特性検査を行うために電極パッド３に接触させるテストプローブ、６はテストプローブ５の接触により電極パッド３表面の金属が凹凸状に変形したプローブ痕である。   FIG. 3 is a cross-sectional view when a test probe is brought into contact with an electrode pad of a general semiconductor device. In FIG. 3, 1 is a semiconductor substrate on which a semiconductor device is formed, 2 is an insulating film, 3 is an electrode pad serving as an input / output terminal of the semiconductor device, and 4 is formed so as to expose a part of the surface of the electrode pad 3. The surface protective film 5 is a test probe to be brought into contact with the electrode pad 3 in order to inspect the electrical characteristics of the semiconductor device, and 6 is a probe mark in which the metal on the surface of the electrode pad 3 is deformed into an uneven shape by the contact with the test probe 5. .

半導体装置の電気特性検査を行う際には、テストプローブ５と電極パッド３とを電気的に確実に接触させるため、テストプローブ５が電極パッド３に接触した状態より荷重を加えた状態となるため、電極パッド３上でテストプローブ５が矢印で示すように接触した状態で移動し、電極パッド３表面の金属が削られるように変形する。この変形は、図３に示すように、電極パッド３の表面の一部が削り取られて凹み、削り取られた金属がテストプローブ５先端部分に集まり突出することになる。この突出した金属の高さは、５μｍ以下程度である。   When electrical characteristics inspection of a semiconductor device is performed, the test probe 5 and the electrode pad 3 are brought into electrical contact with certainty, so that a load is applied from a state in which the test probe 5 is in contact with the electrode pad 3. The test probe 5 moves in contact with the electrode pad 3 as indicated by an arrow, and is deformed so that the metal on the surface of the electrode pad 3 is scraped. As shown in FIG. 3, this deformation causes a part of the surface of the electrode pad 3 to be scraped and recessed, and the scraped metal collects and protrudes at the tip of the test probe 5. The height of the protruding metal is about 5 μm or less.

一方半導体装置を実装基板に接続するため、電極パッド３上にバンプ電極を形成する場合がある。バンプ電極を備える半導体装置では、バンプ電極にテストプローブを接触させて電気特性検査が行われてきた。   On the other hand, bump electrodes may be formed on the electrode pads 3 in order to connect the semiconductor device to the mounting substrate. In a semiconductor device including a bump electrode, an electrical characteristic inspection has been performed by bringing a test probe into contact with the bump electrode.

しかし近年、微細化が進み、バンプ電極の径が小さくなった半導体装置等では、バンプ電極にテストプローブ５を接触させて電気特性検査を行うことができず、バンプ電極形成前に電極パッド３にテストプローブ５を接触させて電気特性検査を行い、その後バンプ電極を形成するようになってきている。これは、図３に示すようなプローブ痕６が形成された電極パッド３上にバンプ電極を形成することになる。   However, in recent years, in a semiconductor device or the like in which the size of the bump electrode has been reduced with the progress of miniaturization, the test probe 5 cannot be brought into contact with the bump electrode to perform the electrical characteristic inspection. The test probe 5 is brought into contact to perform an electrical property test, and then a bump electrode is formed. This means that a bump electrode is formed on the electrode pad 3 on which the probe mark 6 as shown in FIG. 3 is formed.

一方、バンプ電極を形成する簡便な方法の一つに電解メッキ法がある。ところで、プローブ痕６のある電極パッド３上に電解メッキ法によりバンプ電極を形成する場合、種々な問題が発生することが知られている。   On the other hand, there is an electrolytic plating method as one simple method for forming bump electrodes. By the way, it is known that various problems occur when bump electrodes are formed on the electrode pads 3 having the probe marks 6 by the electrolytic plating method.

例えば、図４に電解メッキ法によりバンプ電極を形成する製造工程を示す。まず、電気特性検査が終了した半導体装置を用意する。この半導体装置は、図３で説明したように、電極パッド３表面にはプローブ痕６が形成されている。全面に電解メッキのための析出電極となる金属膜７を形成し、バンプ電極形成予定領域を開口するようにフォトレジスト８をパターニングする。その後、電解メッキを開始する。ここで厚いバンプ電極を形成する通常の条件でメッキを行うと、図４（ａ）に示すように、メッキ工程の初期段階でプローブ痕６の突出した金属先端付近に厚いメッキ層９が析出する。   For example, FIG. 4 shows a manufacturing process for forming bump electrodes by electrolytic plating. First, a semiconductor device that has been subjected to electrical characteristic inspection is prepared. In this semiconductor device, probe marks 6 are formed on the surface of the electrode pad 3 as described with reference to FIG. A metal film 7 to be a deposition electrode for electrolytic plating is formed on the entire surface, and a photoresist 8 is patterned so as to open a bump electrode formation scheduled region. Thereafter, electrolytic plating is started. Here, when plating is performed under normal conditions for forming a thick bump electrode, as shown in FIG. 4A, a thick plating layer 9 is deposited near the protruding metal tip of the probe mark 6 in the initial stage of the plating process. .

このような状態で引き続いてメッキを続けて厚いメッキ層を形成すると、図４（ｂ）に示すようにコブのような大きな突起のあるバンプ電極１０となってしまう。またメッキ工程の初期段階の厚いメッキ層９は、プローブ痕６の突出した金属先端に電流が集中した結果生じるため、金属先端の形状によりこの部分への電流集中の度合いが変わると、形成される厚いメッキ層９の高さがばらついてしまう。その結果、最終的に出来上がるバンプ電極の高さがばらつくという問題があった。例えば、バンプ電極１０の高さ（電極パッド３上のメッキ層の厚さ）が３０μｍ弱まで電解メッキを行うと、メッキ工程に入る前の電極パッド３のプローブ痕６の金属の突出高さが、５μｍ以下程度であっても、最終的にバンプ電極上に１０〜２０μｍの高さのコブのような大きな突起が形成されてしまう。このような問題を解決するため、電極パッドの表面に予め溝を形成する加工を施すことで、電極パッドに大きな凹凸を形成しない技術が提案されている（例えば特許文献１、特許文献２）。   If a thick plating layer is formed by continuing plating in such a state, the bump electrode 10 having a large protrusion such as a bump is formed as shown in FIG. In addition, since the thick plating layer 9 in the initial stage of the plating process is generated as a result of current concentration on the protruding metal tip of the probe mark 6, the thick plating layer 9 is formed when the degree of current concentration on this portion changes depending on the shape of the metal tip. The height of the thick plating layer 9 varies. As a result, there has been a problem that the height of the bump electrode finally produced varies. For example, when the electrolytic plating is performed until the height of the bump electrode 10 (thickness of the plating layer on the electrode pad 3) is less than 30 μm, the metal protrusion height of the probe mark 6 of the electrode pad 3 before entering the plating process is increased. Even if it is about 5 μm or less, a large protrusion like a bump having a height of 10 to 20 μm is finally formed on the bump electrode. In order to solve such a problem, a technique has been proposed in which a large unevenness is not formed on the electrode pad by performing a process for forming a groove in advance on the surface of the electrode pad (for example, Patent Document 1 and Patent Document 2).

特開２００７−２４３０１３号公報JP 2007-243013 A 特開２０１０−２２１６５６号公報JP 2010-221656 A

しかしながら従来提案されている方法は、電極パッドに溝を形成するための製造工程が増加し、好ましくない。本発明は、このような問題点を解消し、追加の製造工程なしで、コブのような大きな突起のないバンプ電極を備えた半導体装置およびその製造方法を提供することを目的とする。   However, the conventionally proposed method is not preferable because a manufacturing process for forming a groove in the electrode pad increases. An object of the present invention is to solve such problems, and to provide a semiconductor device including a bump electrode without a large protrusion such as a bump and a manufacturing method thereof without an additional manufacturing process.

上記目的を達成するために、本願請求項１に係る発明は、半導体装置の入出力端子となる電極パッドと、該電極パッド上にバンプ電極を備えた半導体装置において、前記電極パッドの一部は、該電極パッドを構成する金属の一部が凹凸状に変形したプローブ痕を有し、該プローブ痕を有する電極パッド上に、第１の電流密度で形成された前記電極パッド上および前記プローブ痕上を被覆する均一な膜厚の第１のメッキ層と、該第１のメッキ層上に、前記第１の電流密度より高い第２の電流密度で形成された前記第１のメッキ層より厚い第２のメッキ層とを備え、前記バンプ電極は、少なくとも前記第１のメッキ層と前記第２のメッキ層を含むことを特徴とする。   In order to achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor device including an electrode pad serving as an input / output terminal of a semiconductor device and a bump electrode on the electrode pad. A part of the metal constituting the electrode pad has a probe mark deformed in an uneven shape, and the electrode pad formed at a first current density on the electrode pad having the probe mark and the probe mark A first plating layer having a uniform thickness covering the top, and thicker than the first plating layer formed on the first plating layer at a second current density higher than the first current density And the bump electrode includes at least the first plating layer and the second plating layer.

本願請求項２に係る発明は、半導体装置の入出力端子となる電極パッドと、該電極パッド上にバンプ電極を備えた半導体装置の製造方法において、前記電極パッドにテストプローブを接触させ、半導体装置の電気特性検査を行うテスト工程と、前記テストプローブの接触により前記電極パッドを構成する金属の一部が凹凸状に変形したプローブ痕が形成された電極パッド上に電解メッキを施すバンプ電極形成工程とを含み、該バンプ電極形成工程は、前記電極パッド上および前記プローブ痕上に均一な膜厚のメッキ層を析出させる第１の電流密度で電解メッキを行い、第１のメッキ層を形成する第１のメッキ工程と、前記第１のメッキ層上に、前記第１の電流密度より高い第２の電流密度で電解メッキを行い、前記第１のメッキ層より厚い第２のメッキ層を形成する第２のメッキ工程を含むことを特徴とする。   According to a second aspect of the present invention, in a method of manufacturing a semiconductor device having an electrode pad serving as an input / output terminal of a semiconductor device and a bump electrode on the electrode pad, a test probe is brought into contact with the electrode pad. A test process for inspecting electrical characteristics of the electrode, and a bump electrode formation process in which electrolytic plating is performed on the electrode pad on which a probe mark is formed in which a part of the metal constituting the electrode pad is deformed in an uneven shape by contact with the test probe And forming the first plating layer by performing electrolytic plating at a first current density that deposits a plating layer having a uniform film thickness on the electrode pad and the probe trace. A first plating step, and electrolytic plating is performed on the first plating layer at a second current density higher than the first current density, and the first plating layer is thicker than the first plating layer. Characterized in that it comprises a second plating step for forming a plating layer.

本発明の半導体装置は、電極パッド３上にプローブ痕６のような金属突起が存在しても、電解メッキ工程の初期段階で積層形成される第１のメッキ層は、その形状に沿ってほぼ均一に析出するため、異常メッキを防止することができ、その後に厚いメッキ層を施して形成するバンプ電極１０の表面に残る凹凸は、プローブ痕６の金属突起の高さ、即ち５μｍ弱程度のばらつきに留まり、大幅なばらつきの低減を計ることができる。   In the semiconductor device of the present invention, even if a metal protrusion such as the probe mark 6 is present on the electrode pad 3, the first plating layer formed and laminated at the initial stage of the electrolytic plating process is substantially along the shape. Since it deposits uniformly, abnormal plating can be prevented, and the unevenness remaining on the surface of the bump electrode 10 formed by applying a thick plating layer thereafter is the height of the metal protrusion of the probe trace 6, that is, about 5 μm or less. It is possible to achieve a significant reduction in the variation.

また本発明の半導体装置の製造方法は、メッキ工程の初期段階の電流密度を調整し、プローブ痕６の金属突起上にほぼ均一な厚さのメッキ層が析出する条件に設定するのみでよく、電極パッド３に特別な加工を施す必要がなく、非常に簡便な方法である。   Further, the semiconductor device manufacturing method of the present invention only needs to adjust the current density in the initial stage of the plating process and set the conditions so that a plating layer having a substantially uniform thickness is deposited on the metal protrusions of the probe trace 6. The electrode pad 3 does not need to be specially processed and is a very simple method.

本発明の半導体装置の説明図である。It is explanatory drawing of the semiconductor device of this invention. 本発明の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor device of this invention. 一般的な半導体装置の電極パッドにテストプローブを接触させた場合の断面図である。It is sectional drawing at the time of making a test probe contact the electrode pad of a common semiconductor device. 図３に示す電極パッドに電解メッキ法によりバンプ電極を形成する製造方法を説明する図である。It is a figure explaining the manufacturing method which forms a bump electrode on the electrode pad shown in FIG. 3 by the electrolytic plating method.

本発明の半導体装置は、図１に示すように、プローブ痕６の残る電極パッド３上に形成されるバンプ電極１０が、第１のメッキ層９ａと第２のメッキ層９ｂを含む構成となっている。この第１のメッキ層９ａは、メッキを行う際の電流密度を調整することで、プローブ痕６の残る電極パッド３上にほぼ均一な膜厚で形成され、第２のメッキ層９ｂは、第１のメッキ層９ａ上に電流密度を高くした条件で厚く形成されている。以下、本発明を実施例について、製造工程に従い詳細に説明する。   In the semiconductor device of the present invention, as shown in FIG. 1, the bump electrode 10 formed on the electrode pad 3 on which the probe trace 6 remains includes a first plating layer 9a and a second plating layer 9b. ing. The first plated layer 9a is formed with a substantially uniform film thickness on the electrode pad 3 where the probe marks 6 remain by adjusting the current density during plating, and the second plated layer 9b It is formed thick on one plating layer 9a under the condition that the current density is increased. Hereinafter, the present invention will be described in detail according to the production process with respect to examples.

本発明の半導体装置は、図３で説明したように、電極パッド３表面の金属の一部が削り取られて凹み、削り取られた金属がテストプローブ先端部分に集まり突出するプローブ痕６が形成されている。突出した金属の高さは、５μｍ以下程度である。電極パッド３は、金（Ａｕ）、アルミニウム（Ａｌ）、アルミニウム銅（ＡｌＣｕ）、銅（Ｃｕ）等半導体装置の製造工程で一般的に用いられる金属で構成されている。   In the semiconductor device of the present invention, as described with reference to FIG. 3, a part of the metal on the surface of the electrode pad 3 is scraped and recessed, and a probe mark 6 is formed in which the scraped metal collects and protrudes at the tip portion of the test probe. Yes. The height of the protruding metal is about 5 μm or less. The electrode pad 3 is made of a metal generally used in the manufacturing process of a semiconductor device, such as gold (Au), aluminum (Al), aluminum copper (AlCu), copper (Cu).

従来例同様、全面に電解メッキのための析出電極となる金属膜７を形成し、バンプ電極形成予定領域を開口するようにフォトレジスト８をパターニングする。バンプ電極は、金（Ａｕ）、銅（Ｃｕ）、ニッケル（Ｎｉ）、スズ（Ｓｎ）、銀スズ（ＳｎＡｇ）、金スズ（ＳｎＡｕ）などから適宜選択される。   As in the conventional example, a metal film 7 serving as a deposition electrode for electrolytic plating is formed on the entire surface, and a photoresist 8 is patterned so as to open a bump electrode formation scheduled region. The bump electrode is appropriately selected from gold (Au), copper (Cu), nickel (Ni), tin (Sn), silver tin (SnAg), gold tin (SnAu), and the like.

本発明のバンプ電極形成のためのメッキ工程は、少なくとも第１のメッキ工程と第２のメッキ工程を含んでいる。まず第１のメッキ工程は、通常の電解メッキ工程の条件と比べて電流密度の低い条件とする。具体的には、０．１３５Ａ／ｄｍ2とする。１０分程度の電解メッキを行うと、厚さ１〜２μｍ程度の均一な厚さの第１のメッキ層９ａを形成することができる（図２ａ）。 The plating process for forming the bump electrode of the present invention includes at least a first plating process and a second plating process. First, the first plating process is performed under a condition where the current density is lower than that in the normal electrolytic plating process. Specifically, it is set to 0.135 A / dm 2 . When electrolytic plating is performed for about 10 minutes, the first plating layer 9a having a uniform thickness of about 1 to 2 μm can be formed (FIG. 2a).

図２（ａ）に示すようにこの第１のメッキ工程では、電流密度を低くして電解メッキを行うことで、プローブ痕６の突出した金属先端に電流が集中することがなく、電極パッド３表面全体にほぼ均一なメッキ層（第１のメッキ層９）が形成される。ここで第１のメッキ工程は、第１メッキ層９ａにより被覆されたプローブ痕６の突出した金属先端が、その太さを増し、第１のメッキ工程のメッキ条件より電流密度を増して行う後述する第２のメッキ工程でもプローブ痕の先端部に電流密度の集中が生じない程度の厚さの第１のめっき層９ａが形成されるまで行うことになる。従って、第２のメッキ工程のメッキ条件に応じ、あるいはプローブ痕６の形状に応じ、第１のメッキ層の厚さやメッキ条件（電流密度）は適宜設定されることになる。   As shown in FIG. 2A, in this first plating step, the current density is lowered and electrolytic plating is performed, so that no current concentrates on the protruding metal tip of the probe mark 6 and the electrode pad 3 A substantially uniform plating layer (first plating layer 9) is formed on the entire surface. Here, the first plating step is performed by increasing the thickness of the protruding metal tip of the probe mark 6 covered with the first plating layer 9a and increasing the current density from the plating conditions of the first plating step. The second plating step is performed until the first plating layer 9a having a thickness that does not cause concentration of current density at the tip of the probe trace is formed. Therefore, the thickness of the first plating layer and the plating conditions (current density) are appropriately set according to the plating conditions of the second plating process or according to the shape of the probe mark 6.

次に、第１のメッキ層９ａ上に第２のメッキ層９ｂを析出させる。この第２のメッキ工程は、バンプ電極１０のように厚いメッキ層を形成するため、先に説明したメッキ条件より成長速度の早い条件を選択するのが好ましい。具体的には、０．２７Ａ／ｄｍ2で３時間程度の電解メッキを行うと、厚さ２７μｍ程度の厚さの第２のメッキ層９ｂを形成することができる（図２ｂ）。 Next, a second plating layer 9b is deposited on the first plating layer 9a. In this second plating step, since a thick plating layer is formed like the bump electrode 10, it is preferable to select a condition with a faster growth rate than the plating conditions described above. Specifically, when electrolytic plating is performed at 0.27 A / dm 2 for about 3 hours, a second plating layer 9 b having a thickness of about 27 μm can be formed (FIG. 2 b).

この第２のメッキ工程とのバンプ電極１０の表面は、プローブ痕６の突出した金属の高さ（５μｍ以下程度）より低い突起はあるものの、従来例で説明したようなコブにような大きな突起が生じることはない。   The surface of the bump electrode 10 in the second plating step has large protrusions like a bump as described in the conventional example, although there are protrusions lower than the metal height (about 5 μm or less) from which the probe marks 6 protrude. Will not occur.

その後、フォトレジスト８を除去するとともに露出する析出電極として使用した金属膜７を除去することで、バンプ電極１０を備えた半導体装置を完成することができる（図１）。   Then, the semiconductor device provided with the bump electrode 10 can be completed by removing the photoresist 8 and removing the metal film 7 used as the exposed deposition electrode (FIG. 1).

このように本発明は、バンプ電極を形成する際のメッキ条件を変更することのみで、プローブ痕のある電極パッド上にバンプ電極を形成することができ、非常に簡便な方法である。なお本発明では、第２のメッキ工程は電流密度の異なる条件のメッキ工程を繰り返したり、複数の金属膜の積層構造としても良い。   As described above, the present invention is a very simple method in which a bump electrode can be formed on an electrode pad having a probe mark only by changing the plating conditions for forming the bump electrode. In the present invention, the second plating step may be repeated under different conditions of current density, or a laminated structure of a plurality of metal films.

１：半導体基板、２：絶縁膜、３：電極パッド、４：表面保護膜、５：テストプローブ、６プローブ痕、７：金属膜、８：フォトレジスト、９：メッキ層、９ａ：第１のメッキ層、第２のメッキ層、１０：バンプ電極 1: Semiconductor substrate, 2: Insulating film, 3: Electrode pad, 4: Surface protective film, 5: Test probe, 6 probe mark, 7: Metal film, 8: Photoresist, 9: Plating layer, 9a: First Plating layer, second plating layer, 10: bump electrode

Claims (2)

半導体装置の入出力端子となる電極パッドと、該電極パッド上にバンプ電極を備えた半導体装置において、
前記電極パッドの一部は、該電極パッドを構成する金属の一部が凹凸状に変形したプローブ痕を有し、
該プローブ痕を有する電極パッド上に、第１の電流密度で形成された前記電極パッド上および前記プローブ痕上を被覆する均一な膜厚の第１のメッキ層と、
該第１のメッキ層上に、前記第１の電流密度より高い第２の電流密度で形成された前記第１のメッキ層より厚い第２のメッキ層とを備え、
前記バンプ電極は、少なくとも前記第１のメッキ層と前記第２のメッキ層を含むことを特徴とする半導体装置。 In an electrode pad serving as an input / output terminal of a semiconductor device, and a semiconductor device provided with a bump electrode on the electrode pad,
A part of the electrode pad has a probe mark in which a part of the metal constituting the electrode pad is deformed into an uneven shape,
A first plating layer having a uniform thickness covering the electrode pad formed at a first current density and the probe mark on the electrode pad having the probe mark;
A second plating layer thicker than the first plating layer formed at a second current density higher than the first current density on the first plating layer;
The bump electrode includes at least the first plating layer and the second plating layer. 半導体装置の入出力端子となる電極パッドと、該電極パッド上にバンプ電極を備えた半導体装置の製造方法において、
前記電極パッドにテストプローブを接触させ、半導体装置の電気特性検査を行うテスト工程と、
前記テストプローブの接触により前記電極パッドを構成する金属の一部が凹凸状に変形したプローブ痕が形成された電極パッド上に電解メッキを施すバンプ電極形成工程とを含み、
該バンプ電極形成工程は、前記電極パッド上および前記プローブ痕上に均一な膜厚のメッキ層を析出させる第１の電流密度で電解メッキを行い、第１のメッキ層を形成する第１のメッキ工程と、前記第１のメッキ層上に、前記第１の電流密度より高い第２の電流密度で電解メッキを行い、前記第１のメッキ層より厚い第２のメッキ層を形成する第２のメッキ工程を含むことを特徴とする半導体装置の製造方法。 In an electrode pad serving as an input / output terminal of a semiconductor device, and a method of manufacturing a semiconductor device provided with a bump electrode on the electrode pad,
A test step of bringing a test probe into contact with the electrode pad and inspecting electrical characteristics of the semiconductor device;
A bump electrode forming step of performing electrolytic plating on an electrode pad on which a probe mark in which a part of a metal constituting the electrode pad is deformed into an uneven shape by contact with the test probe,
The bump electrode forming step includes a first plating for forming a first plating layer by performing electrolytic plating at a first current density for depositing a plating layer having a uniform film thickness on the electrode pad and the probe trace. And a second step of performing electrolytic plating on the first plating layer at a second current density higher than the first current density to form a second plating layer thicker than the first plating layer. A method for manufacturing a semiconductor device, comprising a plating step.
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