JP2007243013A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress projections on an electrode pad since large projections are formed also on a bump surface after forming bumps due to a projecting shape (probe trace) on the electrode pad for decreasing packaging reliability, when forming the bumps on the electrode pad after inspecting the electrical characteristics of a semiconductor integrated circuit. <P>SOLUTION: A plurality of grooves are formed in an island shape on the surface layer of the electrode pad, thus enabling needle dust generated by the contact of the electrode pad and a probe to become small broken pieces and preventing large projections from being generated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure of an electrode pad in a semiconductor integrated circuit device, particularly when a bump is formed on the electrode pad after electrical characteristic inspection.

  FIG. 4 is a cross-sectional view schematically showing a schematic configuration of a bump of a conventional semiconductor integrated circuit device, and FIG. 5 is a cross-sectional view schematically showing a manufacturing process of a bump formed on an electrode pad.

  In FIG. 4, 101 is a semiconductor substrate on which a semiconductor integrated circuit is formed, 102 is an electrode pad for connecting to an external input / output terminal formed on a semiconductor element (not shown) of the semiconductor substrate 101, and 103 is an electrode pad. A protective film including a part of 102 and formed on the semiconductor substrate 101, 104 is a bump base metal film as a barrier metal, and 105 is a bump formed on the bump base metal film 104. However, FIG. 4 is a schematic diagram in the case where bump formation is performed without performing electrical property inspection, and a probe mark (described later) is not formed on the electrode pad 102.

  Next, the manufacturing process of the bump formed on the electrode pad will be described with reference to FIG. In FIG. 5A, a protective film 103 is coated on the semiconductor substrate 101, and the protective film 103 is patterned by a photolithography technique in order to electrically connect the electrode pad 102 and the external input / output terminal. A surhole 106 is formed on the electrode pad 102.

  Next, in FIG. 5B, a bump base metal film 104 as a barrier metal is formed on the entire surface with a predetermined thickness. Usually, the bump base metal film 104 is made of a metal having high adhesion to the electrode pad 102 and the bump 105 formed in a later process. Further, the bump base metal film 104 may be formed in a multilayer structure, and finally becomes a conductive layer of the bump 105 in a later process.

  Next, in FIG. 5C, a photoresist 107 is applied on the bump base metal film 104 by a spin coat method or the like, and then a resist pattern is formed by a photolithography technique. At this time, the photoresist 107 is applied thicker than the thickness of the bump 105 formed at an arbitrary height.

  Next, in FIG. 5D, a predetermined current is passed through the plating conductive layer (bump base metal film) 104 by electroplating, and bumps 105 are selectively formed in regions not covered with the photoresist 107. To do.

  Next, in FIG. 5E, the photoresist 107 is removed by immersing in a photoresist stripping solution for a predetermined time, and the bump base metal film 104 is exposed. Next, the bump base metal film 104 is etched using the bump 105 as a mask to form the bump base metal film 104 in a desired shape. The bump structure shown in FIG. 4 is manufactured by such a manufacturing process.

  Usually, as a pre-process of the step of forming the bump base metal film 104 (FIG. 5B), a test (electric characteristic test) of the semiconductor element characteristics of the semiconductor integrated circuit is performed with the electrode pad 102.

  With reference to FIG. 3, a manufacturing process of the bump when the electrical property inspection is performed will be described. In FIG. 3A, since the electrode pad 102 is generally formed of Al or an alloy containing Al, the surface is covered with a natural oxide film. Therefore, when performing an electrical characteristic test, in order to ensure electrical contact between the test probe 201 and the electrode pad 102, the natural oxide film formed on the surface of the electrode pad 102 is removed and the test probe 201 and The electrode pad 102 needs to be contacted.

  Therefore, as shown in FIG. 3B, the natural oxide film is generally removed by rubbing the test probe 201 on the electrode pad 102 to bring the test probe 201 and the electrode pad 102 into contact with each other. Probe marks 202 (uneven shape) are formed on the surface.

  Further, a part of the electrode pad (needle dust) peeled off by the test probe 201 adheres to the substrate surface, and another part remains on the electrode pad 102 as a large protrusion 204. Therefore, after the electrical characteristic inspection, cleaning is performed to remove needle dust and the like attached to the substrate surface. As shown in FIG. 3C, the large protrusion 204 formed on the electrode pad is cleaned. Even if it passes through, it is hardly removed and remains on the electrode pad 102 as it is.

  When a bump is formed on the electrode pad in this state, as shown in FIG. 3D, the shape of the bump 105 is broken, and a large protrusion 205 is formed on the bump surface. Due to the influence of the large protrusion 205 formed on the surface of the bump 105, the bump adhesion strength is reduced as compared with the case where the bump is formed on the electrode pad without the probe trace, and the semiconductor substrate 101 is cracked in the mounting process. There was a problem related to the reliability of the implementation.

  In order to solve this problem, for example, in Patent Document 1, a method for repairing a probe mark by irradiating a probe mark formed on the electrode pad with a laser beam or the like and melting the surface of the electrode pad. Has been proposed. However, in this method, since it is necessary to irradiate an infinite number of electrode pads on the wafer with laser light or the like, there is a concern about a decrease in production capacity and an increase in cost.

Therefore, the present invention has been made to solve the above-described problems, and in the case where bumps are formed on electrode pads after testing the semiconductor element characteristics (electric characteristic inspection) An object of the present invention is to provide an electrode pad structure that does not cause a reduction in mounting reliability without increasing costs.
Japanese Patent Laid-Open No. 6-267884

  In order to achieve the above object, the present invention has the following features.

  That is, in a semiconductor integrated circuit device in which a test probe is brought into contact with an electrode pad serving as an input / output terminal of a semiconductor integrated circuit, and electrical characteristics inspection of the semiconductor integrated circuit is performed, and then a bump is formed on the electrode pad. A semiconductor integrated circuit device in which an electrode pad is composed of two or more conductor layers, wherein the first conductor layer formed on the top of the conductor layers is a soft metal material. And the second conductor layer formed under the first conductor layer is formed of a hard metal material, and the first conductor layer has a plurality of grooves. It is formed and has an island shape. The plurality of grooves formed in the first conductor layer are formed in a region where the test probe contacts and a peripheral region thereof.

  The first conductor layer is formed of Al or an alloy containing Al.

  According to the present invention, a plurality of grooves are formed in the surface layer of the electrode pad serving as the input / output terminal of the semiconductor integrated circuit, so that a shape without large irregularities (probe marks) is obtained on the electrode pad after the electrical characteristic inspection. It is done. Therefore, when bumps are formed on the electrode pads after the electrical characteristic inspection, problems such as a decrease in bump adhesion strength and generation of cracks in the semiconductor substrate in the mounting process do not occur. Therefore, a semiconductor integrated circuit device with high mounting reliability can be obtained. Can be provided.

  The present invention relates to a structure of an electrode pad in a semiconductor integrated circuit device, particularly when bumps are formed on the electrode pad after an electrical characteristic test. Embodiments of the present invention will be described below.

  FIG. 1 is a schematic diagram showing the structure of an electrode pad of a semiconductor integrated circuit device according to an embodiment of the present invention.

  In FIG. 1, a second layer is provided as an electrode pad for connecting a semiconductor element (not shown) formed on the semiconductor substrate 101 and an external input / output terminal on the upper layer of the semiconductor substrate 101 on which the semiconductor integrated circuit is formed. A conductor layer 108 and a first conductor layer 109 are sequentially stacked. Here, the first conductor layer 109 is a soft metal material, and is formed of, for example, Al or an alloy containing Al. The second conductor layer 108 is formed of a hard metal material (rather than the material of the test probe 201).

  A protective film 103 is formed on the semiconductor substrate 101 and the first conductor layer 109, and a protective film 103 is formed on the first conductor layer 109 so as to be electrically connected to an external input / output terminal. A surhole 106 is formed in the film 103. Further, the first conductor layer 109 has an island shape in which a plurality of grooves are formed by a photolithography technique.

  In the present embodiment, as shown in FIG. 1, a lattice-like groove is formed on the entire surface of the through hole 106, but the plurality of grooves are formed at least in a region where the electrode pad and the test probe are in contact with each other. That's fine.

  Next, with reference to FIG. 2, description will be given of a manufacturing process in the case where bump formation is performed after electrical characteristic inspection is performed with the electrode pad structure proposed in the present invention. In FIG. 2A, since the first conductor layer 109 which is the uppermost layer of the electrode pad portion is formed of Al or an alloy containing Al, the surface is covered with a natural oxide film. Therefore, when performing an electrical characteristic test, a natural oxide film formed on the surface of the first conductor layer 109 to ensure electrical contact between the test probe 201 and the first conductor layer 109. Therefore, it is necessary to make the test probe 201 and the first conductor layer 109 contact each other.

  Therefore, as shown in FIG. 2B, the natural oxide film is peeled off by rubbing the test probe 201 on the first conductor layer 109 to bring the test probe 201 into contact with the electrode pad. At this time, since the first conductor layer 109 has an island shape and the second conductor layer 108 is a hard metal material, the tip of the test probe 201 is connected to the first conductor layer 109 and the first conductor layer 109. A part of the island-shaped first conductor layer 109 is peeled off as small fragments 203 and adheres to the substrate surface or the like. Accordingly, probe marks are formed on the electrode pads, but large protrusions as shown in FIG. 3B are not formed.

  Next, after the electrical property inspection, cleaning is performed to remove needle dust attached to the substrate surface. Since the small debris 203 generated by the test probe 201 is removed by the cleaning, there is no large protrusion as shown in FIG. 3C on the electrode pad.

  Next, in FIG. 2D, the bump 105 is formed on the electrode pad portion through the bump manufacturing process. Since large protrusions are not formed on the surface of the electrode pad portion, the bump surface has small irregularities compared to FIG. 3D, and has a flatter shape. Therefore, problems such as a decrease in the adhesion strength of the bumps and a crack in the semiconductor substrate 101 during the mounting process did not occur.

It is a schematic diagram which shows the structure of the electrode pad of the typical semiconductor integrated circuit device in this invention. It is sectional drawing which shows a manufacturing process at the time of performing bump formation after an electrical property test | inspection with the electrode pad structure in this invention. It is sectional drawing which shows the manufacturing process at the time of performing bump formation after an electrical property test | inspection with the conventional electrode pad structure. It is sectional drawing which shows typically schematic structure of the conventional electrode pad. It is sectional drawing which shows typically the manufacturing process until it reaches the outline structure of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 Electrode pad 103 Protective film 104 Bump foundation metal film 105 Bump 106 Through hole 107 Photoresist 108 Second conductor layer 109 First conductor layer 201 Test probe 202 Probe mark 203 Small debris of electrode pad (small Debris)
204 Large pieces of electrode pad (large protrusions)
205 Protrusion on bump

Claims (3)

In a semiconductor integrated circuit device in which a test probe is brought into contact with an electrode pad serving as an input / output terminal of a semiconductor integrated circuit, an electrical characteristic inspection of the semiconductor integrated circuit is performed, and then a bump is formed on the electrode pad.
A semiconductor integrated circuit device in which the electrode pad is composed of two or more conductor layers, wherein the first conductor layer formed on the top of the conductor layers is a soft metal. A second conductor layer formed of a material and formed below the first conductor layer is formed of a hard metal material;
A semiconductor integrated circuit device, wherein a plurality of grooves are formed in the first conductor layer to form an island shape.   2. The semiconductor integrated circuit device according to claim 1, wherein the plurality of grooves formed in the first conductor layer are formed in a region where the test probe contacts and a peripheral region thereof.   3. The semiconductor integrated circuit device according to claim 1, wherein the first conductor layer is made of Al or an alloy containing Al.

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