JP2008028336A - Method of manufacturing electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture an electronic component such that conductive material is embedded into a via hole formed in a substrate by using a plating method with favorable embedding characteristics. <P>SOLUTION: The manufacturing method includes: a plating step of embedding conductive material into the via hole with an electrolytic plating method by dividing a conductive layer arranged so as to plug up two or more via holes formed in a substrate into two or more regions and by controlling individually the current flowing into the conductive layers of the two or more regions; and a conductive pattern formation step of forming a conductive pattern connected to the above conductive material. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing an electronic component including a step of embedding a conductive material by an electrolytic plating method.

  When manufacturing various electronic components such as a wiring board and a semiconductor device, a plating process in which a via hole penetrating the board is embedded with a conductive material by a plating method may be used. The plating method has a feature that a conductive material can be easily embedded in a via hole at a high film formation rate.

  1A to 1B are diagrams schematically showing a method of manufacturing an electronic component using a plating method. First, in the step shown in FIG. 1A, a via hole 2A is formed in the insulating layer 2 formed on the core substrate 1, and a conductive layer 2B serving as a power feeding layer for electrolytic plating is formed by electroless plating. In this case, the conductive layer 2B is formed on the bottom surface of the via hole 2A (exposed insulating layer 2), the side wall surface of the via hole 2A, and further on the insulating layer 2.

Next, in the step shown in FIG. 1B, the via hole 2A is embedded with the conductive material 3 by electrolytic plating using the conductive layer 2B formed in the step of FIG. 1A as a power feeding layer.
JP 2005-39142 A

  However, according to the above method, there is a problem that the void 3A is likely to be generated when the conductive material is embedded. For example, when the power supply layer (electroconductive layer 2B) for electroplating is formed by electroless plating, the power supply layer is formed not only on the bottom surface of the via hole 2A but also on the side wall surface of the via hole and further on the outside of the via hole. It will be. For this reason, the growth of electrolytic plating occurs not only from the bottom surface of the via hole but also from the side wall surface of the via hole and the outside of the via hole (near the opening). There was a case.

  In the above-described method, voids tend to be easily generated particularly when the aspect ratio of the via hole is increased. For example, in the above method, it has been difficult to embed a conductive material in a void-free manner in a via hole having an aspect ratio of 1 or more. In addition, it is difficult to uniformly embed a conductive material in via holes having different diameters (different aspect ratios), and the state of burying may vary in the plane of the substrate.

  In view of this, the present invention has a general object to provide a new and useful method of manufacturing an electronic component that solves the above-described problems.

  A specific problem of the present invention is to manufacture an electronic component by embedding a conductive material in a via hole formed in a substrate with a good embedding characteristic by a plating method.

  The present invention solves the above problem by dividing a conductive layer installed so as to block a plurality of through holes formed in a substrate into a plurality of regions, and individually controlling currents flowing through the conductive layers in the plurality of regions. A method of manufacturing an electronic component comprising: a plating step of burying a conductive material in the through hole by electrolytic plating; and a conductive pattern forming step of forming a conductive pattern connected to the conductive material. Resolve.

  According to the present invention, an electronic component can be manufactured by embedding a conductive material in a via hole formed in a substrate by a plating method with good embedding characteristics.

  Further, when the conductive layer is divided into at least a first region corresponding to the central portion of the substrate and a second region corresponding to the peripheral portion of the substrate, the first region and the second region are divided. It is possible to adjust the growth rate of plating in this area, which is preferable.

  In the plating step, if the current flowing through the first region is larger than the current flowing through the second region, the difference in the plating growth rate between the first region and the second region may be reduced. This is possible and preferable.

  In addition, if the substrate has a plurality of through holes having different diameters, and the conductive layer is divided according to the diameter of the through holes, the growth rate of plating due to the difference in the diameters of the through holes It is possible to adjust the difference between the two.

  Further, in the plating step, when the diameters of the through holes corresponding to the divided conductive layers are compared, the current flowing through the conductive layer corresponding to the through holes having a small diameter is larger than the diameter. When the current is larger than the current flowing in the conductive layer corresponding to the through hole, it is possible to reduce the difference in the growth rate of plating due to the difference in the diameter of the through hole.

  The conductive layer may be bonded to the substrate with an adhesive layer.

  Moreover, you may further have the process of mounting a semiconductor chip in the said conductive pattern.

  According to the present invention, an electronic component can be manufactured by embedding a conductive material in a via hole formed in a substrate by a plating method with good embedding characteristics.

  FIG. 2 is a cross-sectional view for explaining the outline of the method of manufacturing an electronic component according to the present invention. The method for manufacturing an electronic component according to the present invention includes a step of burying a conductive material in a via hole (through hole) 102 formed in the substrate 101 by a plating method to form a via plug.

  In the manufacturing method described above, a conductive material is embedded in the via hole 102 by using the conductive layer 104 provided so as to close the plurality of via holes 102 formed in the substrate 101 as a power supply layer of an electrolytic plating method.

  In this case, since the power feeding layer (conductive layer 104) is formed only on the bottom surface of the via hole 102, the conductive material filled by electrolytic plating grows substantially only from the bottom surface of the via heel 102. For this reason, the embedding characteristic (coverage) of the plating becomes good, and it is possible to embed the conductive material while suppressing the generation of voids even when the aspect ratio of the via hole 102 is high.

  For example, in the electroplating method (FIGS. 1A to 1B) by forming a power feeding layer by electroless plating, it was difficult to bury a via hole having an aspect ratio of 1 or more in a void-free manner, A conductive material can be embedded in a fine via hole having an aspect ratio of about 1 to 20 while suppressing generation of voids.

  For example, in the above case, the conductive layer (feeding layer) 104 made of Cu is bonded to the substrate by the adhesive layer (adhesive material) 103 so as to close one end of the opening hole of the via hole 102 formed in the substrate 101 made of Si. 101 is attached. For example, in the above structure, a conductive material such as Cu can be embedded in the via hole 102 to form a via plug.

  In the above case, it is preferable to divide the conductive layer 104 into a plurality of regions and individually control currents flowing through the conductive layers 104 in the plurality of regions. In this case, conductive materials are embedded in the through holes 102 corresponding to the plurality of regions, respectively, by electrolytic plating. As described above, when the conductive layer is divided, it is possible to reduce variation in the local growth rate of plating in the substrate surface.

  3A is a cross-sectional view schematically showing the whole of the substrate 101, the adhesive layer 103, and the conductive layer 104 described above in FIG. 2, and FIG. 3B is a plan view of the adhesive layer 103 and the conductive layer 104 in FIG. 3A. It is. However, the same code | symbol is attached | subjected to the part demonstrated previously in FIG.

  3A and 3B, the conductive layer 104 provided on the substrate 101 is divided into a conductive layer 104A corresponding to the central portion of the substrate 101 and a conductive layer 104B corresponding to the peripheral portion of the substrate 101. Yes. A via hole 102A is formed in a portion corresponding to the conductive layer 104A of the substrate 101, and a via hole 102B is formed in a portion corresponding to the conductive layer 104B of the substrate 101.

  In the conventional electrolytic plating method, since various conditions concerning the electrolytic plating method differ between the central portion and the peripheral portion of the substrate, the plating growth rate (film formation rate) may vary. . Typically, the growth rate tends to be high at the peripheral edge of the substrate and low at the center of the substrate. As described above, there are various reasons why the growth rate varies between the central portion and the peripheral portion of the substrate. For example, the length of the power supply path for electrolytic plating is different. It is thought that.

  Therefore, in the present invention, the conductive layer 104 serving as a power feeding layer for electrolytic plating is divided into a plurality of regions (for example, the conductive layer 104A and the conductive layer 104B), and the current flowing through each conductive layer is controlled independently. Thus, variation in the growth rate of plating within the surface of the substrate can be reduced.

  FIG. 4 is a diagram schematically showing a method of embedding a conductive material (Cu) in the via hole 102 of the substrate 101 shown in FIGS. 3A and 3B by electrolytic plating. However, the parts described above are denoted by the same reference numerals, and description thereof is omitted. In the drawing, the via hole 102 and the adhesive layer 103 are not shown.

  Referring to FIG. 4, a substrate (wafer) 101 serving as a cathode is supported by a jig and immersed in a plating solution so as to face a Cu plate serving as an anode. Further, as described above, the conductive layer 104 is divided into the conductive layer 104A and the conductive layer 104B. A power source is connected to each of the conductive layers 104A and 104B, and an ammeter (voltmeter) is individually connected. ) Is installed and the flowing current is controlled.

  For example, a power source is connected to the conductive layer 104A via the ammeter 1, and another power source is connected to the conductive layer 104B via the ammeter 2. In addition, the ammeter 1 and the ammeter 2 are connected to control means, respectively, and the control means controls the power supply according to the current value (voltage value) detected by the ammeter 1 and ammeter 2. Further, although two power supplies are shown in the figure, a common power supply may be provided for the divided conductive layers, and a current (voltage) control circuit may be provided separately.

  For example, in the above case, the current flowing in the conductive layer 104A corresponding to the center of the substrate is made larger than the current flowing in the conductive layer 104B corresponding to the peripheral portion of the substrate, thereby varying the growth rate of electrolytic plating in the substrate surface. Can be suppressed.

  Further, the number of divisions of the conductive layer (feeding layer) is not limited to two, and may be three or more, for example. Further, the method for dividing the conductive layer is not limited to the case where the conductive layer is divided at the center portion and the peripheral portion of the substrate. For example, the conductive layer may be divided according to the diameter of the via hole formed in the substrate (this example). (It will be described later in FIG. 7A).

  In manufacturing an electronic component (semiconductor device), a plurality of electronic components may be manufactured using the substrate 101, and the plurality of electronic components (semiconductor chips) may be separated (separated) in a later process. FIG. 5 is an example showing an arrangement state of electronic components formed on the substrate 101. As described above, the electronic components may be arranged in a lattice pattern. For example, in the case shown in this figure, the conductive layer 104 </ b> A may be installed corresponding to the electronic component near the center of the substrate 101, and the conductive layer 104 </ b> B may be installed corresponding to the electronic component in the peripheral portion of the substrate 101.

  Next, the details of the method for manufacturing the electronic component will be described step by step. However, the same reference numerals are given to the parts described above, and the description may be omitted.

  First, in the process shown in FIG. 6A, the substrate (wafer) 101 made of, for example, Si is thinned by back surface grinding so that the thickness becomes about 200 μm. Next, a plurality of via holes (through holes) 102 having a diameter of, for example, 60 μm are formed in the substrate 101 by dry etching using a mask pattern (not shown) formed by photolithography.

  Next, in a step shown in FIG. 6B, an insulating film (thermal oxide film) 105 is formed by thermally oxidizing the surface of the substrate 101. Further, the insulating film 105 may be partially peeled off as necessary (for example, a part to be anodically bonded in a later process).

  Next, in the step shown in FIG. 6C, a conductive layer 104 made of Cu, for example, is attached to the substrate 101 using an adhesive layer (layer made of an adhesive material) 103. In this case, the conductive layer 104 is attached so as to close the opening on one side of the via hole 102.

  Further, as described in FIGS. 3A, 3B, and 4 to 5, the conductive layer 104 is divided into a plurality of regions (for example, the central conductive layer 104A and the peripheral conductive layer 104B). .

  Next, in the step shown in FIG. 6D, after removing the adhesive layer 103 at the bottom of the via hole 102 to expose the conductive layer 104, a conductive material (conducting material (not shown) is formed in the via hole 102 by electrolytic plating using the conductive layer 104 as a power feeding layer. Cu) is buried and a via plug 106 is formed.

  In this case, as described above with reference to FIGS. 3A, 3B, and 4 to 5, the conductive layer 104 is divided into, for example, the conductive layer 104A and the conductive layer 104B, and flows into the respective conductive layers 104A and 104B. The current (applied voltage) is individually controlled.

  For example, by making the current flowing through the conductive layer 104A corresponding to the center of the substrate 101 larger than the current flowing through the conductive layer 104B corresponding to the peripheral portion of the substrate, electrolytic plating at the central portion of the substrate and the peripheral portion of the substrate is performed. It is possible to suppress variations in the growth rate.

  Next, in the step shown in FIG. 6E, the conductive layer 104 and the adhesive layer 103 are removed, and in the step shown in FIG. 6F, Cu protruding from the via hole 102 is removed by polishing.

  Next, in the process shown in FIG. 6G, the upper surface of the substrate 101 (the surface opposite to the side where the conductive layer 104 was installed, the same applies to the following) and the insulating layer 105 on the lower surface of the substrate 101 are electrically conductive. Layers 107 and 108 are formed.

  For example, the conductive layers 107 and 108 have a Cr (thickness 50 nm) / Cu (thickness 750 nm) structure (a stacked structure in which Cu is on the outside) and are formed by a sputtering method. These conductive layers 107 and 108 serve as a power feeding layer when a conductive pattern connected to the via plug 106 is formed by an electrolytic plating method in a later step.

  Next, in the step shown in FIG. 6H, a conductive pattern 109 made of Cu connected to the via plug 106 is formed on the lower surface of the substrate 101 by pattern plating using a plating resist (not shown). In the above electrolytic plating, the conductive layer 108 is used as a power feeding layer. Further, the conductive layer 108 exposed by peeling the plating resist after the formation of the conductive pattern 109 is peeled off by etching.

  Next, in the step shown in FIG. 6I, a protective layer (insulating layer) 111 covering the insulating film 105 is formed so as to expose a part of the conductive pattern 109. In addition, a connection layer 110 made of, for example, a Ni / Au structure (a laminated structure with Au on the outside) is formed on the conductive pattern 109 exposed from the protective layer 111 by electrolytic plating.

  Next, in a step shown in FIG. 6J, a conductive pattern 112 made of Cu connected to the via plug 106 is formed on the upper surface of the substrate 101 by pattern plating using a plating resist (not shown). In the above electrolytic plating, the conductive layer 107 is used as a power feeding layer. Furthermore, a connection layer 113 made of, for example, a Ni / Au structure is formed on the conductive pattern 112 by an electrolytic plating method. Further, the conductive layer 107 exposed by the plating resist peeling after the formation of the conductive pattern 112 and the connection layer 113 is peeled off by etching.

  In this manner, a wiring board (electronic component) having via plugs 106 penetrating the substrate 101 and conductive patterns 109 and 112 connected to the via plugs 106 can be manufactured. Further, a semiconductor chip may be further mounted on the above wiring board, and an electronic component having a structure in which the semiconductor chip is mounted may be configured.

  For example, in the step shown in FIG. 6K, the semiconductor chip 201 to which the bump 202 made of Au is connected is mounted on the connection layer 113. In this case, the semiconductor chip can be flip-chip mounted by bonding the bump 202 and the Au of the connection layer 113 using ultrasonic waves.

  Further, in the step shown in FIG. 6L, the substrate 101 is cut into pieces by dicing. Further, when the semiconductor chip 201 is made of an optical functional element such as a light emitting element or a light receiving element, a cover 203 made of a light transmissive material is bonded onto the substrate 101 as necessary, and the semiconductor chip 201 is sealed. It is good also as a structure. When the light transmissive material is made of glass, the cover 203 is bonded to the substrate 101 by anodic bonding. In this case, a convex portion of the cover 203 may be bonded to a portion where the insulating film 105 is peeled and Si is exposed. Further, solder balls 114 may be formed on the connection layer 110 as external connection terminals.

  In this way, an electronic component in which the semiconductor chip 201 is mounted on the substrate 101 can be manufactured.

  According to the above manufacturing method, when the via plug 106 penetrating the substrate 101 is formed, variations in the growth rate of the electrolytic plating within the surface of the substrate (for example, the central portion of the substrate 101 and the peripheral portion of the substrate 101) are suppressed. It is possible to manufacture electronic components of good quality.

  Further, in the above manufacturing method, when the via hole 102 of the substrate 101 is embedded by electrolytic plating, the growth of plating occurs substantially only from the bottom surface (conductive layer 104), so even for a via hole having a high aspect ratio, It is possible to bury the conductive material (form the via plug 106) while suppressing the generation of voids.

  For example, according to the above manufacturing method, a via hole having an aspect ratio of about 1 to 20 can be buried free of voids. The above manufacturing method can be applied to a via hole having a diameter of 10 to 200 μm. However, these numerical values are examples, and the present invention is not limited to these numerical values.

  Further, in the case of Example 1, the conductive layer serving as the power feeding layer for electrolytic plating was divided corresponding to the central portion and the peripheral portion of the substrate, but the present invention is not limited to this. For example, the conductive layer may be divided corresponding to the diameter of the via hole.

  For example, in the conventional electrolytic plating method, there are cases where the growth rate of plating varies when the diameters of via holes are different. Normally, when the via hole diameter is large, the plating solution ion exchange efficiency is improved, so the plating growth rate tends to increase. On the other hand, in the portion where the via hole diameter is small, the plating growth rate is low. Tend to be. For this reason, it is difficult to suppress variations in the growth rate of plating in a substrate on which via holes having different diameters are formed.

  FIG. 7A shows an arrangement of electronic components (semiconductor chips) formed on the substrate, and each electronic component shows an example of the size of a via hole to be formed. As described above, via holes having different sizes are often formed in a region where one chip is formed.

  For example, when via holes have different diameters as shown in FIG. 7A, the conductive layer may be divided as shown in FIG. 7B. FIG. 7B is an enlarged view of the electronic component shown in FIG. 7A and shows an example of a divided state of the conductive layer installed on the electronic component (substrate).

  Referring to FIG. 7B, conductive layer 104A is formed so as to correspond to a via hole having a small diameter, and conductive layer 104B is formed to correspond to a via hole having a large diameter. The conductive layers 104A and 104B are preferably patterned so as to be common (connected and formed) to a plurality of electronic components.

  With respect to the conductive layers 104A and 104B configured as described above, as shown in FIG.

  In this case, the diameters of the respective via holes corresponding to the divided conductive layers 104A and 104B are compared, and the current flowing through the conductive layer 104A corresponding to the via hole having a small diameter is applied to the conductive layer 104B corresponding to the via hole having a large diameter. It is preferable to control the current value so as to be larger than the flowing current.

  When the current value is controlled as described above, variations in the growth rate of plating due to the difference in via hole diameter can be suppressed, and high-quality electronic components can be manufactured.

  FIG. 8 is a cross-sectional view showing the configuration of an electronic component manufactured using the method for manufacturing an electronic component according to this embodiment. However, the parts described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 8, this embodiment is characterized in that via plugs 106 </ b> A smaller than the diameter of the via plug 106 are formed between the via plugs 106 and connected to the semiconductor chip 201.

  In the case of manufacturing the above-described electronic component, the conductive pattern may be divided as shown in FIG. 9 (FIG. 7B) in forming the via plugs 106 and 106A penetrating the substrate 101. FIG. 9 is a diagram corresponding to FIG. 6D of the first embodiment. However, the parts described above are denoted by the same reference numerals, and description thereof is omitted.

  In the process shown in this drawing, the conductive layer 104 is divided so that the conductive layer 104A corresponds to the via hole (via plug 106A) having a small diameter and the conductive layer 104B corresponds to the via hole (via plug 106) having a large diameter. ing. Here, as described above, the current value is controlled so that the current flowing through the conductive layer 104A corresponding to the via hole having a small diameter is larger than the current flowing through the conductive layer 104B corresponding to the via hole having a large diameter. Therefore, it is possible to suppress the variation in the growth rate of plating due to the difference in the diameter of the via hole, and to manufacture a high-quality electronic component.

  Except for the steps shown in this drawing, the electronic component shown in FIG. 8 can be manufactured in the same manner as in the case of the first embodiment.

  As described above, the division of the conductive layer can be variously changed according to the specification of the electronic component. For example, when the growth rate of electrolytic plating varies for various reasons, it is possible to manufacture high-quality electronic components by suppressing the variation in growth rate by dividing the conductive layer and controlling the current independently. It becomes.

  It is also possible to form a multilayer wiring board by a so-called build-up method by forming conductive patterns and insulating layers in multiple layers on via plugs that penetrate the substrate.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the specific embodiments described above, and various modifications and changes can be made within the scope described in the claims.

  According to the present invention, an electronic component can be manufactured by embedding a conductive material in a via hole formed in a substrate by a plating method with good embedding characteristics.

It is a figure (the 1) which shows the manufacturing method of the conventional electronic component. It is FIG. (2) which shows the manufacturing method of the conventional electronic component. 1 is a diagram showing an outline of a method for manufacturing an electronic component according to Example 1. FIG. It is FIG. (1) which shows an example of the installation method of a conductive layer. It is a top view of FIG. 3A. It is a figure which shows the control method of the electric current value of a conductive layer. It is a figure (the 2) which shows an example of the installation method of a conductive layer. FIG. 6 is a diagram (No. 1) illustrating a method for manufacturing an electronic component according to the first embodiment. FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 3 is a diagram (No. 3) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 6 is a diagram (No. 4) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 10 is a diagram (No. 5) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 6 is a view (No. 6) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 7 is a view (No. 7) showing a method for manufacturing an electronic component according to Example 1. FIG. 8 is a view (No. 8) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 9 is a diagram (No. 9) illustrating a method for manufacturing an electronic component according to Example 1. FIG. 10 is a view (No. 10) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 11 is a view (No. 11) illustrating the method for manufacturing the electronic component according to the first embodiment. FIG. 12 is a view (No. 12) illustrating the method for manufacturing the electronic component according to the first embodiment. It is a figure which shows the arrangement | sequence of the chip | tip formed in a board | substrate. It is FIG. (3) which shows an example of the installation method of a conductive layer. FIG. 6 is a diagram (No. 1) illustrating a method for manufacturing an electronic component according to a second embodiment. FIG. 10 is a second diagram illustrating a method of manufacturing an electronic component according to the second embodiment.

Explanation of symbols

101 Substrate 102 Via hole (through hole)
103 Adhesive layer 104, 104A, 104B Conductive layer 105 Insulating film 106, 106A Via plug 107, 108 Conductive layer 109, 112 Conductive pattern 110, 113 Connection layer 111 Protective layer 114 Solder ball 201 Semiconductor chip 202 Bump 203 Cover

Claims (7)

A conductive layer installed so as to block a plurality of through holes formed in the substrate is divided into a plurality of regions, and currents flowing through the conductive layers in the plurality of regions are individually controlled to electroplat the through holes. A plating process for burying a conductive material;
And a conductive pattern forming step of forming a conductive pattern connected to the conductive material.   The electronic component according to claim 1, wherein the conductive layer is divided into at least a first region corresponding to a central portion of the substrate and a second region corresponding to a peripheral portion of the substrate. Manufacturing method.   3. The method of manufacturing an electronic component according to claim 2, wherein, in the plating step, a current flowing through the first region is larger than a current flowing through the second region.   2. The method of manufacturing an electronic component according to claim 1, wherein a plurality of through holes having different diameters are formed in the substrate, and the conductive layer is divided in accordance with the size of the diameter of the through holes.   In the plating step, when the diameters of the through holes corresponding to the divided conductive layers are compared, the current flowing in the conductive layer corresponding to the through holes having a small diameter is larger than the through holes having a large diameter. 5. The method of manufacturing an electronic component according to claim 4, wherein the current is larger than a current flowing in the conductive layer corresponding to.   The method of manufacturing an electronic component according to claim 1, wherein the conductive layer is bonded to the substrate by an adhesive layer.   The method of manufacturing an electronic component according to claim 1, further comprising a step of mounting a semiconductor chip on the conductive pattern.

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