JP7266469B2 - Wiring board manufacturing method and laminated structure - Google Patents

Description

The present disclosure relates to a method of manufacturing a wiring board and a laminate structure.

In one method of manufacturing a wiring substrate, a resin layer is formed on a support substrate having a release layer, conductive vias are formed in the resin layer, and fine wiring is formed on the resin layer.

JP 2013-251313 A

In the above method, the metal layer may be polished during the formation of the conductive via, but the release layer may be peeled off during the polishing of the metal layer.

An object of the present disclosure is to provide a wiring substrate manufacturing method and a laminated structure that can suppress peeling of a peeling layer during polishing.

According to one aspect of the present disclosure, a step of preparing a support substrate including a support and a release layer on the support; forming an insulating layer on the release layer; forming a via hole; forming a first conductive layer in the via hole and on the insulating layer; and polishing the first conductive layer, and preparing the support substrate. and polishing the first conductive layer, exposing the side surface of the release layer on the support; and forming a protective material covering the side surface of the release layer on the support. and a step of exposing the side surface of the release layer between the step of preparing the support substrate and the step of forming the insulating layer, wherein the step of forming the insulating layer includes: The side surface of the release layer is covered with a part of the insulating layer as the protective material, and an opening is provided on the release layer between the step of preparing the supporting substrate and the step of exposing the side surface of the release layer. and forming a second conductive layer to which the first conductive layer is connected in the opening, exposing the side surface of the release layer. A method of manufacturing a wiring board is provided , which includes, between the step and the step of forming the insulating layer, the step of removing the film formation mask .

According to the disclosed technique, peeling of the peeling layer during polishing can be suppressed.

FIG. 4 is a cross-sectional view (part 1) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 2 is a cross-sectional view (Part 2) showing the method of manufacturing the wiring board according to the first embodiment; 3 is a cross-sectional view (part 3) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 4 is a cross-sectional view (part 4) showing the method for manufacturing the wiring board according to the first embodiment; FIG. FIG. 5 is a cross-sectional view (No. 5) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 8 is a cross-sectional view (No. 6) showing the method for manufacturing the wiring board according to the first embodiment; 7 is a cross-sectional view (No. 7) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 8 is a cross-sectional view (No. 8) showing the method for manufacturing the wiring board according to the first embodiment; FIG. FIG. 10 is a cross-sectional view (No. 9) showing the method for manufacturing the wiring board according to the first embodiment; 10 is a cross-sectional view (No. 10) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 11A and 11B are cross-sectional views (No. 11) showing the method for manufacturing the wiring board according to the first embodiment; 12 is a cross-sectional view (No. 12) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 13 is a cross-sectional view (No. 13) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 14 is a cross-sectional view (part 14) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 15 is a cross-sectional view (No. 15) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 16 is a cross-sectional view (No. 16) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 17 is a cross-sectional view (No. 17) showing the method for manufacturing the wiring board according to the first embodiment; FIG. 18 is a cross-sectional view (part 18) showing the method for manufacturing the wiring board according to the first embodiment; FIG. FIG. 11 is a cross-sectional view (part 1) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 11 is a cross-sectional view (part 2) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 11 is a cross-sectional view (No. 3) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 10 is a cross-sectional view showing an example of the constricted shape of the electrode pad in the second embodiment; FIG. 11 is a cross-sectional view (part 1) showing the method of manufacturing the wiring board according to the third embodiment; FIG. 12 is a cross-sectional view (part 2) showing the method of manufacturing the wiring board according to the third embodiment; FIG. 14 is a cross-sectional view (No. 3) showing the method of manufacturing the wiring board according to the third embodiment; FIG. 14 is a cross-sectional view (part 4) showing the method of manufacturing the wiring board according to the third embodiment; FIG. 15 is a cross-sectional view (No. 5) showing the method for manufacturing the wiring board according to the third embodiment; FIG. 16 is a cross-sectional view (No. 6) showing the method of manufacturing the wiring board according to the third embodiment; FIG. 17 is a cross-sectional view (No. 7) showing the method for manufacturing the wiring board according to the third embodiment;

Hereinafter, embodiments will be specifically described with reference to the accompanying drawings. In the present specification and drawings, constituent elements having substantially the same functional configuration may be denoted by the same reference numerals, thereby omitting redundant description.

(First embodiment)
The first embodiment relates to a method of manufacturing a wiring board. 1 to 18 are cross-sectional views showing the method for manufacturing a wiring board according to the first embodiment.

In the first embodiment, a first wiring structure 10 including a support is formed, a second wiring structure 20 is formed on the first wiring structure 10, the first wiring structure 10 and The supporting member is removed from the layered structure 30 of the second wiring structure 20, and the layered structure 30 is mounted on the buildup board 40 separately prepared.

In the first embodiment, first, as shown in FIG. 1, a support substrate 100 is prepared. The support substrate 100 has a support 101 , an adhesion layer 102 , a release layer 103 , an etch stop layer 104 and a seed layer 105 . In the present disclosure, for convenience, the surface of the support 101 facing the adhesion layer 102, release layer 103, etch stop layer 104, and seed layer 105 is referred to as the upper surface, and the other surface is referred to as the lower surface. However, the wiring board can be used upside down, and can be used in any posture.

The adhesion layer 102 is formed on the upper surface 101 A of the support 101 , and the release layer 103 is formed on the adhesion layer 102 . An etch stop layer 104 is formed on the release layer 103 and a seed layer 105 is formed on the etch stop layer 104 . For example, the release layer 103 is an inorganic layer. For example, the adhesion layer 102 has a titanium layer on the support 101 and a copper layer on the titanium layer to adhere the release layer 103 to the support 101 . The etch stop layer 104 has etching resistance to the etchant used for wet etching the seed layer 105 . The material of the seed layer 105 is, for example, metal such as copper. The material of the etch stop layer 104 is metal such as titanium.

The support substrate 100 is provided with a wiring portion 100A that forms wiring in a plan view, and an annular outer peripheral portion 100B that surrounds the wiring portion 100A in a plan view.

Next, as shown in FIG. 2, a plating resist layer 191 having openings 191x is formed on the seed layer 105. Then, as shown in FIG. For example, the openings 191x are provided in areas where pads are to be formed in the wiring section 100A. The plating resist layer 191 is an example of a film formation mask.

Thereafter, as shown in FIG. 3, a metal plating layer 111 made of copper or the like is formed in the opening 191x by electroplating using the seed layer 105 as a plating power supply path. Metal plating layer 111 is an example of a second conductive layer.

Subsequently, as shown in FIG. 4, the plating resist layer 191, the seed layer 105, the etch stop layer 104, the release layer 103, and the adhesion layer 102 are removed in an annular shape in the outer peripheral portion 100B. As a result, the side surface 103A of the release layer 103 is exposed on the support 101. Next, as shown in FIG. In other words, the side surface 103A of the release layer 103 is positioned inside the side surface of the support 101 . Moreover, the interface between the release layer 103 and the etch stop layer 104 and the interface between the release layer 103 and the adhesion layer 102 are also exposed on the support 101 . In other words, these interfaces are positioned inside the side surfaces of the support 101 . The plating resist layer 191, the seed layer 105, the etch stop layer 104, the release layer 103, and the adhesion layer 102 can be removed by processing using, for example, a dicing saw. A portion of the surface of the support 101 may be removed. For example, the width of removal of the plating resist layer 191, the seed layer 105, the etch stop layer 104, the separation layer 103 and the adhesion layer 102 is about 2 mm to 3 mm. For example, the depth of removal of the plating resist layer 191, the seed layer 105, the etch stop layer 104, the release layer 103 and the adhesion layer 102 is about 30 μm to 40 μm including the surface of the support 101.

Next, as shown in FIG. 5, the plating resist layer 191 is removed. Further, the seed layer 105 is removed by wet etching using the metal plating layer 111 as a mask. As a result, the surface of the etch stop layer 104 is exposed. Also, an electrode pad 112 including the seed layer 105 and the metal plating layer 111 is formed.

Thereafter, as shown in FIG. 6, an insulating layer 120 is formed to cover the side surfaces of the adhesion layer 102, the release layer 103 and the etch stop layer 104, the surface of the etch stop layer 104, and the side surfaces and surfaces of the electrode pads 112. As shown in FIG. The insulating layer 120 is an example of a protective material.

The insulating layer 120 includes, for example, a resin layer 121 , a resin layer 122 on the resin layer 121 , and a resin layer 123 on the resin layer 122 . The resin layer 122 is formed by impregnating a reinforcing member such as glass fiber with an insulating resin. The insulating resin with which the reinforcing member of the resin layer 122 is impregnated is cured by heat curing, for example. The resin layers 121 and 123 contain a thermosetting resin, but do not contain a reinforcing member such as glass fiber. The resin layers 121 and 123 may contain filler or the like. For example, the resin layer 122 is thicker than the resin layers 121 and 123, and the resin layer 121 is located closer to the support substrate 100 than the resin layer 122 is. The insulating layer 120 is also formed on the bottom surface 101B of the support 101 .

Subsequently, as shown in FIG. 7, via holes 120x reaching the electrode pads 112 are formed in the insulating layer 120 on the upper surface 101A side of the support 101. Then, as shown in FIG. The via hole 120x can be formed by laser processing, for example. After forming the via hole 120x, it is preferable to perform a desmear treatment to remove resin residue adhering to the surface of the electrode pad 112 exposed at the bottom of the via hole 120x.

Next, as shown in FIG. 8, a seed layer 131 is formed on the surface of the insulating layer 120, the inner wall surface of the via hole 120x, and the surface of the electrode pad 112 on the upper surface 101A side of the support 101 by, for example, electroless plating. Form.

Thereafter, as shown in FIG. 9, a plating resist layer 192 having openings 192x above each electrode pad 112 is formed on the seed layer 131. Then, as shown in FIG.

Subsequently, as shown in FIG. 10, a metal plating layer 132 made of copper or the like is formed in the opening 192x by electroplating using the seed layer 131 as a plating power supply path. The seed layer 131 and the metal plating layer 132 are examples of the first conductive layer.

Next, as shown in FIG. 11, the plating resist layer 192 is removed, and the seed layer 131 is removed by wet etching using the metal plating layer 132 as a mask.

Thereafter, as shown in FIG. 12, the metal plating layer 132 and the seed layer 131 are polished by chemical mechanical polishing (CMP) so that the metal plating layer 132 is flush with the insulating layer 120 . As a result, conductive via 133 including seed layer 131 and metal plating layer 132 is formed in via hole 120x.

Thus, the first wiring structure 10 including the insulating layer 120, the conductive vias 133 in the insulating layer 120, and the electrode pads 112 connected to the conductive vias 133 is formed.

When polishing the metal plating layer 132 and the seed layer 131, the upper surface of the resin layer 123 may be polished. In this case, undulations on the upper surface of the resin layer 123 generated on the surface during lamination are removed by polishing to obtain a flatter surface. If the flatness of the upper surface of the resin layer 123 is high, the wiring of the second wiring structure 20 formed on the upper surface of the resin layer 123 can be made finer.

Subsequently, as shown in FIG. 13, the insulating layer 141 and the wiring 151 are formed on the insulating layer 120 and the conductive via 133 by, for example, a semi-additive method, and the insulating layer 142 and the wiring 152 are formed on the insulating layer 141 and the wiring 151. An insulating layer 143 and a wiring 153 are formed over the insulating layer 142 and the wiring 152 , and an insulating layer 144 and a wiring 154 are formed over the insulating layer 143 and the wiring 153 .

In this manner, the second wiring structure 20 including the insulating layers 141 to 144 and the wirings 151 to 154 is formed, and the laminated structure of the first wiring structure 10 and the second wiring structure 20 is formed. 30 is obtained. The number of insulating layers and wiring included in the second wiring structure 20 is not particularly limited. The second wiring structure 20 is an example of multilayer wiring.

Next, as shown in FIG. 14, the adhesive layer 102 and the support 101 are peeled off from the etch stop layer 104 together with the peeling layer 103 . In this peeling, for example, the laminated structure 30 is cut at the portion closer to the wiring portion 100A than the side surfaces of the etch stop layer 104, the peeling layer 103 and the adhesion layer 102 at the outer peripheral portion 100B. As a result, the interface between the release layer 103 and the etch stop layer 104 is exposed. Therefore, the release layer 103 can be easily separated from the etch stop layer 104 . The etch stop layer 104 is exposed as the peeling layer 103 is peeled off.

Thereafter, as shown in FIG. 15, the etch stop layer 104 is removed to expose the end surface 112A of the electrode pad 112. Next, as shown in FIG. Etch stop layer 104 can be wet etched using an etchant that is different from the etchant used to wet etch seed layer 105 . Therefore, the end surfaces 112A of the electrode pads 112 on the lower surface of the first wiring structure 10 are not etched, and the surfaces are kept smooth and less rough. Since the top surface of the etch stop layer 104 is flat like the top surface 101A of the support 101, the end surface 112A and the bottom surface of the resin layer 121 are flush with each other.

Subsequently, as shown in FIG. 16, an adhesive layer 50 is formed on the lower surface of the first wiring structure 10 to cover the end surface 112A of the electrode pad 112. Next, as shown in FIG. Since the end surface 112A and the lower surface of the first wiring structure 10 are flush with each other, the adhesive layer 50 formed on the lower surface of the first wiring structure 10 can have a uniform thickness. As the adhesive layer 50, for example, an NCF (non-conductive film) containing epoxy as a main component can be used.

As shown in FIG. 17, a buildup board 40 is prepared separately. The buildup substrate 40 has, for example, a core layer 160 , a buildup layer 170 laminated on the upper surface of the core layer 160 , and a buildup layer 180 laminated on the lower surface of the core layer 160 . An electrode pad 171 is formed on the top surface of the buildup layer 170 and an electrode pad 181 is formed on the bottom surface of the buildup layer 180 . The material of the electrode pad 171 is, for example, a conductor such as copper. The electrode pads 171 are used as connection terminals when the buildup substrate 40 is joined to the laminated structure 30 . The material of the electrode pad 181 is a conductor such as copper. The electrode pads 181 are used as connection terminals when the buildup board 40 is joined to an external component such as a motherboard. Wirings for electrically connecting the electrode pads 171 and 181 are formed inside the core layer 160 , the buildup layers 170 , and the buildup layers 180 . The buildup board 40 is an example of a mounting board. The number of insulating layers and wiring included in buildup layer 170 and buildup layer 180 is not particularly limited.

Then, as shown in FIG. 18, the laminated structure 30 of the first wiring structure 10 and the second wiring structure 20 is mounted on the buildup board 40 . At this time, the electrode pad 112 and the electrode pad 171 are joined with solder 172 . The adhesive layer 50 is arranged between the bottom surface of the laminate structure 30 (that is, the bottom surface of the first wiring structure 10) and the top surface of the buildup substrate 40, and covers part of the side surface of the laminate structure 30. The laminate structure 30 and the buildup substrate 40 are adhered. As described above, since the adhesive layer 50 has a uniform thickness, the adhesive layer 50 is evenly pushed outward from the lower surface of the first wiring structure 10 when the laminate structure 30 and the buildup substrate 40 are adhered. Therefore, it is difficult to remain on the end surface 112</b>A of the electrode pad 112 . Therefore, it is possible to prevent the adhesive layer 50 from being caught between the electrode pads 112 and the electrode pads 171 and obtain excellent connection reliability.

Thus, a wiring board can be manufactured.

In the first embodiment, when polishing the metal plating layer 132 and the seed layer 131, the side surface 103A of the release layer 103, the interface between the release layer 103 and the etch stop layer 104, and the interface between the release layer 103 and the adhesion layer 102 is covered with an insulating layer 120 . Therefore, it is possible to suppress the generation of starting points of peeling. Therefore, although stress in the direction perpendicular to the thickness direction (in-plane direction) acts on the release layer 103 during polishing, the separation of the release layer 103 can be suppressed. Further, in the polishing by the CMP method, it is possible to suppress the polishing slurry from reaching the peeling layer 103 . In this respect as well, peeling of the peeling layer 103 can be suppressed.

Furthermore, in the first embodiment, the top surface of the etch stop layer 104 is covered with the plating resist layer 191 and the seed layer 105 when the side surface 103A of the release layer 103 and the like are exposed on the support 101 using a dicing saw or the like. Therefore, it is possible to suppress contamination of the upper surface of the etch stop layer 104 by particles or the like generated by processing the separation layer 103 or the like.

(Second embodiment)
Next, a second embodiment will be described. The second embodiment differs from the first embodiment in the shape of electrode pads 112 . 19 to 21 are cross-sectional views showing the method of manufacturing the wiring board according to the second embodiment.

In the second embodiment, first, in the same manner as in the first embodiment, processing up to formation of the plating resist layer 191 having the opening 191x is performed (see FIG. 2). Next, as shown in FIG. 19, a metal plating layer 211 made of copper or the like is formed in the opening 191x by electroplating using the seed layer 105 as a plating power supply path. As the metal plating layer 211, a layer having a lower grain boundary density than the seed layer 105 is formed. For example, by forming the seed layer 105 by sputtering, the grain boundary density of the metal plating layer 211 can be made smaller than the grain boundary density of the seed layer 105 .

Thereafter, as shown in FIG. 20, a plating resist layer 191, a seed layer 105, an etch stop layer 104, and a peeling layer 103 are formed on the outer peripheral portion 100B by processing using a dicing saw or the like in the same manner as in the first embodiment. And the adhesion layer 102 is removed. As a result, the side surface 103A of the release layer 103 is exposed on the support 101. Next, as shown in FIG. In other words, the side surface 103A of the release layer 103 is positioned inside the side surface of the support 101 . Moreover, the interface between the release layer 103 and the etch stop layer 104 and the interface between the release layer 103 and the adhesion layer 102 are also exposed on the support 101 . In other words, these interfaces are positioned inside the side surfaces of the support 101 .

Subsequently, as shown in FIG. 21, the plating resist layer 191 is removed. Further, the seed layer 105 is removed by wet etching using the metal plating layer 211 as a mask. As a result, the surface of the etch stop layer 104 is exposed. Also, an electrode pad 212 including the seed layer 105 and the metal plating layer 211 is formed. Since the seed layer 105 and the metal plating layer 211 have different grain boundary densities, the boundary portion between the seed layer 105 and the metal plating layer 211 is preferentially etched when the seed layer 105 is wet-etched. Therefore, a constriction 214 is formed in a region of the outer side surface 212B of the electrode pad 212 corresponding to the boundary portion 213 between the seed layer 105 and the metal plating layer 111 .

Since the grain boundary density of the metal plating layer 211 is smaller than that of the seed layer 105 , the constriction 214 is formed in an asymmetrical shape with respect to the boundary portion 213 between the seed layer 105 and the metal plating layer 211 . Specifically, for example, as shown in FIG. 22 , the constriction 214 is formed in a shape in which the slope of the surface above the boundary portion 213 is greater than the slope of the surface below the boundary portion 213 . FIG. 22 is a cross-sectional view showing an example of the shape of the constriction 214. As shown in FIG.

After the formation of the electrode pads 212, the processes after the formation of the insulating layer 120 (see FIG. 6) are performed in the same manner as in the first embodiment. Thus, a wiring board can be manufactured.

Effects similar to those of the first embodiment can also be obtained by the second embodiment. Furthermore, in the second embodiment, since the contact area between the constriction 214 formed in the electrode pad 212 and the insulating layer 120 is increased, the adhesion between the electrode pad 212 and the insulating layer 120 can be further improved. can.

In the first and second embodiments, the treatment for exposing the side surface 103A of the release layer 103 may be performed after removing the plating resist layer 191 and the seed layer 105. FIG.

(Third Embodiment)
Next, a third embodiment will be described. The third embodiment differs from the first embodiment in the configuration of the protective material that covers the side surface 103A of the release layer 103. FIG. 23 to 29 are cross-sectional views showing the method of manufacturing the wiring board according to the third embodiment.

In the third embodiment, first, similarly to the first embodiment, processing up to formation of the metal plating layer 111 is performed (see FIG. 3). Next, as shown in FIG. 23, the plating resist layer 191 is removed while leaving the seed layer 105, the etch stop layer 104, the release layer 103 and the adhesion layer 102 as a whole. Further, the seed layer 105 is removed by wet etching using the metal plating layer 111 as a mask. As a result, the surface of the etch stop layer 104 is exposed. Also, an electrode pad 112 including the seed layer 105 and the metal plating layer 111 is formed.

After that, as shown in FIG. 24, an insulating layer 120 is formed in the same manner as in the first embodiment.

Subsequently, as shown in FIG. 25, in the outer peripheral portion 100B, the insulating layer 120, the etch stop layer 104, the release layer 103, and the adhesion layer 102 reach the support 101 to form an annular opening 320x in plan view. do. As a result, the side surface 103A of the release layer 103 is exposed on the support 101. Next, as shown in FIG. Moreover, the interface between the release layer 103 and the etch stop layer 104 and the interface between the release layer 103 and the adhesion layer 102 are also exposed on the support 101 . The opening 320x can be formed by processing using a dicing saw, for example. A portion of the surface of the support 101 may be removed.

Next, as shown in FIG. 26, via holes 120x reaching the electrode pads 112 are formed in the insulating layer 120 on the upper surface 101A side of the support 101 in the same manner as in the first embodiment. After forming the via hole 120x, it is preferable to perform a desmear treatment to remove resin residue adhering to the surface of the electrode pad 112 exposed at the bottom of the via hole 120x.

Thereafter, in the same manner as in the first embodiment, processing from formation of the seed layer 131 (see FIG. 8) to wet etching of the seed layer 131 using the metal plating layer 132 as a mask (see FIG. 11) is performed. In the third embodiment, as shown in FIG. 27, the seed layer 131 and the metal plating layer 132 are also formed inside the opening 320x. The seed layer 131 and the metal plating layer 132 inside the opening 320x are examples of protective materials.

Subsequently, as shown in FIG. 28, the metal plating layer 132 and the seed layer 131 are polished by the CMP method so that the metal plating layer 132 is flush with the insulating layer 120 . As a result, conductive via 133 including seed layer 131 and metal plating layer 132 is formed in via hole 120x.

Thus, the first wiring structure 10 including the insulating layer 120, the conductive vias 133 in the insulating layer 120, and the electrode pads 112 connected to the conductive vias 133 is formed.

Next, as shown in FIG. 29, the second wiring structure 20 is formed in the same manner as in the first embodiment, and the adhesion layer 102 and the support 101 are separated from the etch stop layer 104 together with the release layer 103 . In this peeling, for example, the laminated structure 30 is cut at a portion closer to the wiring portion 100A than the opening portion 320x in the outer peripheral portion 100B. As a result, the interface between the release layer 103 and the etch stop layer 104 is exposed. Therefore, the release layer 103 can be easily separated from the etch stop layer 104 . The etch stop layer 104 is exposed as the peeling layer 103 is peeled off.

After peeling off the peeling layer 103, the adhesion layer 102, and the support 101, the etching stop layer 104 is removed (see FIG. 15) and subsequent processes are performed in the same manner as in the first embodiment. Thus, a wiring board can be manufactured.

In the third embodiment, when polishing the metal plating layer 132 and the seed layer 131, the side surface A of the release layer 103, the interface between the release layer 103 and the etch stop layer 104, and the interface between the release layer 103 and the adhesion layer 102 is covered by the metal plating layer 132 and the seed layer 131 in the opening 320x. Therefore, it is possible to suppress the generation of starting points of peeling. Therefore, although stress in the direction perpendicular to the thickness direction (in-plane direction) acts on the release layer 103 during polishing, the separation of the release layer 103 can be suppressed. Further, in the polishing by the CMP method, it is possible to suppress the polishing slurry from reaching the peeling layer 103 . In this respect as well, peeling of the peeling layer 103 can be suppressed.

The electrode pads 212 of the second embodiment may be applied to the third embodiment.

Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope of the claims. Modifications and substitutions can be made.

REFERENCE SIGNS LIST 10 first wiring structure 20 second wiring structure 30 laminated structure 40 buildup substrate 100 support substrate 101 support 102 adhesion layer 103 release layer 103A side surface 104 etch stop layer 105, 131 seed layer 111, 132 metal plating layer 112 electrode pad 120 insulating layer 121, 122, 123 resin layer 133 conductive via 320x opening

Claims (6)

preparing a support substrate comprising a support and a release layer on the support;
forming an insulating layer on the release layer;
forming a via hole in the insulating layer;
forming a first conductive layer in the via hole and on the insulating layer;
polishing the first conductive layer;
has
Between the step of providing the support substrate and the step of polishing the first conductive layer,
exposing a side surface of the release layer on the support;
forming a protective material covering the side surface of the release layer on the support;
has
exposing the side surface of the release layer between the step of preparing the support substrate and the step of forming the insulating layer;
In the step of forming the insulating layer, the side surface of the release layer is covered with a portion of the insulating layer as the protective material;
Between the step of preparing the support substrate and the step of exposing the side surface of the release layer,
forming a deposition mask having an opening on the release layer;
forming a second conductive layer in the opening to which the first conductive layer is connected;
has
A method of manufacturing a wiring substrate, comprising a step of removing the film-forming mask between the step of exposing the side surface of the release layer and the step of forming the insulating layer. 2. The method of manufacturing a wiring board according to claim 1, wherein the polishing of said first conductive layer is performed by a chemical mechanical polishing method. After the step of forming the first conductive layer,
3. The method of manufacturing a wiring board according to claim 1 , further comprising the step of forming a multilayer wiring connected to said first conductive layer on said insulating layer. After the step of forming the multilayer wiring,
peeling the release layer from the insulating layer;
4. The method of manufacturing a wiring board according to claim 3, further comprising the step of electrically connecting said first conductive layer to an electrode pad provided on said mounting board. a support;
a release layer on the support;
an insulating layer on the release layer;
a via hole formed in the insulating layer;
a first conductive layer in the via hole;
has
the side surface of the release layer is located inside the side surface of the support;
a protective material covering the side surface of the release layer on the support ;
the protective material is part of the insulating layer;
The upper surface of the support is
a first region covered with the release layer;
a second region exposed from the release layer;
has
The laminated structure , wherein the second region is closer to the lower surface of the support than the first region . the support has a first surface continuous with the first region and the second region;
6. The laminate structure of claim 5, wherein the protective material contacts the first surface and the second region.

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