JPH05243183A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05243183A
JPH05243183A JP4078493A JP7849392A JPH05243183A JP H05243183 A JPH05243183 A JP H05243183A JP 4078493 A JP4078493 A JP 4078493A JP 7849392 A JP7849392 A JP 7849392A JP H05243183 A JPH05243183 A JP H05243183A
Authority
JP
Japan
Prior art keywords
wafer
holder
1b
1c
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4078493A
Other languages
Japanese (ja)
Inventor
Yurie Inayoshi
由理恵 稲吉
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP4078493A priority Critical patent/JPH05243183A/en
Publication of JPH05243183A publication Critical patent/JPH05243183A/en
Application status is Granted legal-status Critical

Links

Abstract

PURPOSE:To restrain a plating film from varying in thickness by a method wherein a wafer is placed on a wafer holder composed of a ring-shaped insulator and conductive holder pieces electrically isolated from each other, and currents are separately fed to the holder pieces. CONSTITUTION:A wafer holder 1 is composed of holder pieces 1a, 1b, and 1c and a ring-shaped insulating 1d which electrically isolates the holder pieces 1a, 1b, and 1c. The holder pieces 1a, 1b, and 1c are separately connected to current power sources 9a, 9b, and 9c with copper wires 5 respectively. An Si wafer 2 is held by pawls 3, coming into close contact with the wafer holder 1, and dipped into Au plating solution in a treating tank 8. A counter electrode 6 is made to serve as a positive electrode, constant currents are fed to the holder pieces 1a, 1b, and 1c respectively to carry out Au plating. By this setup, a current can be evenly fed throughout the wafer, so that, a plating film can be prevented from varying in thickness throughout the surface of the wafer 2.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、半導体装置の製造方法に関し、特に半導体装置のAu電極等の電極を形成するための電解メッキ方法に関する。 The present invention relates relates to a method of manufacturing a semiconductor device, it relates to an electrolytic plating method, particularly for forming an electrode such as Au electrode of the semiconductor device.

【0002】 [0002]

【従来の技術】従来のAuメッキ方法を図3を参照して説明する。 BACKGROUND ART will be described with the conventional Au plating method with reference to FIG. 銅製のウェハホルダー10に、メッキを施すべきSiウェハ2をホルダー付属のポリテトラフルオロエチレン等の弗素樹脂製のつめ3により密着させる。 The copper wafer holder 10, the Si wafer 2 to be subjected to plating is brought into close contact with fluorine resin claws 3 of polytetrafluoroethylene or the like of the holder attached. ウェハホルダー10は定電流電源9に銅線5により接続されている。 Wafer holder 10 is connected by copper 5 to the constant-current power supply 9. また、ウェハホルダー10および銅線5は、 Further, the wafer holder 10 and copper 5,
ウェハが密着する部分を除いて弗素樹脂4でコーティングされている。 Except where the wafer is in close contact are coated with fluorine resin 4.

【0003】このSiウェハ2を保持したウェハホルダー10は、処理槽8内のAuメッキ液7中に浸漬される。 [0003] wafer holder 10 holding the Si wafer 2 is immersed in a Au plating solution 7 in the processing bath 8. Auメッキ液7中にはまた、定電流電源9と接続された白金製の対向電極6が、Siウェハ2と対向して配置されている。 During Au plating solution 7 The counter electrode 6 made of platinum is connected to the constant current source 9 is arranged to face the Si wafer 2.

【0004】この装置において、0.4A/dm 2 (1 [0004] In this device, 0.4A / dm 2 (1
dmは0.1m)の電流密度で電流を流すとウェハ2上にAuが約2000Å/minの速度でメッキされる。 dm is Au when a current flows on the wafer 2 at a current density of 0.1 m) is plated at a rate of about 2000 Å / min.

【0005】 [0005]

【発明が解決しようとする課題】上述した従来のメッキ方法では、ウェハ2の周辺部に電流が集中するため、著しいメッキ膜厚のばらつきが生じる。 In the above-described conventional plating method [0006] In order to concentrate the current in the peripheral portion of the wafer 2, the variation of significant plating film thickness occurs. 即ち、図4に示されるように、ウェハ周囲に膜厚1.2μmのAuメッキがなされた時、ウェハ中央での膜厚は0.6μmになる。 That is, as shown in FIG. 4, when the film thickness 1.2μm Au plated is made around the wafer, the thickness of the wafer center becomes 0.6 .mu.m.

【0006】 [0006]

【課題を解決するための手段】本発明の半導体装置の製造方法は、1乃至複数個のリング状絶縁体と、前記リング状絶縁体により互いに電気的に分離されている複数個の導電性のホルダー素片とから構成されるウェハホルダーにウェハを載置し、各ホルダー素片にそれぞれ独立に電流を供給しながら電解メッキを行うものである。 The method of manufacturing a semiconductor device of the present invention SUMMARY OF] includes one or a plurality of ring-shaped insulator, a plurality of conductive which is electrically isolated from each other by the ring-shaped insulator placing the wafer on the wafer holder consists of the holder segment, and performs electrolytic plating while supplying current independently into each holder segment.

【0007】 [0007]

【実施例】次に、本発明の実施例について図面を参照して説明する。 EXAMPLES will be described with reference to the accompanying drawings embodiments of the present invention. 図1の(a)は、本発明の一実施例において用いられるメッキ槽の概略断面図であり、図1の(b)は、本実施例において用いられるウェハホルダーの平面図である。 (A) of FIG. 1 is a schematic sectional view of a plating tank used in an embodiment of the present invention, shown in FIG. 1 (b) is a plan view of the wafer holder used in this embodiment. ウェハホルダー1は、銅製のホルダー素体1a、1b、1cとこれらを電気的に分離するリング状の絶縁体1dとから構成されている。 Wafer holder 1 is composed of a copper holder body 1a, 1b, 1c and these ring-shaped insulator 1d to electrically isolate.

【0008】各ホルダー素体1a、1b、1cは、それぞれ銅線5により別個の定電流電源9a、9b、9cと接続されている。 [0008] Each holder element 1a, 1b, 1c are connected by copper wires 5 each separate constant current source 9a, 9b, 9c and. ウェハホルダー1の下面表面を除く部分および銅線5のメッキ液に浸される部分は、弗素樹脂4でコーティングされている。 Part immersed in the plating solution of the partial and copper 5 except underside surface of the wafer holder 1 is coated with a fluorine resin 4. Siウェハ2をつめ3によりウェハホルダー1に密着・保持させ、処理槽8内のAuメッキ液7中に浸漬する。 By the Si wafer second 3 is adhered and held on the wafer holder 1, immersed in the Au plating solution 7 in the processing bath 8.

【0009】Auメッキ液7内には、白金製の対向電極6がSiウェハ2と対向する位置に配置されている。 [0009] Within the Au plating solution 7, the counter electrode 6 made of platinum is disposed at a position opposite to the Si wafer 2. 対向電極6は、各定電流電源9a、9b、9cに接続されている。 The counter electrode 6, the constant current source 9a, 9b, and is connected to 9c. 対向電極6を正極側として、定電流電源9a、 The counter electrode 6 as the positive electrode side, a constant current source 9a,
9b、9cにより各ホルダー素片1a、1b、1cに定電流を供給してAuメッキを行う。 9b, the holder segment 1a, 1b, the Au plating by supplying a constant current to 1c performed by 9c.

【0010】各ホルダー素片にそれぞれ0.4A/dm [0010] to each holder segment 0.4A / dm
2の電流密度で電流を供給してメッキを行ったときのウェハ上でのメッキ膜厚を図2に示す。 The plating film thickness on the wafer when performing plating by supplying current at a second current density is shown in FIG. 同図に示されるように、本実施例により、ウェハ全面においてメッキ膜厚を0.9〜1.1μmの範囲に収めることができた。 As shown in the figure, the present embodiment, it is possible to fit the plating thickness in the range of 0.9~1.1μm in the entire wafer surface.

【0011】もし、メッキ膜厚が同一ホルダー素片内でばらつくときには、そのホルダー素片をさらに分割するようにすればよい。 [0011] If, when the plated film thickness varies in the same holder segment may be to further divide the holder segment. また、ホルダー素片間において膜厚に差が生じる場合には、例えば膜厚の不足する部分のホルダー素片への定電流を増加させるようにすればよい。 Further, when the difference in the film thickness in the holder element pieces occurs, for example, it may be to increase the constant current to the holder segment of the portion of insufficient thickness.

【0012】上記実施例では、各ホルダー素片にDC定電流を供給していたが、これをパルス電流に置き換えることができる。 [0012] In the above embodiment, although not feed DC constant current to each holder segment can replace this with a pulse current. また、本発明はAuメッキ以外のメッキにも適用しうるものである。 Further, the present invention can be applied to plating other than Au plating.

【0013】 [0013]

【発明の効果】以上説明したように、本発明の半導体装置の製造方法は、リング状絶縁体とこれによって分離されたホルダー素片とからなるウェハホルダーにウェハを保持し、各ホルダー素片に独立して電流を供給しつつメッキを行うものであるので、本発明によれば、ウェハ全面に渡って均等に電流を供給することができ、メッキ膜厚の位置によるばらつきを抑制することができる。 As described above, according to the present invention, a method of manufacturing a semiconductor device of the present invention is to retain the wafer on the wafer holder comprising a holder segment separated by this and the ring-shaped insulator, each holder segment since independently performs a plating while supplying current, according to the present invention, can be supplied evenly current over the entire surface of the wafer, it is possible to suppress the variation due to position of the plating film thickness .

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例を説明するためのメッキ装置の概略断面図と本実施例に用いられるウェハホルダーの平面図。 1 is a schematic cross-sectional view and a plan view of a wafer holder used in this embodiment of the plating apparatus for explaining an embodiment of the present invention.

【図2】本実施例の効果を示すメッキ膜厚分布図。 [Figure 2] Plating thickness distribution chart showing the effect of the present embodiment.

【図3】従来例を説明するためのメッキ装置の概略断面図。 3 is a schematic cross-sectional view of a plating apparatus for explaining a conventional example.

【図4】従来例によって得られるメッキ膜厚分布図。 [4] Conventional examples plated film thickness distribution chart obtained.

【符号の説明】 DESCRIPTION OF SYMBOLS

1、10 ウェハホルダー 1a、1b、1c ホルダー素片 1d 絶縁体 2 Siウェハ 3 つめ 4 弗素樹脂 5 銅線 6 対向電極 7 Auメッキ液 8 処理槽 9、9a、9b、9c 定電流電源 1,10 wafer holder 1a, 1b, 1c holder segment 1d insulator 2 Si wafer third 4 fluororesin 5 copper wire 6 counter electrode 7 Au plating solution 8 processing tank 9, 9a, 9b, 9c constant current source

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 5識別記号 庁内整理番号 FI 技術表示箇所 // C25D 3/48 ────────────────────────────────────────────────── ─── front page continued (51) Int.Cl. 5 in identification symbol Agency Docket No. FI art display portion // C25D 3/48

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 1乃至複数個のリング状絶縁体と、前記リング状絶縁体により互いに電気的に分離されている複数個の導電性のホルダー素片とから構成されるウェハホルダーにウェハを載置し、各ホルダー素片にそれぞれ独立に電流を供給しながら電解メッキを行うことを特徴とする半導体装置の製造方法。 And 1. A 1 or a plurality of ring-shaped insulator, placing the wafer on the wafer holder consists of a plurality of conductive holder segments which are electrically isolated from each other by the ring-shaped insulator location and method of manufacturing a semiconductor device characterized by carrying out electrolytic plating while supplying current independently into each holder segment.
JP4078493A 1992-02-28 1992-02-28 Manufacture of semiconductor device Granted JPH05243183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4078493A JPH05243183A (en) 1992-02-28 1992-02-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4078493A JPH05243183A (en) 1992-02-28 1992-02-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05243183A true JPH05243183A (en) 1993-09-21

Family

ID=13663503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4078493A Granted JPH05243183A (en) 1992-02-28 1992-02-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05243183A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07173700A (en) * 1993-12-17 1995-07-11 Nec Corp Divided anode plating device and current value determining method
US5620581A (en) * 1995-11-29 1997-04-15 Aiwa Research And Development, Inc. Apparatus for electroplating metal films including a cathode ring, insulator ring and thief ring
WO2001014618A2 (en) * 1999-08-26 2001-03-01 Cvc Products, Inc. Apparatus and method for electroplating a material layer onto a wafer
US6837984B2 (en) 1998-07-09 2005-01-04 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
US7136173B2 (en) 1998-07-09 2006-11-14 Acm Research, Inc. Method and apparatus for end-point detection
JP2008028336A (en) * 2006-07-25 2008-02-07 Shinko Electric Ind Co Ltd Method of manufacturing electronic component

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07173700A (en) * 1993-12-17 1995-07-11 Nec Corp Divided anode plating device and current value determining method
US5620581A (en) * 1995-11-29 1997-04-15 Aiwa Research And Development, Inc. Apparatus for electroplating metal films including a cathode ring, insulator ring and thief ring
US5744019A (en) * 1995-11-29 1998-04-28 Aiwa Research And Development, Inc. Method for electroplating metal films including use a cathode ring insulator ring and thief ring
US6837984B2 (en) 1998-07-09 2005-01-04 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
US7136173B2 (en) 1998-07-09 2006-11-14 Acm Research, Inc. Method and apparatus for end-point detection
WO2001014618A2 (en) * 1999-08-26 2001-03-01 Cvc Products, Inc. Apparatus and method for electroplating a material layer onto a wafer
WO2001014618A3 (en) * 1999-08-26 2001-07-26 Cvc Products Inc Apparatus and method for electroplating a material layer onto a wafer
JP2008028336A (en) * 2006-07-25 2008-02-07 Shinko Electric Ind Co Ltd Method of manufacturing electronic component

Similar Documents

Publication Publication Date Title
US3536594A (en) Method and apparatus for rapid gold plating integrated circuit slices
KR100572433B1 (en) The program pulse electroplating method
US3880725A (en) Predetermined thickness profiles through electroplating
EP0458863B1 (en) Method and apparatus for manufacturing interconnects with fine lines and spacing
CA1206436A (en) Rotary electroplating cell with controlled current distribution
US6210554B1 (en) Method of plating semiconductor wafer and plated semiconductor wafer
US5443707A (en) Apparatus for electroplating the main surface of a substrate
US6179983B1 (en) Method and apparatus for treating surface including virtual anode
US5776327A (en) Method and apparatus using an anode basket for electroplating a workpiece
US4944850A (en) Tape automated bonded (tab) circuit and method for making the same
US4466864A (en) Methods of and apparatus for electroplating preselected surface regions of electrical articles
JP4095896B2 (en) Iontophoretic electrode having improved current distribution
US4624749A (en) Electrodeposition of submicrometer metallic interconnect for integrated circuits
US5227041A (en) Dry contact electroplating apparatus
US5876580A (en) Rough electrical contact surface
US5395508A (en) Apparatus for the electrolytic deposition of a metal on a weakly conductive flexible substrate electrolytic deposition process and product obtained by this process
JPH05132799A (en) Electroplating method and device therefor
EP0806834A3 (en) Method and apparatus for balancing an electrostatic force produced by an electrostatic chuck
US4367123A (en) Precision spot plating process and apparatus
KR100577662B1 (en) Method and apparatus for controlling local current to achieve uniform plating thickness
US6093291A (en) Electroplating apparatus
CN1551931A (en) Method and apparatus for controlling thickness uniformity of electroplated layers
US2429222A (en) Method of making contact wires
CA1070635A (en) Method and apparatus for selectively electroplating an area of a surface
US2793420A (en) Electrical contacts to silicon

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 8

Free format text: PAYMENT UNTIL: 20081027

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 9

Free format text: PAYMENT UNTIL: 20091027

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091027

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 10

Free format text: PAYMENT UNTIL: 20101027

LAPS Cancellation because of no payment of annual fees