JPH05243183A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05243183A
JPH05243183A JP4078493A JP7849392A JPH05243183A JP H05243183 A JPH05243183 A JP H05243183A JP 4078493 A JP4078493 A JP 4078493A JP 7849392 A JP7849392 A JP 7849392A JP H05243183 A JPH05243183 A JP H05243183A
Authority
JP
Japan
Prior art keywords
wafer
holder
plating
pieces
holder pieces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4078493A
Other languages
Japanese (ja)
Inventor
Yurie Inayoshi
由理恵 稲吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4078493A priority Critical patent/JPH05243183A/en
Publication of JPH05243183A publication Critical patent/JPH05243183A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electroplating And Plating Baths Therefor (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To restrain a plating film from varying in thickness by a method wherein a wafer is placed on a wafer holder composed of a ring-shaped insulator and conductive holder pieces electrically isolated from each other, and currents are separately fed to the holder pieces. CONSTITUTION:A wafer holder 1 is composed of holder pieces 1a, 1b, and 1c and a ring-shaped insulating 1d which electrically isolates the holder pieces 1a, 1b, and 1c. The holder pieces 1a, 1b, and 1c are separately connected to current power sources 9a, 9b, and 9c with copper wires 5 respectively. An Si wafer 2 is held by pawls 3, coming into close contact with the wafer holder 1, and dipped into Au plating solution in a treating tank 8. A counter electrode 6 is made to serve as a positive electrode, constant currents are fed to the holder pieces 1a, 1b, and 1c respectively to carry out Au plating. By this setup, a current can be evenly fed throughout the wafer, so that, a plating film can be prevented from varying in thickness throughout the surface of the wafer 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に半導体装置のAu電極等の電極を形成する
ための電解メッキ方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an electrolytic plating method for forming electrodes such as Au electrodes of a semiconductor device.

【0002】[0002]

【従来の技術】従来のAuメッキ方法を図3を参照して
説明する。銅製のウェハホルダー10に、メッキを施す
べきSiウェハ2をホルダー付属のポリテトラフルオロ
エチレン等の弗素樹脂製のつめ3により密着させる。ウ
ェハホルダー10は定電流電源9に銅線5により接続さ
れている。また、ウェハホルダー10および銅線5は、
ウェハが密着する部分を除いて弗素樹脂4でコーティン
グされている。
2. Description of the Related Art A conventional Au plating method will be described with reference to FIG. The Si wafer 2 to be plated is brought into close contact with the copper wafer holder 10 by the pawl 3 made of a fluorine resin such as polytetrafluoroethylene attached to the holder. The wafer holder 10 is connected to the constant current power source 9 by the copper wire 5. Further, the wafer holder 10 and the copper wire 5 are
Except for the part where the wafer is in close contact, it is coated with a fluororesin 4.

【0003】このSiウェハ2を保持したウェハホルダ
ー10は、処理槽8内のAuメッキ液7中に浸漬され
る。Auメッキ液7中にはまた、定電流電源9と接続さ
れた白金製の対向電極6が、Siウェハ2と対向して配
置されている。
The wafer holder 10 holding the Si wafer 2 is immersed in the Au plating solution 7 in the processing bath 8. In the Au plating liquid 7, a counter electrode 6 made of platinum and connected to a constant current power source 9 is arranged so as to face the Si wafer 2.

【0004】この装置において、0.4A/dm2 (1
dmは0.1m)の電流密度で電流を流すとウェハ2上
にAuが約2000Å/minの速度でメッキされる。
In this device, 0.4 A / dm 2 (1
When a current is applied at a current density of 0.1 m), Au is plated on the wafer 2 at a rate of about 2000 Å / min.

【0005】[0005]

【発明が解決しようとする課題】上述した従来のメッキ
方法では、ウェハ2の周辺部に電流が集中するため、著
しいメッキ膜厚のばらつきが生じる。即ち、図4に示さ
れるように、ウェハ周囲に膜厚1.2μmのAuメッキ
がなされた時、ウェハ中央での膜厚は0.6μmにな
る。
In the conventional plating method described above, the current concentrates on the peripheral portion of the wafer 2, so that the plating film thickness varies significantly. That is, as shown in FIG. 4, when Au plating having a film thickness of 1.2 μm is applied around the wafer, the film thickness at the center of the wafer becomes 0.6 μm.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、1乃至複数個のリング状絶縁体と、前記リン
グ状絶縁体により互いに電気的に分離されている複数個
の導電性のホルダー素片とから構成されるウェハホルダ
ーにウェハを載置し、各ホルダー素片にそれぞれ独立に
電流を供給しながら電解メッキを行うものである。
According to the method of manufacturing a semiconductor device of the present invention, one to a plurality of ring-shaped insulators and a plurality of conductive layers electrically isolated from each other by the ring-shaped insulators. A wafer is placed on a wafer holder composed of holder pieces, and electrolytic plating is performed while supplying current to each holder piece independently.

【0007】[0007]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1の(a)は、本発明の一実施例におい
て用いられるメッキ槽の概略断面図であり、図1の
(b)は、本実施例において用いられるウェハホルダー
の平面図である。ウェハホルダー1は、銅製のホルダー
素体1a、1b、1cとこれらを電気的に分離するリン
グ状の絶縁体1dとから構成されている。
Embodiments of the present invention will now be described with reference to the drawings. 1A is a schematic cross-sectional view of a plating bath used in one embodiment of the present invention, and FIG. 1B is a plan view of a wafer holder used in this embodiment. The wafer holder 1 is composed of copper holder bodies 1a, 1b, 1c and a ring-shaped insulator 1d that electrically separates them.

【0008】各ホルダー素体1a、1b、1cは、それ
ぞれ銅線5により別個の定電流電源9a、9b、9cと
接続されている。ウェハホルダー1の下面表面を除く部
分および銅線5のメッキ液に浸される部分は、弗素樹脂
4でコーティングされている。Siウェハ2をつめ3に
よりウェハホルダー1に密着・保持させ、処理槽8内の
Auメッキ液7中に浸漬する。
Each holder element body 1a, 1b, 1c is connected to a separate constant current power source 9a, 9b, 9c by a copper wire 5, respectively. The portion of the wafer holder 1 excluding the lower surface and the portion of the copper wire 5 which is immersed in the plating solution are coated with a fluororesin 4. The Si wafer 2 is brought into close contact with and held by the wafer holder 1 by the pawl 3, and is immersed in the Au plating solution 7 in the processing bath 8.

【0009】Auメッキ液7内には、白金製の対向電極
6がSiウェハ2と対向する位置に配置されている。対
向電極6は、各定電流電源9a、9b、9cに接続され
ている。対向電極6を正極側として、定電流電源9a、
9b、9cにより各ホルダー素片1a、1b、1cに定
電流を供給してAuメッキを行う。
In the Au plating solution 7, a counter electrode 6 made of platinum is arranged at a position facing the Si wafer 2. The counter electrode 6 is connected to each constant current power supply 9a, 9b, 9c. With the counter electrode 6 as the positive electrode side, a constant current power source 9a,
A constant current is supplied to each holder element 1a, 1b, 1c by 9b, 9c to perform Au plating.

【0010】各ホルダー素片にそれぞれ0.4A/dm
2 の電流密度で電流を供給してメッキを行ったときのウ
ェハ上でのメッキ膜厚を図2に示す。同図に示されるよ
うに、本実施例により、ウェハ全面においてメッキ膜厚
を0.9〜1.1μmの範囲に収めることができた。
0.4 A / dm for each holder element
The plating film thickness on the wafer when performing plating by supplying current at a second current density is shown in FIG. As shown in the figure, according to this example, the plating film thickness could be set within the range of 0.9 to 1.1 μm on the entire surface of the wafer.

【0011】もし、メッキ膜厚が同一ホルダー素片内で
ばらつくときには、そのホルダー素片をさらに分割する
ようにすればよい。また、ホルダー素片間において膜厚
に差が生じる場合には、例えば膜厚の不足する部分のホ
ルダー素片への定電流を増加させるようにすればよい。
If the plating film thickness varies within the same holder piece, the holder piece may be further divided. Further, when the film thickness varies between the holder pieces, for example, the constant current to the holder piece in the portion where the film thickness is insufficient may be increased.

【0012】上記実施例では、各ホルダー素片にDC定
電流を供給していたが、これをパルス電流に置き換える
ことができる。また、本発明はAuメッキ以外のメッキ
にも適用しうるものである。
In the above embodiment, a DC constant current was supplied to each holder element, but this can be replaced with a pulse current. Further, the present invention can be applied to plating other than Au plating.

【0013】[0013]

【発明の効果】以上説明したように、本発明の半導体装
置の製造方法は、リング状絶縁体とこれによって分離さ
れたホルダー素片とからなるウェハホルダーにウェハを
保持し、各ホルダー素片に独立して電流を供給しつつメ
ッキを行うものであるので、本発明によれば、ウェハ全
面に渡って均等に電流を供給することができ、メッキ膜
厚の位置によるばらつきを抑制することができる。
As described above, according to the method of manufacturing a semiconductor device of the present invention, a wafer is held in a wafer holder composed of a ring-shaped insulator and holder pieces separated by the insulator, and each holder piece is held. Since the plating is performed while supplying the current independently, according to the present invention, the current can be uniformly supplied over the entire surface of the wafer and the variation in the plating film thickness due to the position can be suppressed. .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明するためのメッキ装置
の概略断面図と本実施例に用いられるウェハホルダーの
平面図。
FIG. 1 is a schematic cross-sectional view of a plating apparatus for explaining an embodiment of the present invention and a plan view of a wafer holder used in this embodiment.

【図2】本実施例の効果を示すメッキ膜厚分布図。FIG. 2 is a plating film thickness distribution diagram showing the effect of the present embodiment.

【図3】従来例を説明するためのメッキ装置の概略断面
図。
FIG. 3 is a schematic sectional view of a plating apparatus for explaining a conventional example.

【図4】従来例によって得られるメッキ膜厚分布図。FIG. 4 is a plating film thickness distribution diagram obtained by a conventional example.

【符号の説明】[Explanation of symbols]

1、10 ウェハホルダー 1a、1b、1c ホルダー素片 1d 絶縁体 2 Siウェハ 3 つめ 4 弗素樹脂 5 銅線 6 対向電極 7 Auメッキ液 8 処理槽 9、9a、9b、9c 定電流電源 1, 10 Wafer holder 1a, 1b, 1c Holder piece 1d Insulator 2 Si wafer 3rd 4 Fluorine resin 5 Copper wire 6 Counter electrode 7 Au plating solution 8 Treatment tank 9, 9a, 9b, 9c Constant current power supply

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 // C25D 3/48 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location // C25D 3/48

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 1乃至複数個のリング状絶縁体と、前記
リング状絶縁体により互いに電気的に分離されている複
数個の導電性のホルダー素片とから構成されるウェハホ
ルダーにウェハを載置し、各ホルダー素片にそれぞれ独
立に電流を供給しながら電解メッキを行うことを特徴と
する半導体装置の製造方法。
1. A wafer holder is mounted on a wafer holder including one to a plurality of ring-shaped insulators and a plurality of conductive holder pieces electrically separated from each other by the ring-shaped insulators. And a method of manufacturing a semiconductor device, wherein electrolytic plating is performed while supplying electric current to each holder piece independently.
JP4078493A 1992-02-28 1992-02-28 Manufacture of semiconductor device Pending JPH05243183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4078493A JPH05243183A (en) 1992-02-28 1992-02-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4078493A JPH05243183A (en) 1992-02-28 1992-02-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05243183A true JPH05243183A (en) 1993-09-21

Family

ID=13663503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4078493A Pending JPH05243183A (en) 1992-02-28 1992-02-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05243183A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07173700A (en) * 1993-12-17 1995-07-11 Nec Corp Divided anode plating device and current value determining method
US5620581A (en) * 1995-11-29 1997-04-15 Aiwa Research And Development, Inc. Apparatus for electroplating metal films including a cathode ring, insulator ring and thief ring
WO2001014618A2 (en) * 1999-08-26 2001-03-01 Cvc Products, Inc. Apparatus and method for electroplating a material layer onto a wafer
US6837984B2 (en) 1998-07-09 2005-01-04 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
US7136173B2 (en) 1998-07-09 2006-11-14 Acm Research, Inc. Method and apparatus for end-point detection
JP2008028336A (en) * 2006-07-25 2008-02-07 Shinko Electric Ind Co Ltd Method of manufacturing electronic component

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07173700A (en) * 1993-12-17 1995-07-11 Nec Corp Divided anode plating device and current value determining method
US5620581A (en) * 1995-11-29 1997-04-15 Aiwa Research And Development, Inc. Apparatus for electroplating metal films including a cathode ring, insulator ring and thief ring
US5744019A (en) * 1995-11-29 1998-04-28 Aiwa Research And Development, Inc. Method for electroplating metal films including use a cathode ring insulator ring and thief ring
US6837984B2 (en) 1998-07-09 2005-01-04 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
US7136173B2 (en) 1998-07-09 2006-11-14 Acm Research, Inc. Method and apparatus for end-point detection
WO2001014618A2 (en) * 1999-08-26 2001-03-01 Cvc Products, Inc. Apparatus and method for electroplating a material layer onto a wafer
WO2001014618A3 (en) * 1999-08-26 2001-07-26 Cvc Products Inc Apparatus and method for electroplating a material layer onto a wafer
JP2008028336A (en) * 2006-07-25 2008-02-07 Shinko Electric Ind Co Ltd Method of manufacturing electronic component

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