US20040099534A1 - Method and apparatus for electroplating a semiconductor wafer - Google Patents

Method and apparatus for electroplating a semiconductor wafer Download PDF

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Publication number
US20040099534A1
US20040099534A1 US10306641 US30664102A US2004099534A1 US 20040099534 A1 US20040099534 A1 US 20040099534A1 US 10306641 US10306641 US 10306641 US 30664102 A US30664102 A US 30664102A US 2004099534 A1 US2004099534 A1 US 2004099534A1
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wafer
surface
anode
apparatus
electrode
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US10306641
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James Powers
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Intel Corp
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Intel Corp
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/10Electrodes, e.g. composition, counter electrode
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for plating wafers, e.g. semiconductors, solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/10Electrodes, e.g. composition, counter electrode
    • C25D17/12Shape or form
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors coated first with a seed layer, e.g. for filling vias
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

Abstract

A method, apparatus and anode for plating copper or other metals onto a barrier or seed layer of a wafer surface is described. A copper layer of uniform thickness is plated on the surface by, for instance, maintaining a constant current density between the anode and wafer surface. Several configurations of anodes are described for obtaining the constant current density.

Description

    FIELD OF THE INVENTION
  • This invention relates to the field of electroplating metals onto a semiconductor wafer. [0001]
  • PRIOR ART
  • In the fabrication of integrated circuits, metal layers are often formed on semiconductor wafers as part of a process for forming conductive lines. More recently, the electroplating of copper is used in a damascene process because of the high conductivity of copper when compared, for instance, to aluminum. [0002]
  • As shown in FIG. 1, in the process for electroplating copper, a copper electrode (an anode) [0003] 10 is disposed above a surface 14 of a semiconductor wafer 13. A second electrode 12 is clamped about the outer edge of the wafer 13 and provides a conductive path to the first electrode through a barrier layer or seed layer formed on surface 14. When a potential 16 is applied between the electrodes 10 and 12, current flows between the electrodes. When this occurs, copper moves from the plating solution to the surface 14, thereby plating the surface 14 with copper.
  • The deposition rate of copper in a given area on the surface [0004] 14 is directly related to the current density, that is, the more current the more copper is deposited. The seed layer or barrier layer on the surface 14 has a relatively high resistivity. As a result, the current path between electrode 10 to electrode 12 follows paths of different resistance depending upon where on the wafer surface the current enters the barrier or seed layer as it moves toward the electrode 12. The path, for example, that includes the center of the wafer has more resistance because the current must travel the full radius of the wafer. In contrast, the path nearer the electrode 12 and electrode 10 has a relatively short path, and consequently, encounters a lower resistance. For this reason, the current flow between the anode and the wafer surface 14 is not uniform across the surface of the wafer. Less current flows in the center of the wafer and more current flows toward the periphery of the wafer per unit area. This causes the thickness of the copper layer to be thicker near electrode 12 and thinner in the center of the wafer.
  • The generally concave shaped copper layer formed on the wafer [0005] 13 is made uniform by polishing the layer using, for instance, chemical-mechanical polishing (CMP). There are numerous disadvantages with depositing a non-uniform layer and polishing it, some of these disadvantages are discussed later.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic of a prior art electroplating apparatus. [0006]
  • FIG. 2 is a schematic of an electroplating apparatus in accordance with one embodiment of the present invention. [0007]
  • FIG. 2A is a plan view of a segment of the anode of FIG. 2. [0008]
  • FIG. 2B is a plan view of a segment of an alternate embodiment of an anode. [0009]
  • FIG. 3 is a schematic of another embodiment of an electroplating apparatus. [0010]
  • FIG. 4 is a schematic of yet another embodiment of an electroplating apparatus in accordance with the present invention. [0011]
  • DETAILED DESCRIPTION
  • Electroplating methods, apparatuses, and anodes, particularly for use in forming a metal layer on a semiconductor wafer are described. The methods, apparatuses, and anodes are described for the formation of a copper layer in a damascene process. It will be apparent that the present invention may be used for forming other layers. Moreover, in the following description, numerous specific details known in the art, such as for the formation of barrier and seed layers in a damascene process, and electroplating chemistry are not set forth in detail in order not to obscure the present invention. [0012]
  • With some of the methods, apparatuses, and anodes described below, a relatively uniform current density is achieved between the anode of the electroplating apparatus and the surface of the semiconductor wafer upon which the layer is plated. Several anode configurations are discussed below for providing this uniform current density. This uniform current provides a layer of relatively uniform thickness. Thus, for instance, in the formation of a copper layer in a damascene process, less polishing is required to provide a flat surface and to define the inlaid conductors. This more readily allows the use of mechanically weaker, lower k dielectrics. The need for a hard mask may be eliminated in some processes because of the uniform layer. Less polishing is needed which shortens the processing time. Other advantages will be apparent to one skilled in the art. [0013]
  • Referring first to FIG. 2, a wafer [0014] 20 clamped within a first electrode 22 is illustrated. The clamp 22 of FIG. 2 may be similar to the clamp 12, shown in the prior art apparatus of FIG. 1. A layer is formed on the surface 21 of the wafer, such as a copper layer.
  • While not specifically shown in FIG. 2, prior to placing the wafer [0015] 20 in the electrode 22, a barrier layer or seed layer is formed on the surface 21, particularly where a damascene interconnect structure for an integrated circuit is formed. The barrier layer is often a tantalum or TaN layer used to prevent the subsequently formed copper from diffusing into the interlayer dielectric (ILD) and into other regions of the integrated circuit. In some instances, a seed layer is formed on the barrier layer, such as by sputtering copper, to increase the conductivity of the barrier layer.
  • The barrier layer, even with the seed layer, are not particularly conductive. Consequently, as described above, there is a significant voltage drop associated with the current flow between the first electrode [0016] 22 and the anode 26 as a function of the distance the current must travel.
  • The anode [0017] 26 of FIG. 2 comprises a generally disc-like member having a pair of parallel surfaces, one surface of which faces the surface 21 of wafer 20, as illustrated in FIG. 2. A plurality of rods, such as rod 27, are disposed between the faces of the anode 26 and are generally perpendicular to the surface 21 of the wafer 20. The rods are all of the same diameter for the illustrated embodiment. For copper plating, these rods are fabricated from copper. The body of the anode 26 may be formed from an insulative member such as Teflon, with the rods 27 inserted into the Teflon member.
  • In one embodiment, the density of the rods is greater at the center of the anode [0018] 26 than it is at a distance away from the center. For instance, as shown in FIGS. 2 and 2A, the rods indicated by the bracket 28 are more densely disposed than those indicated by the bracket 29. Any number of different densities may be used even though in FIG. 2, only three different densities are shown.
  • The rods are coupled to a source of potential with respect to the clamp/electrode [0019] 22. In FIG. 2, the rods of each density are coupled to a different potential. The different potentials provide an additional parameter that can be varied to achieve a uniform current density. For instance, the rods 28 are coupled to a potential V3 and the rods 29 are coupled to a potential V4. To provide a more uniform current flow, V3 may be a higher potential than V4. In FIG. 2, five different potentials are illustrated. Again, any number of different potentials may be used. Moreover, the potentials V1 and V5 may be equal to one another, and similarly, the potentials V2 and V4 may be equal to one another. These voltages such as V1 and V5 are illustrated as being different from one another. Different potentials may be used to balance the currents at different regions of the wafer surface equidistant from the center.
  • The anode [0020] 26 of FIG. 2 may also be used where all the rods are coupled to the same potential since the different densities of the conducting rods will tend to cause a uniform current density across the surface 21 of wafer 20.
  • In another embodiment, the rods may be of uniform density within the anode [0021] 26 and the different voltages shown in FIG. 2 may be used to achieve the uniform current density between the anode and the wafer surface 21. The same result can be achieved by varying the diameter of the rods. For instance, a higher “density” of rods can be obtained by increasing the diameter of the rods in one region when compared to other regions of the anode.
  • In yet another embodiment shown in FIG. 2B, rather than rods, annular, ring-like conductive elements [0022] 33 fabricated from, for instance copper, may be used for the anode 30. The elements are separated from one another by annular shaped Teflon members 32, as an example. The annular conductive elements may have a uniform density or may have a greater density towards the center of the electrode similar to the dispersal shown for the rods of FIG. 2. For the embodiment of FIG. 2B, the conductive rings 33 are uniformly spaced. A uniform current density across the surface of the wafer is obtained by using different voltages. The rings closer to the center of the anode 30 receive a higher potential than the potential applied to the rings with a larger diameter.
  • For all the embodiments, including the prior art, a reduction reaction occurs at the wafer and an oxidation reaction occurs at the anode. The wafer is negative relative to the anode and the Cu[0023] +2 ions in the plating solution, in which the electrode and wafer are submerged, are attracted to the wafer surface.
  • In the embodiment of FIG. 3, the anode [0024] 36 has a lenticular shape, more specifically, it has a convex surface facing the surface 35 of the wafer 34. When a potential is applied between the clamping electrode 38 and the copper electrode/anode 36, the voltage gradient between the wafer 34 and the anode is greater at the center of the wafer than at distances on the surface 35 spaced apart from the center. This compensates for the fact that there is more resistance between the electrodes at the wafer center. The shape of the anode 35 is selected to provide a uniform current density between the surface 35 and the electrode 36. Again as mentioned, this provides a uniform thickness of a layer plated onto surface 35.
  • In the embodiment of FIG. 4, a wafer [0025] 41 is again held by an electrode/clamp 52. This time, however, the surface 41 that is to be plated is facing downward for the illustrated embodiment. A volume 50 is defined by, for instance, a cylindrical cell 42 having an inlet 52 and an outlet 53. An anode, such as a copper electrode 51, is disposed within the volume 50. A voltage is applied between the anode 51 and the electrode 52. The cylindrical cell 42 is moved relative to the surface 41 such that the outlet 53 can be, in effect, swept over the entire surface 41 of the wafer 40.
  • The cell [0026] 42 is filled with a plating solution. In practice, while not illustrated, the outlet 53 is a relatively short distance from the surface 41. Enough space is provided to allow the plating fluid to escape from a gap between the surface 41 and the outlet 53, as shown by the arrows. The plating solution first flows upward and then escapes through the gap between the cell and the wafer surface 41. Once the liquid has escaped the cell, it drains downward and away from the surface of the wafer. Consequently, only a fraction of the wafer surface is exposed to the electroplating solution at any given time.
  • The entire surface [0027] 41 can be electroplated by moving the cell relative to the surface 41. The anode voltage 60 is varied as the electroplating cell is moved. More voltage is applied near the center region than at the region near the electrode 52. This voltage variation provides a constant current density, and consequently, a constant plating rate. This results in a layer of uniform thickness.
  • Alternatively, the voltage [0028] 60 may remain constant and the rate at which the cell 40 is moved can be varied. For instance, the cell can be moved at a slower rate near the center of the wafer than at the periphery of the wafer. This again allows for a layer of uniform thickness since the plating rate at the center will be slower than at the periphery because of the added resistance at the center from the barrier or seed layer. A combination of the varied voltages and varied rate of movement can be used.
  • Thus, the method of the present invention is to provide an anode that results in a uniform layer being formed on a wafer surface. In some cases, as shown above, this is achieved by having a greater voltage drop between the anode and wafer surface at the peripheral regions of the surface. For instance, this occurs with the anode of FIG. 3. In other instances, more sources of current are provided near the center of the wafer than at the periphery, such as shown in FIG. 2. A uniform current density is also achieved in some embodiments by having different voltages applied to different conductive elements in the anode, again to provide a uniform current density between the wafer surface and anode. In the embodiment of FIG. 4, the uniform layer thickness is obtained by moving an anode and either changing the rate of movement and/or the voltage applied to the anode as it is moved. [0029]

Claims (24)

    What is claimed is:
  1. 1. A method for electroplating a wafer comprising:
    connecting a first electrode on the periphery of a wafer to provide an electrical path to a surface of the wafer; and
    applying a potential with respect to the first electrode to a second electrode disposed adjacent to the surface of the wafer, such that the potential between the second electrode and the surface of the wafer varies across the surface of the wafer.
  2. 2. The method of claim 1, wherein the variation results in a substantially uniform current density between the second electrode and the surface of the wafer.
  3. 3. The method of claim 2, wherein the second electrode comprises copper.
  4. 4. The method of claim 3, including forming a barrier layer or seed layer on the surface of the wafer before connecting the first electrode to the wafer.
  5. 5. A method for electroplating a semiconductor wafer comprising:
    applying at least one potential to an anode disposed adjacent to a surface of the wafer such that the current flow between the surface of the wafer and the anode is substantially uniform over the surface of the wafer; and
    forming a layer of relatively uniform thickness on the surface of the wafer as a result of the uniform current flow.
  6. 6. The method of claim 5, including forming a barrier layer on the surface of the wafer prior to the applying of at least one potential to the anode.
  7. 7. The method of claim 5, including forming a seed layer on the surface of the wafer prior to the applying of at least one potential to the anode.
  8. 8. The method of claim 5, wherein the layer includes copper.
  9. 9. The method of claim 5, wherein during the forming of the layer, the voltage drop between the anode and the surface of the wafer is greater at the center of the wafer than it is at distances away from the center.
  10. 10. An apparatus for electroplating a wafer comprising:
    a conductive clamp for engaging the periphery of a wafer; and
    an anode disposed above the wafer, comprising a plurality of conductive elements disposed in an insulative member, the conductive elements being coupled to at least one source of potential.
  11. 11. The apparatus of claim 10, wherein the conductive elements comprise a plurality of rods having a uniform density in the insulative member.
  12. 12. The apparatus of claim 10, wherein the conductive elements comprise a plurality of rods having a higher density in a center of the anode when compared to a distance away from the center of the anode.
  13. 13. The apparatus of claim 10, wherein the conductive elements include a plurality of concentric, annular members.
  14. 14. The apparatus of claim 10, wherein a plurality of voltages are applied to the conductive elements with a higher voltage being applied to conductive elements disposed at a center of the anode, when compared to conductive elements disposed at a distance away from the center of the anode.
  15. 15. The apparatus of claim 10, wherein the conductive elements comprise copper.
  16. 16. The apparatus of claim 11, wherein the conductive elements comprise copper.
  17. 17. The apparatus of claim 12, wherein the conductive elements comprise copper.
  18. 18. The apparatus of claim 13, wherein the conductive elements comprise copper.
  19. 19. The apparatus of claim 14, wherein the conductive elements comprise copper.
  20. 20. An apparatus for electroplating a wafer comprising:
    a conductive clamp disposed about the periphery of the electrode,
    a lenticular shaped anode disposed above a surface of the wafer such that the anode is closer to the wafer at a center of the wafer when compared to the periphery of the wafer.
  21. 21. The apparatus of claim 20,wherein the anode is copper.
  22. 22. An apparatus for electroplating a wafer comprising:
    an electrode disposed about the periphery of the wafer;
    a cell having an inlet and an outlet facing a surface of the wafer, the cell carrying an electroplating fluid and being movable such that the outlet of the cell, sweeps over substantially the entire surface of the wafer;
    an anode disposed within the cell; and
    a source of potential applied between the electrode and the anode.
  23. 23. The apparatus of claim 22, wherein the source of potential is varied as the cell moves.
  24. 24. The apparatus of claim 23, wherein the rate at which the cell moves is varied.
US10306641 2002-11-27 2002-11-27 Method and apparatus for electroplating a semiconductor wafer Abandoned US20040099534A1 (en)

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US20100089760A1 (en) * 2006-03-27 2010-04-15 Yuefeng Luo Fabrication of topical stopper on head gasket by active matrix electrochemical deposition
CN102383174A (en) * 2010-09-01 2012-03-21 中芯国际集成电路制造(上海)有限公司 Electroplating anode
US20140216940A1 (en) * 2011-06-24 2014-08-07 Acm Research (Shanghai) Inc. Methods and apparatus for uniformly metallization on substrates
CN107034506A (en) * 2017-03-31 2017-08-11 北京半导体专用设备研究所(中国电子科技集团公司第四十五研究所) Wafer electroplating device and method

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US6402923B1 (en) * 2000-03-27 2002-06-11 Novellus Systems Inc Method and apparatus for uniform electroplating of integrated circuits using a variable field shaping element

Cited By (15)

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US9441309B2 (en) 2005-11-18 2016-09-13 Luxembourg Institute Of Science And Technology (List) Electrode and method of forming the master electrode
US20090071837A1 (en) * 2005-11-18 2009-03-19 Mikael Fredenberg Master electrode and method of forming it
US20090205967A1 (en) * 2005-11-18 2009-08-20 Replisaurus Technologies Ab Method of forming a multilayer structure
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WO2007058605A1 (en) * 2005-11-18 2007-05-24 Replisaurus Technologies Ab Master electrode and method of forming it
US9163321B2 (en) * 2006-03-27 2015-10-20 Federal-Mogul World Wide, Inc. Fabrication of topical stopper on head gasket by active matrix electrochemical deposition
US20100089760A1 (en) * 2006-03-27 2010-04-15 Yuefeng Luo Fabrication of topical stopper on head gasket by active matrix electrochemical deposition
CN102383174A (en) * 2010-09-01 2012-03-21 中芯国际集成电路制造(上海)有限公司 Electroplating anode
US20140216940A1 (en) * 2011-06-24 2014-08-07 Acm Research (Shanghai) Inc. Methods and apparatus for uniformly metallization on substrates
US9666426B2 (en) * 2011-06-24 2017-05-30 Acm Research (Shanghai) Inc. Methods and apparatus for uniformly metallization on substrates
CN107034506A (en) * 2017-03-31 2017-08-11 北京半导体专用设备研究所(中国电子科技集团公司第四十五研究所) Wafer electroplating device and method

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