US20050145499A1 - Plating of a thin metal seed layer - Google Patents

Plating of a thin metal seed layer Download PDF

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US20050145499A1
US20050145499A1 US11072473 US7247305A US2005145499A1 US 20050145499 A1 US20050145499 A1 US 20050145499A1 US 11072473 US11072473 US 11072473 US 7247305 A US7247305 A US 7247305A US 2005145499 A1 US2005145499 A1 US 2005145499A1
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substrate
plating
metal layer
method
anode
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US11072473
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Nicolay Kovarsky
You Wang
John Dukovic
Ivan Rodriguez
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Applied Materials Inc
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Applied Materials Inc
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/10Electrodes, e.g. composition, counter electrode
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18Electroplating using modulated, pulsed or reversing current
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors coated first with a seed layer, e.g. for filling vias

Abstract

A method and apparatus for plating a metal layer onto a substrate is provided. The plating apparatus includes two or more segments of an anode and an auxiliary electrode. The plating method includes a first stage of plating a thin metal seed uniformly in the center of the substrate and near the edges of the substrate before metal gap filling and bulk metal plating are performed. The thin metal seed is plated on the substrate surface by applying a current pulse provided by a first power supply and a second power supply which are in electrical communication in reverse polarity with one segment of the anode and the auxiliary electrode. Thereafter, gap filling of features is performed by applying a second current pulse where current is provided to all segments of the anode.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of U.S. provisional patent application Ser. No. 60/579,129, entitled “Method Of Barrier Layer Surface Treatment To Enable Direct Copper Plating”, filed on Jun. 10, 2004 and claims benefit of U.S. provisional patent application Ser. No. 60/621,215 (AMAT/9201L), filed on Oct. 21, 2004, entitled “Plating Chemistry And Method Of Single-Step Electroplating Of Copper On A Barrier Metal”. This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 10/880,103 (AMAT/8556), titled “Multiple-Step Electrodeposition Process For Direct Copper Plating On Barrier Metals”, filed on Jun. 28, 2004; co-pending U.S. patent application Ser. No. 10/616,097 (AMAT/8241), titled “Multiple-Step Electrodeposition Process For Direct Copper Plating On Barrier Metals”, filed on Jul. 8, 2003; co-pending U.S. patent application Ser. No. 10/664,277 (AMAT/7735), titled “Insoluble Anode with an Auxiliary Electrode”, filed on Sep. 17, 2003; co-pending U.S. patent application Ser. No. 09/586,736 (AMAT/4256Y1), titled “Programmable Anode Apparatus and Associated Method”, filed on Jun. 5, 2000; and co-pending U.S. patent application Ser. No. 10/962,236, filed on Oct. 8, 2004, which claim benefit of U.S. provisional patent application Ser. No. 60/510,190 (AMAT/8039L), titled “Methods And Chemistry For Providing Initial Conformal Electrochemical Deposition Of Copper In Sub-Micron Features”, filed on Oct. 10, 2003. Each of the aforementioned related patent applications is herein incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • Embodiments of the invention generally relate to deposition of a metal layer onto a substrate. Particularly, the invention relates to methods and systems for electrochemical deposition of a metal layer on a substrate.
  • 2. Description of the Related Art
  • Submicron, multi-level metallization is one of the key technologies for very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices. The multilevel interconnects that lie at the heart of this technology require the filling of contacts, vias, lines, and other features formed in high aspect ratio apertures. Reliable formation of these features is very important to the success of both VLSI and ULSI as well as to the continued effort to increase circuit density and quality on individual substrates and die.
  • As circuit densities increase, the widths of contacts, vias, lines and other features, as well as dielectric materials between them, may be decreased. Since the thickness of the dielectric materials remains invariable, the result is that the aspect ratios (i.e., their height divided by width) for most semiconductor features have to substantially increase. Many conventional deposition processes do not consistently fill semiconductor structures in which the aspect ratios exceed 6:1, and particularly when the aspect ratios exceed 10:1. As such, there is a great amount of ongoing effort being directed to the formation of void-free, nanometer-sized structures having aspect ratios of 6:1 or higher.
  • Electro-chemical deposition (ECD), such as Electro-chemical plating (ECP), originally used in other industries, has been applied in the semiconductor industry as a deposition technique for filling small features because of its ability to grow the deposited material, such as copper, on a conductive surface and fill even high aspect ratio features substantially free of voids. Typically, a metallic diffusion barrier layer is deposited over the surface of a feature, followed by the deposition of a conductive metal seed layer. Then, a conductive metal is electro-chemically plated over the conductive metal seed layer to fill the structure/feature. Finally, the surface of the feature is planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
  • Copper has become the desired metal for semiconductor device fabrication, because of its lower resistivities and significantly higher electromigration resistance as compared to aluminum and good thermal conductivity. Copper electro-chemical plating systems have been developed for semiconductor fabrication of advanced interconnect structures. Typically, copper ECP uses a plating bath/electrolyte including positively charged copper ions in contact with a negatively charged substrate, as a source of electrons, to plate out the copper on the charged substrate.
  • All ECP electrolytes have both inorganic and organic compounds at low concentrations. Typical inorganics include copper sulfate (CuSO4), sulfuric acid (H2SO4), and trace amounts of chloride (Cl) ions. Typical organics include accelerators, suppressors, and levelers. An accelerator is sometimes called a brightener or anti-suppressor. A suppressor may be a surfactant or wetting agent, and is sometimes called a carrier. A leveler is also called a grain refiner or an over-plate inhibitor.
  • Most ECP processes generally require two processes, wherein a seed layer is first formed over the surface of features on the substrate (this process may be performed in a separate system), and then the surfaces of the features are exposed to an electrolyte solution while an electrical bias is simultaneously applied between the substrate surface (serving as a cathode) and an anode positioned within the electrolyte solution.
  • Conventional plating practices include depositing a copper seed layer by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) onto a diffusion barrier layer (e.g., tantalum or tantalum nitride). However, as the feature sizes become smaller, it becomes difficult to have adequate seed step coverage with PVD techniques, as discontinuous islands of copper agglomerates are often obtained in the feature side walls close to the feature bottom. When using a CVD or ALD deposition process in place of PVD to deposit a continuous sidewall layer throughout the depth of the high aspect ratio features, a thick copper layer is formed over the field. The thick copper layer on the field can cause the throat of the feature to close before the feature sidewalls are completely covered. When the deposition thickness on the field is reduced to prevent throat closure, ALD and CVD techniques are also prone to generate discontinuities in the seed layer. These discontinuities in the seed layer have been shown to cause plating defects in the layers plated over the seed layer. In addition, copper tends to oxidize readily in the atmosphere and copper oxide readily dissolves in the plating solution. To prevent complete dissolution of copper in the features, the copper seed layer is usually made relatively thick (as high as 800 Å), which can inhibit the plating process from filling the features. Therefore, it is desirable to have a copper plating process that allows direct electroplating of copper on suitable barrier layer(s) without a copper seed layer.
  • Another challenge with direct copper plating on a suitable barrier metal layer is that the resistance of the barrier metal layer is high (low resistivity) and is known to cause high edge-plating, i.e. thicker copper plating at the edge of the substrate and no copper plating in the middle of the substrate. Also, copper tends to plate on local sites of nucleation, resulting in clusters of copper nuclei, copper clusters/crystal, so deposition is not uniform on the whole surface of the substrate.
  • Therefore, there is a need for a copper plating process that can plate a thin copper seed layer directly on suitable barrier metals to uniformly deposit copper across the whole substrate surface and fill features before plating of a bulk copper layer.
  • SUMMARY OF THE INVENTION
  • Embodiments of the invention provide an electrochemical deposition method for plating a thin copper seed layer directly on a barrier layer and an apparatus adapted for the method.
  • Embodiments of the invention provide a method of plating a metal layer onto a substrate in a plating apparatus having two or more segments of an anode and an auxiliary electrode. The method includes plating a first portion of the metal layer on the surface of the substrate under a first processing condition to at least cover a large portion of the substrate, the first processing condition comprising electrically connecting a first power supply to a central segment of the anode and the substrate.
  • Embodiments of the invention further provide a method of plating a metal layer onto a substrate in a plating cell having a first and a second electrode. The method includes connecting a first power supply to a central segment of the first electrode and the substrate, connecting a second power supply to the second electrode and the substrate, and plating a first portion of the metal layer on the surface of the substrate at reverse polarity of the first and the second electrodes.
  • Embodiments of the invention may further provide a method of plating a metal layer onto a substrate in a plating cell having two or more segments of an anode and an second electrode. The method includes applying a first current pulse to the substrate to deposit a first portion of the metal layer on the surface of the substrate, the first current pulse is provided by a first power supply and a second power supply which are in electrical communication in reverse polarity with one segment of the anode and the second electrode, respectively. The method further includes applying a second current pulse to the substrate to deposit a second portion of the metal layer on the surface of the substrate, the second current pulse comprising currents provided to all segments of the anode.
  • Embodiments of the invention may further provide a method of plating a metal layer onto a substrate in a plating cell including plating a metal coating on the contact points of the plating cell before the substrate is placed inside the plating cell and plating a metal layer onto the surface of the substrate.
  • Embodiments of the invention may further provide an electrochemical plating cell configured to metallize sub 100 nanometer features on integrated circuit devices. The plating cell includes a fluid basin having an anolyte solution compartment and a catholyte solution compartment, an ionic membrane positioned between the anolyte solution compartment and the catholyte solution compartment, two or more anode segments positioned in the anolyte solution compartment, an auxiliary electrode, two or more power supplies connected to the two or more anode segments and the auxiliary electrodes, and substrate contact elements/points positioned to electrically contact and support a substrate for processing in the fluid basin.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
  • FIGS. 1A-1C illustrate schematic cross-sectional views of an integrated circuit fabrication sequence.
  • FIG. 2A illustrates non-uniform deposition during initial phase of metal plating.
  • FIG. 2B illustrates a substrate surface having poor edge plating near contact locations with hazy zones showing depletion of plated copper.
  • FIG. 3 illustrates a flow diagram of a method according to one embodiment of the invention.
  • FIG. 4 illustrates a schematic sectional view of one embodiment of an exemplary electrochemical plating system of the invention.
  • FIG. 5 illustrates a schematic cross-sectional view of one embodiment of an exemplary electrode configuration of the invention.
  • FIG. 6 illustrates a horizontal section of one embodiment of an exemplary electrochemical plating system of the invention showing anolyte fluid flow patterns.
  • FIGS. 7A-7E illustrates exemplary electrode configurations that may be used in an electrochemical plating system of the invention according to embodiments of the invention.
  • FIG. 8 is a flow diagram illustrating one embodiment of an exemplary electrochemical plating method of the invention.
  • FIGS. 9A-9B illustrate exemplary connections of power supplies to various electrodes of an electrochemical plating system of the invention according to embodiments of the invention.
  • FIG. 10 illustrates exemplary current paths inside an electrochemical plating system of the invention according to one embodiment of the invention.
  • FIGS. 11A-11B illustrate exemplary controlled current variation diagrams on power supplies connected to various electrodes of an electrochemical plating system of the invention according to embodiments of the invention.
  • FIG. 12 illustrates an exemplary result of plating a thin metal layer using the method and apparatus of the invention, resulting in uniform deposition across a surface of a substrate.
  • DETAILED DESCRIPTION
  • Embodiments of the invention provide a method and apparatus adapted for electrochemical deposition of a thin metal seed layer and/or a bulk metal layer on a substrate having a conductive barrier metal thereon. The metal material suitable for the bulk metal layer can be any metal materials that can be plated on a substrate surface, such as copper, nickel, etc. For example, the invention provides plating of a copper material on the surface of a barrier material or a copper seed layer during direct or indirect copper plating process to fill submicron features during semiconductor interconnect formation. In one embodiment, the invention may include at least three or more stages/steps (as will be described in detail herein) during electrochemical deposition of a conductive metal material to obtain uniform plating across the entire surface of a substrate. The three or more stages of plating can be performed in the same electrochemical deposition apparatus or in different plating tools. Particularly, the invention allows uniform plating of one or more metal layers on a substrate surface having materials with low resistivity (thus highly resistive) thereon. In addition, the invention is provided to solve high substrate surface resistance problems, to improve contact resistance and current distribution at the edges of a substrate.
  • The surface of the substrate can be any of the materials that can be used as a suitable seed or conductive material for plating, such as a group VIII metal or noble metal barrier layer. The substrate surface material includes, but is not limited to, copper (Cu), ruthenium (Ru), chromium (Cr), tantalum (Ta), iridium (Ir), osmium (Os), tungsten (W), palladium (Pd), platinum (Pt), and alloys thereof. For example, ruthenium (Ru) is a metal with low resistivity and can be used to coat features on a substrate as a barrier layer for direct copper plating without the need of a copper seed layer deposited by other deposition methods than plating.
  • FIGS. 1A-1C illustrate cross-sectional views of a substrate at different stages of a metal interconnect fabrication sequence. In FIG. 1A, metal contacts 104 and a dielectric layer 102 are formed on the surface of a substrate 100 comprising a semiconductor material, such as, for example, silicon, germanium, or gallium arsenide. The dielectric layer 102 may include an insulating material, such as, silicon dioxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxides, such as SiOxCy, for example, BLACK DIAMOND™ Iow-κ dielectric material, available from Applied Materials, Inc., located in Santa Clara, Calif. The metal contacts 104 may include, for example, copper, among others. Apertures 120 are defined in the dielectric layer 102 to provide openings over the metal contacts 104. The apertures 120 may be defined in the dielectric layer 102 using conventional lithography and etching techniques.
  • In FIG. 1B, optionally, a barrier layer 106 may be formed on top of the dielectric layer 102. The barrier layer 106 may include one or more refractory metal-containing layers used as a copper-barrier material, for example, titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, tungsten and tungsten nitride, among others. The barrier layer 106 may be formed using a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). For example, titanium nitride may be deposited by a CVD process or an ALD process using, for example, titanium tetrachloride and ammonia. In one embodiment, tantalum nitride and/or tantalum is deposited as a barrier layer by an ALD process as described in commonly assigned U.S. patent Publication 2003/0121608, published Jul. 3, 2003, and herein incorporated by reference. The thickness of the optional barrier layer is between about 5 Å to about 150 Å and preferably less than 100 Å.
  • One embodiment of the invention provides plating of a uniform copper layer on an underlying layer of a conductive material, such as a group VIII metal material, e.g., ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum (Pt), among others, which are very resistive to start/nucleate plating because of their low electrical resistivity. As an example, a thin ruthenium layer of about 100 Å is about 100 times more resistant than a copper seed layer of about 1000 Å and is passive for copper to plate thereon, independent of the deposition process used to form the underlying layer.
  • The group VIII metal material may be used as a barrier layer or an under-layer for copper interconnect features, e.g., vias, trenches, and lines, which have aspect ratios hreater than 3:1, because most group VIII metal materials provide low electrical resistivity and high thermal stability, and are resistant to corrosion and oxidation. For example, the resistivity of ruthenium is about ˜7 μΩ-cm and its melting point is about 2300° C. In addition, the thermal and electrical conductivities of ruthenium are twice of those of tantalum (Ta), so ruthenium is a good barrier layer for copper. Ruthenium also does not form an alloy with copper at temperature below 900° C. and shows good adhesion to copper. Thus, group VIII metal or noble metal materials can also be deposited on a conventional barrier layer, such as Ta (tantalum) and/or TaN (tantalum nitride), to serve as a glue layer between the conventional barrier layer and copper. In addition, the low resistivity of ruthenium (Ru) can be an advantage when trying to fill ruthenium coated features during copper interconnect without the need for a copper PVD or CVD seed layer. Especially, ruthenium can be a good seedless diffusion barrier material between intermetal dielectrics (IMD) for a less than 45 nm copper interconnect.
  • Referring to FIG. 1B, a group VIII barrier metal layer 108, such as ruthenium (Ru), is formed on the substrate, for example, on a barrier layer 106. The thickness for the group VIII metal layer 108 often depends on the device structure to be fabricated. Typically, the thickness of the group VIII metal layer 108, such as ruthenium (Ru), is less than about 1,000 Å, preferably between about 5 Å to about 200 Å. In one embodiment, the group VIII metal layer 108 is a ruthenium layer having a thickness less than about 100 Å, for example, about 50 Å.
  • Thereafter, referring to FIG. 1C, the apertures 120 may be filled with a metal material 110, such as copper, to complete the interconnect. In one embodiment, the noble or transitional metal layer, such as a ruthenium layer, serves as a seed layer which a copper is directly deposited by electrochemical plating or other copper plating techniques. The width of apertures 120 may be, for example, equal to or less than about 900 Å. The thickness of dielectric layer 102 is not limited and may be in the range between about 1000 Å to about 10000 Å.
  • An electrochemical plating solution for ECP copper plating generally includes a copper source, an acid source, a chlorine ion source, and at least one plating solution additive, i.e., levelers, suppressors, accelerators, antifoaming agents, etc. For example, the plating solution may contain between about 30 and about 60 g/L of copper, between about 10 and about 50 g/L of an acid, between about 20 and about 100 ppm of chloride ions, between about 5 and about 30 ppm of an additive accelerator, between about 100 and about 1000 ppm of an additive suppressor, and between about 1 and about 6 ml/L of an additive leveler. The plating current may be in the range from about 2 mA/cm2 to about 10 mA/cm2 for filling copper into the submicron trench and/or via structures. Examples of copper plating chemistries and processes can be found in commonly assigned U.S. patent application Ser. No. 10/616,097, titled “Multiple-Step Electrodeposition Process For Direct Copper Plating On Barrier Metals”, filed on Jul. 8, 2003, and U.S. patent application No. 60/510,190, titled “Methods And Chemistry For Providing Initial Conformal Electrochemical Deposition Of Copper In Sub-Micron Features”, filed on Oct. 10, 2003. An example of an electrochemical plating (ECP) system and an exemplary plating cell are described in FIGS. 4-7 below.
  • Problems with group VIII barrier material, such as ruthenium (Ru), as a highly resistive thin barrier layer for copper plating is that uniform plating cannot occur on the whole surface of the substrate, especially on substrates having small features thereon. In addition, the initial overpotential to start plating must be higher than normal, for example, an additional voltage of about 30 mV or more is required for plating copper on ruthenium than on copper. In addition, there is poor contact of the substrate with substrate contact points located near the edges of the substrate resulting in hazy zone or poor plating in those locations.
  • FIG. 2A illustrates initial copper growth versus uniformity on the whole surface of a substrate having a ruthenium barrier layer. Initially, plating is mainly on the edge of a substrate for the initial plating time periods t1, t2, t3, resulting in non-uniform copper deposition. Even when copper starts to deposit on the substrate, the plated copper nuclei or clusters are separated and it takes time for them to finally overlap with each other. FIG. 2B illustrates plating of a metal layer on the surface of a substrate 210. Plating on the edges of the substrate 210 where the substrate 210 is in contact with the plating apparatus used is not uniform. Hazy zones 220 showing depletion of plated metal material are sometimes millimeters in sizes.
  • Thus, one embodiment of the invention is provided to solve the problem of non-uniformity on the surface of a substrate during plating of a metal material and includes multiple stages of metal plating processes which require the use of at least two electrodes in a plating apparatus. One electrode serves as the main anode, which is aligned with the center of the substrate during plating. Another electrode is an auxiliary electrode which is located near the edge of the substrate and can serve as an additional anode or cathode during plating. The invention also contemplates the use of additional electrodes, electrode segments, or anode segments to aid in generating uniform current density during plating. Further, before plating of a thin metal seed layer on a substrate, the invention contemplates coating or pre-treating the substrate contact points/locations of a plating apparatus with a thin coating of the metal material to be plated to improve uniform metal plating on the substrate and uniform current distribution,
  • FIG. 3 illustrates a method 300 of the invention including an optional step 310 a of plating a thin metal layer using a plating apparatus in the absence of a substrate. Thus, a metal coating of less than about 600 Å, such as from about 50 Å to about 500 Å, is plated on the contact pins or various contact elements/points of the plating apparatus. Another optional pre-treatment of the substrate contact points/locations/elements prior to deposition of the metal coating may include removing of any contaminants or deposits by de-plating, such as by connecting the substrate contact points to an anodic terminal of a power supply for a short period of time to deplate contaminants from the substrate contact elements.
  • Next at stage 310, a thin metal layer is plated on the surface of the substrate under a first processing condition to at least cover a large portion of the substrate at stage 310. For example, a thin copper seed layer is directly plated on a substrate surface having group VIII metal or noble metal barrier materials thereon in order to generate a relative uniform and conductive surface for subsequent plating steps. The substrate surface may include a ruthenium barrier layer or a copper seed layer deposited by physical vapor deposition (PVD) technique.
  • The first processing condition may include a short DC current pulse provided by at least two power supplies in reverse direction. One power supply is connected to a main anode and the substrate (serving as a cathode). Another power supply is connected to one or more auxiliary electrodes and the substrate to provide a current going through the one or more auxiliary electrodes in reverse polarity to the current going through the main anode.
  • The main anode may be one central/inner anode segment, or several anode segments, which cover a large area of an anode assembly in a plating apparatus. In addition, the main anode may be aligned with or located near the center/middle of a substrate to be processed and the one or more auxiliary electrode may be located near the peripheral regions of the substrate such that current going through the center/middle of the substrate may be increased. The main anode connected to a first power supply is used to electrodeposit copper onto the substrate surface, preferably onto the middle of the substrate. The one or more auxiliary electrodes connected to a second power supply working in reverse direction of the first power supply is used to act as current thieves to decrease the electrodeposition near the edges of the substrate. In one embodiment, the short DC current pulse is applied under the first processing condition to increase deposition toward the center/middle region of the substrate. In another embodiment, the short DC current pulse is applied under the first processing condition to decrease deposition toward the periphery of the substrate.
  • Each current going through the first and the second power supplies is constant during the DC current pulse but may be different in amplitude and direction/polarity. With the use of the main anode, the one or more auxiliary electrodes, and the two or more power supplies, plating can be uniformly occurring on the whole surface of the substrate.
  • The short DC current density of this pulse passing through the substrate depends on the material of the barrier (or the passivity of the barrier material) used, the electrolyte used for plating, and the geometry of the electrical field near the substrate, and may be from about 40 mA/cm2 to about 50 mA/cm2, for example. Other factors which may affect the DC current density may include the diameter of the central main anode segment, conductivity of the electrolyte, etc. The short DC current density may last for a time period until a required thickness is reached. In one embodiment, a thin copper seed layer of about 30 Å to about 250 Å, such as about 50 Å to about 100 Å is formed uniformly at stage 310.
  • At stage 320, plating under a second processing condition is performed to at least fill gaps, features, such as the apertures 120, on the substrate surface. In one embodiment, a total thickness of the plated copper after stage 320 is more than about 50 Å, such as from about 50 Å to about 200 Å or more, or about 500 Å to about 1000 Å. The second processing condition may include a DC current pulse for plating to continue by providing one or more power supplies to one or more anodes, anode segments, or all anode segments, which are aligned to cover the surface of the substrate. The intensity for the DC current pulse under the second processing condition depends on the resitivity of the plated metal, the underlying materials on the substrate, and other plating parameter, and is not limiting. In one embodiment, the intensity for the DC current pulse under the second processing condition is less than the intensity of the DC current pulse under the first processing condition. In addition, under the second processing condition, the current intensity for the auxiliary electrode is not limiting. The auxiliary electrode may be idle, serve as an additional cathode, or serve as an additional anode. In one embodiment, current can be applied through the auxiliary electrode with less current than the current going through the substrate
  • At stage 330, plating is performed under a third processing condition to at least deposit a portion of a bulk metal layer on the substrate surface. In one embodiment, a total thickness of a bulk copper layer at stage 330 may be more than about 500 Å, such as from about 800 Å to about 1200 Å. The third processing condition may include plating at high throughput to continuously deposit copper to a desired total thickness. One or more power supplies are connected to the anode assembly of the plating apparatus (including one or more or all anode segments) and one or more auxiliary electrodes, and plating can be uniformly occurring on the whole surface of the substrate.
  • Embodiments of the invention further provide a plating apparatus adapted for electrochemical deposition of a metal layer including a thin metal seed layer and/or a bulk metal layer on a substrate. The plating apparatus or plating cell includes one or more electrodes, such as a main anode electrode/anode segment, another one or more anode electrodes, and one or more auxiliary electrodes or counter electrodes. The auxiliary electrode is positioned and configured to be electrically isolated from the anode electrodes. Exemplary plating cells may be found in commonly assigned U.S. patent application Ser. No. 10/627,336, filed Jul. 24, 2003 entitled “Electrochemical Processing Cell”, and commonly assigned U.S. patent application Ser. No. 10/880,103, filed Jun., 28, 2004 entitled “Electrochemical Plating Cell with a Counter Electrode in an Isolated Anolyte Compartment”; both are hereby incorporated by reference in their entirety.
  • FIG. 4 illustrates a sectional view of a plating cell 400 of the invention without a head assembly. The plating cell 400 includes a fluid basin 408 surrounded by an overflow weir 409 (a contiguous uppermost fluid overflow point) to contain electrolyte, fluid, or plating bath therein. Excess fluid or electrolyte overflows or spills into an outer collection volume 412 that circumscribes the overflow weir 409. FIG. 5 illustrates another sectional view of the plating cell 400 with a head assembly 402 of the invention in a processing position. The head assembly 402 is configured to support and electrically bias a substrate 418 for electrochemical plating operations in the fluid basin 408 inside the plating cell 400. The head assembly 402 generally includes a contact ring 406 having thereon a plurality of metal or metal alloy electrical contact elements that electrically contact the substrate. The electric contact elements/points take the form of contact pins, contact rods, contact surfaces, contact pads, etc., such as one or more contact pins 403. The contact elements/points are generally made out of inert materials, such as noble metals, semi-noble metals, platinum, etc. One embodiment of the invention includes plating or coating of a thin metal layer to the contact elements in the absence of the substrate to provide a good contact for plating on the substrate during a later plating process. Plating of the thin metal layer on the contact elements or contact pins 403 is performed by connecting the contact pins 403 to a cathodic terminal of a power supply (not shown). The thin metal layer coated on the contact pins 403 may be the same material as the metal to be plated later on the substrate. Optionally, the contact elements or contact pins 403 can be pre-treated by a deplating process to remove any deposits thereon by connecting the contact pins 403 to a anodic terminal of a power supply before the thin metal layer is coated/plated thereon.
  • Inside the fluid basin 408, one or more electrodes, anode assembly 422 or anode segments 422 a-422 c, are configured to be used as the anode for plating. Additionally one embodiment of the invention provides an auxiliary electrode assembly 424 configured to be positioned radially outward of the perimeter of the anode assembly 422 or anode segments 422 a-422 c. The one or more anode assembly 422, anode segments 422 a-422 c, and the auxiliary electrode assembly 424 may be made out of electrically conductive members. The conductive member may be manufactured from a consumable material, such as copper, or from an inconsumable material, such as platinum or another noble metal, etc.
  • An anolyte volume 420 generally contains an anode assembly that includes the one or more anode segments 422 a-422 c positioned in contact with an anolyte solution flowing therethrough. The one or more anode segments may include a main anode 422 a, an anode segment 422 b, and an additional anode segment 422 c, etc, which will be further discussed in FIGS. 7A-7C.
  • The fluid basin 408 is configured to confine an inner fluid volume 410 and to receive the substrate 418 for plating in the inner fluid volume 410. Overflown plating solution from the inner fluid volume 410 is drained into the outer collection volume 412 such that the plating solution may be recirculated back to the inner fluid volume 410. Optionally, a fluid diffusion member 414 is positioned across the inner fluid volume 410 at a position below where the substrate 418 being plated is positioned and above the anode assembly 422. The fluid diffusion member 414 operates to resist fluid flow variations across the substrate 418 and in the direction between the anode assembly 422 and the substrate 418. A more thorough description of the fluid diffusion member and other plating cell components and operational characteristics may be found in commonly assigned U.S. Pat. No. 6,261,433 and commonly assigned U.S. Pat. No. 6,585,876, both of which are hereby incorporated by reference in their entireties.
  • Further, a membrane 416 is positioned across the fluid basin 408 and, if used, at a position below where the diffusion member 414 may be positioned and above the anode segments 422 a-422 c. The membrane 416 is generally an ionic membrane, and more particularly, a cationic membrane, generally configured to prevent fluid passage therethrough, while allowing ions, such as copper ions, to travel through the membrane 416 toward the substrate 418. As such, the membrane 416 generally operates to separate a catholyte volume 419 of the plating cell 400 from the anolyte volume 420 of the plating cell 400. The catholyte volume 419 is generally referred to as the fluid volume between the membrane 416 and the substrate 418, and the anolyte volume 420 is referred to as the fluid volume below the membrane 416 adjacent the anode segments 422 a-422 c. A more thorough description of the membrane 416 and the separation of an anolyte solution from a catholyte solution may be found in commonly assigned U.S. patent application Ser. No. 10/627,336, filed Jul. 24, 2003 entitled “Electrochemical Processing Cell”, which is hereby incorporated by reference in its entirety.
  • A plating solution, such as an anolyte solution, is supplied to the anolyte volume 420 by an anolyte supply conduit 431 a and drained from the anolyte volume 420 by an anolyte drain conduit 431 b positioned on an opposing side from the anolyte supply conduit 431 a. The positioning of the anolyte supply conduit 431 a and the anolyte drain conduit 431 b generates directional flow of the anolyte solution across the upper surface of the anode segments 422 a-422 c, as described in commonly assigned U.S. patent application Ser. No. 10/268,284, filed Oct. 9, 2002 entitled “Electrochemical Processing Cell”, which is hereby incorporated by reference in its entirety.
  • A second anolyte supply conduit 432 a is also configured to supply an anolyte solution to a volume 435 surrounding the auxiliary electrode assembly 424, while not fluidly or electrically communicating with the anolyte volume 420 contained in the volume adjacent the anode segments 422 a-422 c and supplied by the anolyte supply conduit 431 a and the anolyte drain conduit 431 b. A second anolyte drain conduit 432 b is configured to drain fluid from the volume 435 near the auxiliary electrode assembly 424. The volume 435 is fluidly bound by the membrane 416 on the upper side thereof with two seals 436, such as circular o-ring-type seals, adjacent the auxiliary electrode assembly 424.
  • As shown in FIGS. 5 and 6, the anolyte solution supplied by the anolyte supply conduit 432 a generally flows through the volume 435 above the auxiliary electrode assembly 424 in a semicircular pattern, as illustrated by arrows “A”. As such, the anolyte solution circulated through the volume 435 is collected by the second anolyte drain conduit 432 b on the opposing side of the plating cell 400. In addition, the anolyte solution supplied to the anolyte volume 420 generally flows directly across the anode assembly 422 or the anode segments 422 a-422 c, as illustrated by arrows “B” in FIG. 6, and is collected by the anolyte drain conduit 431 b. The fluid flows indicated by arrows “A” and “B” both occur below the membrane 416. Flow “A” occurs between the seals 436, and flow “B” occurs across the top of the anode assembly 422 or the anode segments 422 a-422 c radially inward of the seal 436.
  • Referring back to FIG. 5, although the anode segments 422 a-422 c and the auxiliary electrode assembly 424 are generally positioned such that they are in fluid communication with an anolyte solution, they are also positioned and configured such that the anode segments 422 a-422 c are electrically isolated from the auxiliary electrode assembly 424. More particularly, an electrically insulating spacer 426 is generally positioned between the anode segments 422 a-422 c and the auxiliary electrode assembly 424.
  • A plating solution, also termed a catholyte, is supplied to the catholyte volume 419 by a fluid conduits 433 a, 433 b which is in fluid communication with a catholyte solution tank (not shown). The catholyte solution generally includes several constituents, including, for example, water, copper sulfate, halide ions, and one or more of a plurality of plating additives (levelers, suppressors, accelerators, etc.). The catholyte solution supplied by the fluid conduits 433 a, 433 b overflows the weir 409 and is collected by the collection volume 412.
  • Although the membrane 416 provides a fluid barrier that prevents the anolyte solution from fluidly transferring therethrough, the membrane 416 allows for ionic transfer, and more particularly, for positive ionic transfer. As such, although the anolyte cannot permeate the membrane 416, ions such as copper and hydrogen ions may transfer through the membrane 416 into vent conduit 440, which contains catholyte. Thus, the combination of the volume 435 above the auxiliary electrode assembly 424 and the catholyte in vent conduit 440 generates an electrical path for current to travel through the auxiliary electrode assembly 424.
  • FIGS. 7A-7E illustrate exemplary anode configurations that may be used in embodiments of the invention, wherein the segments a, b, and c are denoted, such as the anode segments 422 a, 422 b, and 422 c. It is understood that each of the segments a, b, and c of the respective anode arrangements may be individually powered to control and/or optimize plating parameters. Electrical flux above the anode segments 422 may be controlled by applying the same or a different electrical power to the respective anode segments 422 a, 422 b, and 422 c during different stages of the plating process. In one embodiment, an inner or central anode segment or a main anode, aligned with an inner or central region of a substrate for plating in the middle of the substrate, may include one or more anode segments (e.g., 422 a, 422 b, or 422 a plus 422 b). The anode segments, 422 or 422 a, 422 b, 422 c may be concentric, symmetric, circular, linear, rectangle, or any other configuration depending upon the desired flux.
  • FIG. 8 illustrates an exemplary method 800 of the invention which can be used in the plating cell 400 to plate a thin metal layer on the surface of a substrate. At step 810, two or more electrodes and a substrate are provided in a plating apparatus, such as the plating cell 400. Optionally, before the substrate is provided inside the plating apparatus, a coating of a metal layer on the contact pins 403 can be performed by plating until a desired thickness of from about 50 Å to about 500 Å or more is reached.
  • At step 820, a first power supply is connected to a central segment of a first electrode, such as an anode positioned in a plating cell and aligned with the central region of the surface of a substrate for plating on the center/middle of the substrate. At step 830, a second power supply is connected to a second electrode positioned and aligned with the peripheral region or edges of the substrate. The second electrode can be, for example, an anode, a cathode, an auxiliary electrode, a counter electrode, etc.
  • At step 840, plating is performed under a first processing condition and at reverse polarity of the first and second electrodes to deposit a thin metal layer uniformly on the substrate surface. For example, one embodiment of the invention provides a plating cell 400 having a central segment, such as the anode segment 422 a, which is in electrical communication with an anodic terminal of a first power supply (not shown) and the cathodic terminal of the same power supply is generally in electrical communication with the contact ring 406, which is configured to electrically contact the substrate 418, serving as the cathode. In another embodiment, the auxiliary electrode assembly 424 is in electrical communication with a cathodic terminal of a second power supply (not shown). However, although only two power supplies are discussed herein, it is understood that more than two independently controlled power supplies may be used without departing from the scope of the invention. For example, additional power supply or the same first power supply can be used to electrically connect to additional electrode segments, such as 422 b and 422 c, depending on the processing parameter requirements during different stages of electrochemical plating. In addition, the anode segments 422 a, 422 b, 422 c may also be individually powered and are not limited to any particular number, i.e., there may be between 1 and about 10 or more anode segments in a plating cell. With regard to independently powering anode segments, the power density applied on the anode segment may be the same or vary, e.g., the power on the anode segment 422 a may be greater than those on the anode segment 422 b.
  • FIGS. 9A and 9B illustrate two exemplary ways to connect the two or more power supplies to the substrate, the main anode 422 a (the main anode segment or one or more anode segments), the one or more auxiliary electrode (the auxiliary electrode assembly 424), and other anodes/electrode segments. Both power supplies are operating synchronously. The current on each power supply (PS) is constant during a short DC current pulse but different in the amplitude and direction/polarity.
  • In one embodiment, the current passing through the auxiliary electrode 424 is less than the current passing through the substrate 418 and also less than the current passing through the anode assembly 422, or the anode segments 422 a, 422 b, or 422 c. For example, the total current passing through the second power supply (PS2) is about 10% to about 60% of the total current passing through the substrate 418 (served as the cathode), as shown in FIG. 9A, or through the one or more anodes/anode segments, as shown in FIG. 9B, depending on the various ways to connect the power supplies. In addition, the current ratio between the first power supply (PS1) and the second power supply (PS2) may vary, depending on the distance between the auxiliary electrodes, the diameter of the central main anode (central anode segment), the resistance of the diffuser in vertical and horizontal directions, and the surface area of the auxiliary electrodes, etc.
  • FIG. 10 illustrates exemplary current paths and electrical flux lines generated near the main anode 422 a and the auxiliary electrode assembly 424 inside the plating cell 400 of the invention during a plating process. The electrical flux immediately above the auxiliary electrode assembly 424 is represented by the arrows labeled “D” and the flux immediately above the main anode 422 a is represented by the arrows labeled “E”, which is in reverse direction as arrow “D”. In one embodiment, the invention provides applying an electrical flux in a reverse direction toward the peripheral of the substrate to deposit a first portion of the metal layer on the surface of the substrate. The electrical flux can be provided by a first power supply and a second power supply which are in electrical communication with at least one segment of the anode and the auxiliary electrode assembly, respectively.
  • Not wishing to be bound by theory, it is thought that when the central anode segment or the main anode 422 a is connected to the first power supply, during the initial plating stage of a very short time span, such as less than 4 seconds, copper deposition starts from the edges of the substrate 418 near the contact pin 403 and extend to the middle of the substrate. The distance between the growing copper front and the middle of the substrate becomes shorter and shorter and the overvoltage in the middle of the substrate increases such that nucleation becomes possible over the whole surface of the substrate. This short time span of initial nucleation generally depends not only on the characteristic or passivity of the barrier metal on the substrate but also on the average current passing through the substrate 418 and the current passing through the auxiliary electrode assembly 424. Higher current passing through the substrate 418 generally results in a larger area on the substrate where nucleation can occur.
  • However, the presence of a nucleation zone 910 or nucleation area on the substrate 418 is also very sensitive to the characteristic of the material already on the substrate surface. For example, Group VIII metal materials generally are very passive and require a high initial overvoltage to start nucleation for copper to plate on. Also the nucleation zone 910 on a surface of a substrate with Group VIII metal material thereon is very narrow, even at extremely high average current applied on the substrate.
  • The invention employs the use of an auxiliary electrode as a current thief with an optimal high reverse current passing through in order to widen the initial nucleation zone dramatically and re-distribute the current from the edges to the center/middle of the substrate. However, the current passing through the auxiliary electrode during the initial nucleation stage should be optimal and cannot otherwise make the current near the contact pins 403 become anodic, resulting in copper dissolution near substrate edges or damage of the surface of the contacts and materials on the substrate. In operation, the auxiliary electrode assembly 424 is used in combination with the anode segments 422 a-422 c, which may be one of the segmented anodes illustrated in FIGS. 7A-7E or variations thereof, to control the electrical flux across the surface of the substrate 418 being plated. More particularly, the auxiliary electrode assembly 424, which is also in electrical communication with a second power supply (not shown) is used to selectively reduce the electric flux near the edges of the substrate 418 to prevent high edge plating by supplying an additional cathodic flux source to the area proximate the edges or perimeter of the substrate 418 and electrically communicating with the cathode volume 419 via a vent 440. As shown in FIG. 5, the vent 440 is generally an annular vent that circumscribes the perimeter of the substrate 418 and is positioned to conduct electrical flux from the auxiliary electrode assembly 424 to the catholyte volume 419 in a manner that reduces the quantity of electrical flux generated by the substrate/cathode near the perimeter of the substrate. As such, the electrical flux originating on the substrate 418 is increased near the center of the substrate 418.
  • As shown in FIG. 10, current generally is passed from the anode segments via the anolyte through the membrane 416, and through the catholyte to the substrate surface, the current path “F”, or directly to the contact pins 403 and contact ring 406 which is in electrical communication with a power supply, the current path “G”, without passing through the substrate. During the initial nucleation stage, when nuclei on a substrate surface start to overlap so that nucleation begins and the substrate surface becomes conductive completely, a current path “F” is easier and faster than a current path “G” such that current can flow through the middle/center region of the substrate easier. The current density in the middle of the substrate becomes higher and higher. After a short while, uniform deposition of a thin metal seed layer is formed on the whole substrate surface, having substantially the same thickness in the middle and the edges of the substrate.
  • Referring back to FIG. 8, at step 850, current is provided to all segments of the first electrodes and, at step 860, plating is performed under a second processing condition to at least fill gaps, features, apertures, among others, on the substrate surface. At step 850, all anode segments are in electrical communication with an anodic terminal of one or more power supplies, such as the first power supply. In one embodiment, the second electrode may be switched to be in electrical communication with an anodic terminal of the first or the second power supply for further uniform gap filling copper plating under the second processing condition. In another embodiment, a reduced current may be applied to the second electrode than the current applied to the anode segments of the first electrode. In an alternative embodiment, the second electrode may be idle.
  • At step 870, current is provided to the first electrode and plating is performed under a third processing condition to at least deposit a portion of a bulk metal layer on the substrate surface. Under the third processing condition, the central anode or, alternatively, all anode segments are in electrical communication with an anodic terminal of one or more power supplies. In addition, the current densities applied to the anode segments and the second electrode are not limiting. Alternatively, the second electrode may be idle.
  • It is noted that embodiments of the invention do not require the stages or steps to be performed in the order as described herein. Also, the respective parameters may be modified to perform the processes in various plating apparatus and for different substrate sizes, such as 200 mm, 300 mm substrates or square substrates, among others.
  • As an example, FIG. 11A illustrates the different currents going through two power supplies at different stages during plating according to embodiments of the invention. Optionally, there may be a substrate immersion stage with very low or no current pulse (Ii) on the two power supplies. Current going through the first power supply is shown as line 1110 in FIG. 11A and current going through the second power supply is shown as line 1120. The line 1110 may include a short current pulse (I1), a second current (I2), and a third current (I3), which are applied to the first power supply. The line 1120 may include a short current pulse (I1), a second current (I2), and a third current (I3), which are applied to the second power supply. The current pulse (I1) and (I1) are applied during the first stage, such as the stage 310 or the plating process for a thin copper seed. The current pulse (I2) and (I2) are applied during the second stage, such as the stage 320 or the plating process for copper gap fill. The current pulse (I3) and (I3) are applied during the third stage, such as the stage 330 or the plating process for a bulk copper layer. According to one embodiment of the invention, the first power supply is connected to the main anode 422 a, but not 422 b or 422 c during the first stage; however, it is connected to all anode segments 422 a-422 c during the second stage.
  • One embodiment of the invention may include a stage 310, step 840, or any steps herein which is also a multi-staged process in order to provide better quality of the thin plated metal seed, such as a copper seed. For example, the short DC current pulse at the stage 310 may include two or more shorter steps to tune the uniformity and quality of the electroplated copper seed formed on the substrate surface.
  • FIG. 11B demonstrates a multi-step first stage. Current going through the first power supply is shown as line 1130 and current going through the second power supply is shown as line 1140. As shown in FIG. 11B, the first stage may include an initial cathodic current pulse with a small and short current pulse going only through the main anode 422 a, a short current pulse with two power supplies in reverse polarity connected to the main anode 422 a and the auxiliary electrode assembly 424, and then an intermediate current pulse going only through the main anode 422 a. There can be overlapping time period for applying different current density to the main anode 422 a and the auxiliary electrode assembly 424.
  • FIG. 12 demonstrates exemplary direct plating of a thin copper seed, line 1201, on a substrate surface having a ruthenium barrier layer of about 100 Å. Plating is performed using an electrolyte having about 35 g/L of copper ions, about 100 g/L of sulfuric acid, about 3 ml/LI of additive accelerator, about 4 ml/L of additive suppressor, about 2 ml/L of additive leveler, and other additives. The average current applied to the substrate is about 20 mA/cm2 and current on the central anode segment is about 19.5 Amp and on the auxiliary electrode is about −5.3 Amp. In addition, line 1202 demonstrates plating uniformity of a copper layer of about 800 Å in thickness when contact pins are pre-plated with a thin copper layer of about 100 Å using the method of the invention. The results in FIG. 12 show uniform copper plating on the whole substrate surface, the same deposition thickness in the center and near the edges for a substrate size of about 300 mm.
  • While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (27)

  1. 1. A method of plating a metal layer onto a substrate in a plating cell having a central anode segment, one or more other anode segments, and an auxiliary electrode, comprising:
    plating a first portion of the metal layer on the surface of the substrate under a first processing condition to at least cover a large portion of the substrate, the first processing condition comprising electrically connecting a first power supply to the central anode segment and the substrate.
  2. 2. The method of claim 1, wherein the first processing condition further comprises:
    electrically connecting a second power supply to the auxiliary electrode and the substrate.
  3. 3. The method of claim 2, wherein the first and the second power supply are connected to the central anode segment and the auxiliary electrode in reverse polarity.
  4. 4. The method of claim 2, wherein the current going through the substrate is greater than the current going through the auxiliary electrode.
  5. 5. The method of claim 2, wherein the current going through the central anode segment is greater than the current going through the auxiliary electrode.
  6. 6. The method of claim 1, wherein the thickness of the metal layer is about 30 Å to about 250 Å.
  7. 7. The method of claim 1, wherein the central anode segment is aligned with a middle region of the substrate.
  8. 8. The method of claim 1, wherein the auxiliary electrode is located near the peripheral edges of the substrate.
  9. 9. The method of claim 1, further comprising:
    plating a second portion of the metal layer under a second processing condition to at least fill gaps between features on the surface of the substrate, wherein the second processing condition comprises electrically connecting a power supply to all anode segments and the substrate.
  10. 10. The method of claim 9, wherein the thickness of the metal layer is between about 50 Å to about 1000 Å.
  11. 11. The method of claim 1, further comprising:
    plating a third portion of the metal layer under a third processing condition to deposit at least a portion of a bulk layer on the surface of the substrate, wherein the thickness of the metal layer is more than about 800 Å.
  12. 12. The method of claim 1, wherein the central anode segment is aligned with a middle area of the substrate.
  13. 13. The method of claim 1, wherein the metal layer comprises copper.
  14. 14. A method of plating a metal layer onto a substrate in a plating cell having a first and a second electrode, comprising:
    connecting a first power supply to a central segment of the first electrode and the substrate;
    connecting a second power supply to the second electrode and the substrate; and
    plating a first portion of the metal layer on the surface of the substrate at reverse polarity of the first and the second electrodes.
  15. 15. The method of claim 14, wherein the current going through the substrate is greater than the current going through the second electrode.
  16. 16. The method of claim 14, wherein the current going through the central segment of the first electrode is greater than the current going through the second electrode.
  17. 17. The method of claim 14, wherein the thickness of the metal layer is about 30 Å to about 250 Å.
  18. 18. The method of claim 14, further comprising:
    plating a second portion of the metal layer under a second processing condition to at least fill gaps between features on the surface of the substrate, wherein the second processing condition comprises electrically connecting all segments of the first electrode.
  19. 19. The method of claim 14, further comprising:
    plating a third portion of the metal layer under a third processing condition to deposit at least a portion of a bulk layer on the surface of the substrate, wherein the thickness of the metal layer is more than about 800 Å.
  20. 20. A method of plating a metal layer onto a substrate in a plating cell having two or more segments of an anode and an second electrode, comprising:
    applying a first current pulse to the substrate to deposit a first portion of the metal layer on the surface of the substrate, the first current pulse being provided by a first power supply and a second power supply which are in electrical communication in reverse polarity with at least one segment of the anode and the second electrode, respectively; and
    applying a second current pulse to the substrate to deposit a second portion of the metal layer on the surface of the substrate, the second current pulse comprising currents provided to all segments of the anode.
  21. 21. The method of claim 20, wherein the at least one segment of the anode is aligned with a central region of the substrate.
  22. 22. The method of claim 20, wherein the auxiliary electrode is located near the peripheral edges of the substrate.
  23. 23. The method of claim 20, wherein the metal layer comprises copper.
  24. 24. A method of plating a metal layer onto a substrate in a plating cell having two or more segments of an anode and an second electrode, comprising:
    applying an electrical flux in a reverse direction toward the peripheral of the substrate to deposit a first portion of the metal layer on the surface of the substrate, the electrical flux being provided by a first power supply and a second power supply which are in electrical communication with at least one segment of the anode and the second electrode, respectively.
  25. 25. A method of plating a metal layer onto a substrate in a plating cell having a central anode segment and one or more other anode segments, comprising:
    plating the metal layer on the surface of the substrate under a first processing condition to at least cover a large portion of the substrate, the first processing condition comprising applying more current to the central anode segment than current applied to the one or more other anode segments;
    plating under a second processing condition to at least fill gaps between features on the surface of the substrate; and
    plating under a third processing condition to deposit at least a bulk portion of the metal layer on the surface of the substrate.
  26. 26. The method of claim 25, further comprising:
    deplating any contaminants from contact points of the plating cell; and
    plating a thin metal layer on contact points of a plating apparatus in the absence of the substrate before plating the metal layer onto the substrate.
  27. 27. The method of claim 25, wherein the metal coating comprises copper and the thickness of the metal coating is less than about 600 Å.
US11072473 2000-06-05 2005-03-03 Plating of a thin metal seed layer Abandoned US20050145499A1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
US58673600 true 2000-06-05 2000-06-05
US10616097 US20050006245A1 (en) 2003-07-08 2003-07-08 Multiple-step electrodeposition process for direct copper plating on barrier metals
US10664277 US7273535B2 (en) 2003-09-17 2003-09-17 Insoluble anode with an auxiliary electrode
US51019003 true 2003-10-10 2003-10-10
US57912904 true 2004-06-10 2004-06-10
US10880103 US20050284751A1 (en) 2004-06-28 2004-06-28 Electrochemical plating cell with a counter electrode in an isolated anolyte compartment
US10962236 US20050109627A1 (en) 2003-10-10 2004-10-08 Methods and chemistry for providing initial conformal electrochemical deposition of copper in sub-micron features
US62121504 true 2004-10-21 2004-10-21
US11072473 US20050145499A1 (en) 2000-06-05 2005-03-03 Plating of a thin metal seed layer

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US11072473 US20050145499A1 (en) 2000-06-05 2005-03-03 Plating of a thin metal seed layer
PCT/US2006/007303 WO2006096418A3 (en) 2005-03-03 2006-03-01 Plating of a thin metal seed layer
TW95107285A TW200643226A (en) 2005-03-03 2006-03-03 Plating of a thin metal seed layer

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US10616097 Continuation-In-Part US20050006245A1 (en) 2003-07-08 2003-07-08 Multiple-step electrodeposition process for direct copper plating on barrier metals
US10664277 Continuation-In-Part US7273535B2 (en) 2003-09-17 2003-09-17 Insoluble anode with an auxiliary electrode
US10880103 Continuation-In-Part US20050284751A1 (en) 2004-06-28 2004-06-28 Electrochemical plating cell with a counter electrode in an isolated anolyte compartment
US10962236 Continuation-In-Part US20050109627A1 (en) 2003-10-10 2004-10-08 Methods and chemistry for providing initial conformal electrochemical deposition of copper in sub-micron features

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Cited By (40)

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