JP2005311245A - Method for forming via hole - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To relieve irregularities at a portion directly above a via hole, to improve the flushness and smoothness between the surface of a plated layer on a substrate surface and the surface of plating metal inside the via hole (the portion directly above the via hole), and to reliably package parts directly above via-on-via and the via hole. <P>SOLUTION: The substrate surface by a plating metal formed by an electrolytic plating process is etched by a chemical liquid for dissolving a plating metal to reduce the irregularities on the substrate surface. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for forming a via hole in a multilayer printed wiring board, and more particularly to a method for forming a via hole by via filling plating.

  In recent years, electronic devices have become smaller and lighter in addition to high-frequency signals, digitization, and the like, and accordingly, printed wiring boards mounted on electronic devices are also required to be small and high-density.

  A build-up multilayer wiring board in which an insulating layer and a conductor layer are stacked one by one to form a multilayer power distribution layer greatly contributes to high-density mounting of a printed wiring board.

  The build-up multilayer wiring board is manufactured by forming an insulating layer on the surface layer of the core base insulating layer, applying holes to the insulating layer by laser light irradiation, etc., and then applying copper plating to the surface layer. A multilayer printed wiring board is manufactured (construction method) by repeating a process of forming a via hole for obtaining interlayer conduction and a surface wiring layer (for example, Non-Patent Document 1).

  Due to the characteristic via hole by this construction method, the build-up multilayer wiring board enables free placement of interlayer conductive portions and is applied to high-density mounting substrates of various mobile devices such as mobile phones.

  However, in this construction method, when a copper foil layer is formed as a conductive layer by ordinary copper sulfate plating, the via hole 105 has a concave shape as shown in FIG. In addition, it is difficult to configure a via-on-via with a further via hole and to mount a component such as an IC chip immediately above the via hole 105, and the requirements for the degree of freedom in wiring cannot be sufficiently satisfied. I came.

  In FIG. 3, 101 is a core base insulating layer, 102 is a core base conductor layer formed on the core base insulating layer 101, and 103 is a build-up formed on the surface of the core base insulating layer 101. An insulating layer 104 is a copper foil layer formed on the surface of the build-up insulating layer 103 by plating.

  Therefore, in recent years, a technique called via fill plating for filling the via hole with copper plating has been announced (for example, Patent Document 1).

  Via fill plating is performed by adding an inhibitor that suppresses plating growth and an accelerator that promotes plating growth to a copper sulfate plating bath.

  Inhibitors are difficult to adsorb inside the via hole and easily adsorb to the substrate surface due to the diffusion law of the substance, and by slowing the plating growth rate on the substrate surface compared to the inside of the via hole, It is said that the via hole is filled with copper.

  The promoter is uniformly adsorbed on the bottom surface, side surface, and substrate surface of the via hole. Subsequently, the surface area of the via hole decreases with the growth of plating, and the distribution of the promoter in the via hole becomes dense. By utilizing this, it is said that the plating speed inside the via hole becomes faster than the plating speed on the substrate surface, and the inside of the via hole is filled with copper.

  In general, the inhibitor and the accelerator are mixed in an appropriate composition in one plating bath, and the inside of the via hole can be filled with copper by the effect of both.

  Since the via hole is completely filled with copper by the above mechanism to form a conductor pattern, the plating growth rate in the via varies depending on the shape of the via hole, such as the diameter and volume (internal volume) of the via hole.

  For this reason, when the via hole shape varies greatly in one substrate or via holes of different diameters are mixed, all the via holes in one substrate are all integrated with via fill plating metal (copper). Is difficult to fill.

  For this reason, as shown in FIG. 4A, the copper inside the via hole is not completely filled, and the plated copper (via fill plated portion) of the via hole 105 with respect to the plated copper 206 on the substrate surface on which the conductor pattern is formed. ) 207 has a concave shape, or as shown in FIG. 4B, the plated copper 208 of the via hole 105 has a convex shape, and the surface of the plating layer on the substrate surface and the inside of the via hole ( The surface of the plated metal in the portion directly above the via hole cannot be made flush with the surface.

  This hinders the via-on-via that provides a via hole immediately above the via-hole and the chip-on-via that mounts a component directly above the via-hole, and greatly impedes the usefulness of via fill plating.

In FIG. 101, 101 is a core base insulating layer, 102 is a core base conductor layer formed on the core base insulating layer 101, and 103 is a build formed on the surface of the core base insulating layer 101. Up insulation layer is shown.
Kiyoshi Takagi “Build-up multilayer printed circuit board technology”, published by Nikkan Kogyo Shimbun, June 15, 2001, 2nd edition, pages 21-23 Japanese Patent Laid-Open No. 2001-291554

  The problem to be solved by the present invention is to alleviate the unevenness of the portion directly above the via hole generated by applying via fill plating to a substrate mixed with via holes having different via diameters when the via shape varies widely, The surface of the plating layer and the surface of the plated metal inside the via hole (immediately above the via hole) improve the smoothness, and even if the via shape varies widely, or even if there is a mixture of via holes with different via diameters, This is to ensure that components can be mounted on vias or directly above via holes.

  According to the method of forming a via hole in a printed wiring board according to the present invention, plating is performed on the bottomed via hole where the conductor layer is exposed on the insulating layer of the substrate having the conductor layer on at least one side of the insulating layer, and the inside of the via hole is formed. In a via hole forming method by via filling plating filled with plating metal, a drilling step of forming a bottomed via hole in which the conductor layer is exposed in the insulating layer of the substrate, and a surface of the insulating layer and a side surface of the via hole are formed. Forming a conductive layer for feeding power by forming a conductive layer for feeding power; and using the plating feeding conductive layer as a feeding electrode, a plating bath to which at least one of a plating inhibitor or a plating accelerator is added. An electrolytic plating process in which electrolytic plating is performed on the surface and the via hole, and the electrolytic plating process. The substrate surface by vapor metal, etched by a chemical solution that dissolves the plating metal, and a smoothing etching step of reducing the unevenness of the substrate surface.

  In the via hole forming method according to the present invention, the drilling step is a step of forming a plurality of via holes having different diameters. Thereby, via holes having different via diameters are mixed in one substrate.

  The smoothing etching step in the via hole forming method according to the present invention is a step of spraying a chemical solution for dissolving the plating metal onto the substrate surface of the plating metal formed by the plating step.

  In the via hole forming method according to the present invention, the electrolytic plating step performs electrolytic plating of copper, and an aqueous solution containing ferric chloride is used as a chemical solution for dissolving the plating metal in the smoothing etching step.

  In the method of forming a via hole according to the present invention, in the smoothing etching process, etching is performed with a chemical solution that dissolves the plating metal, and the unevenness of the substrate surface is reduced. Therefore, when the via shape varies greatly, or via holes having different via diameters are mixed. Unevenness in the portion immediately above the via hole generated by applying via fill plating to the substrate is alleviated.

  This improves the flatness and smoothness between the surface of the plating layer on the substrate surface and the surface of the plated metal inside the via hole (immediately above the via hole), and when there are large variations in via shapes, or via holes with different via diameters are mixed. Even with this board, it is possible to reliably mount components on vias and via holes.

  One embodiment of a printed wiring board manufacturing method to which a via hole forming method according to the present invention is applied will be described with reference to FIGS.

  As shown in FIG. 1A, a glass epoxy substrate 10 having copper circuits 12 and 13 formed on both surfaces of an insulating layer 11 was prepared as a starting material.

  This substrate is a copper-clad polyimide substrate, copper-clad polyester substrate, copper-clad polyetherimide substrate, copper-clad liquid crystal polymer substrate, glass cloth, crow mat, synthetic fiber, etc. and a copper-clad phenolic substrate made of thermosetting resin A copper-clad paper epoxy substrate, a copper-clad paper polyester substrate, a copper-clad glass polyimide substrate, or the like may be used. Moreover, you may use a multilayer printed wiring board instead of a double-sided printed circuit board.

  Next, as shown in FIG. 1B, epoxy interlayer insulating sheets 14 and 15 were bonded to the front and back surfaces of the glass epoxy substrate 10 to obtain a base material 16.

  The interlayer insulating layer is not limited to the epoxy interlayer insulating sheet, and polyimide, glass epoxy, epoxy-impregnated aramid nonwoven fabric, olefin insulating sheet, and the like can also be used. The insulating layer can be formed not only by a bonding method but also by applying a varnish such as epoxy or polyimide and drying it.

Next, as shown in FIG. 1C, as a drilling step, via holes having different via diameters are formed on each of the epoxy-based interlayer insulating sheets (insulating layers) 14 and 15 of the substrate 16 by a carbon dioxide gas laser. 17, 18 and drilled to remove the smear by _{0 2} plasma irradiation. The via hole 17 had a diameter at the bottom of 100 μm, and the via hole 18 had a diameter at the bottom of 50 μm.

  A carbon dioxide gas laser is used for drilling the via holes 17 and 18, but, of course, a UV-YAG laser or various excimer lasers can also be used. In addition, plasma desmear is applied to the desmear process, but wet desmear using permanganate or the like can also be applied.

  Next, as shown in FIG. 1 (d), as a conductive layer forming process for power feeding, the surfaces of the epoxy-based interlayer insulating sheets (insulating layers) 14 and 15 and the via holes 17 and 18 are formed by chemical copper plating. Conductive layers 19 and 20 for plating power supply are provided on the inner surface. Then, as an electrolytic plating process, the entire substrate is immersed in a plating bath for via fill containing the conductive layers 19 and 20 for feeding power as feeding electrodes and an inhibitor and an accelerator based on a sulfur compound as additives. Went.

  This electrolytic copper plating was completed by supplying power for a time during which the portion directly above the via hole 17 having a via diameter of 100 μm was substantially smooth from the periphery thereof.

  At this time, the plating thickness of the plated copper 21 and 22 on the substrate surface is about 17 μm, and the surface 23A of the plated copper 23 filled in the via hole 17 and the surfaces 21A and 22A of the plated copper 21 and 22 are flush with each other. became.

  On the other hand, the via hole 18 with a via diameter of 50 μm has a smaller volume than the via hole 17 with a via diameter of 100 μm, and thus has an excessive via fill plating shape. The plated copper 24 filled in the via hole 18 is composed of plated copper 21, It became the shape containing the protrusion-shaped part 25 which protruded about 5 micrometers from the surface 21A of 22 and 22A.

Next, as a smoothing etching step, as shown by an arrow E in FIG. 1 (e), an aqueous solution containing ferric chloride (FeCl ₃ ) is sprayed on the surface of the substrate in a straight line. The flat part of the surface (the parts of the plated copper 21 and 22 on the substrate surface) was etched by about 8 μm.

  In this etching, the protrusion-shaped portion 25 of the plated copper 24 filled in the via hole 18 has a larger area in contact with the etching solution than the flat portion (the surfaces 21A and 22A of the plated copper 21 and 22), so that the etching is not performed. Progressing preferentially, the protrusions of the protrusion-shaped portion 25 could be reduced to within 2 μm. FIG. 1F shows the state after the smoothing etching.

  Next, as shown in FIG. 1 (g), the plated copper (copper foils) 21 and 22 and the plating power supply conductive layers 19 and 20 on the substrate surface are etched, and circuit formation is performed by a subtractive method. A wiring board 30 was obtained.

  As described above, since the convex portion (projection shape portion 25) on the substrate surface is reduced by the smoothing etching step, the surface of the plating layer on the substrate surface is flush with the surface of the plated metal inside the via hole (a portion immediately above the via hole). Smoothness is improved, and it is possible to mount a component on a via-on-via or just above a via hole even when the via shape has a large variation, or even on a board in which via holes 17 and 18 having different via diameters are mixed.

  Another embodiment of the method for manufacturing a printed wiring board to which the via hole forming method according to the present invention is applied will be described with reference to FIGS.

  As shown in FIG. 2A, a glass epoxy substrate 50 having copper circuits 52 and 53 formed on both surfaces of an insulating layer 51 was prepared as a starting material.

  This substrate is also copper-clad polyimide substrate, copper-clad polyester substrate, copper-clad polyetherimide substrate, copper-clad liquid crystal polymer substrate, glass cloth, crow mat, synthetic fiber, etc. and copper-clad phenolic substrate made of thermosetting resin A copper-clad paper epoxy substrate, a copper-clad paper polyester substrate, a copper-clad glass polyimide substrate, or the like can be used. Moreover, you may use a multilayer printed wiring board instead of a double-sided printed circuit board.

  Next, as shown in FIG. 2B, epoxy-based interlayer insulating sheets 54 and 55 were bonded to the front and back surfaces of the glass epoxy substrate 50 to obtain a base material 56.

  The interlayer insulating layer is not limited to the epoxy interlayer insulating sheet, and polyimide, glass epoxy, epoxy-impregnated aramid nonwoven fabric, olefin insulating sheet, and the like can be used. The insulating layer can be formed not only by a bonding method but also by applying a varnish such as epoxy or polyimide and drying it.

Next, as shown in FIG. 2C, as a drilling step, via holes having different via diameters are formed on each of the epoxy-based interlayer insulating sheets (insulating layers) 54 and 55 of the base material 56 by a carbon dioxide gas laser. 57 and 58 drilled to remove the smear by _{0 2} plasma irradiation. The via hole 57 had a diameter at the bottom of 100 μm, and the via hole 58 had a diameter at the bottom of 50 μm.

  A carbon dioxide gas laser is used for drilling the via holes 57 and 58, but it is of course possible to use a UV-YAG laser or various excimer lasers. In addition, plasma desmear is applied to the desmear process, but wet desmear using permanganate or the like can also be applied.

  Next, as shown in FIG. 2 (d), the surface of each of the epoxy-based interlayer insulating sheets (insulating layers) 54 and 55 and the via holes 57 and 58 are formed by chemical copper plating as a conductive layer forming process for feeding. Conductive layers 59 and 60 for plating power supply are provided on the inner surface. Thereafter, as an electrolytic plating process, the entire substrate is immersed in a plating bath for via fill containing conductive layers 59 and 60 for feeding power as feeding electrodes and an inhibitor and an accelerator based on a sulfur compound as additives. Went.

  This electrolytic copper plating was completed by supplying power for a time period in which the portion directly above the via hole 58 having a via diameter of 50 μm was substantially smooth from the periphery thereof.

  At this time, the plating thickness of the plated copper 61 and 62 on the substrate surface is about 12 μm, and the surface 64A of the plated copper 64 filled in the via hole 58 and the surfaces 61A and 62A of the plated copper 61 and 62 are flush with each other. became.

  On the other hand, the via hole 57 having a via diameter of 100 μm has a larger volume than the via hole 58 having a via diameter of 50 μm, and thus has a deficient via fill plating shape, and the plated copper 63 filled in the via hole 57 includes plated copper 61, It became the shape containing the recessed shape part 65 which protruded about 3 micrometers from the surface 61A of 62, 62A.

Next, as a smoothing etching step, an aqueous solution containing ferric chloride (FeCl ₃ ) is sprayed on the substrate surface as shown by an arrow E in FIG. A flat portion on the surface (plated copper 61 and 62 portions on the substrate surface) was etched by about 5 μm.

  As the etching solution for this etching, the one having a higher specific gravity and higher viscosity than the case of the first embodiment is used, so that the diffusion (mass transfer) of the etching solution in the recessed portion 65 hardly occurs, and the recessed portion Etching of the flat portions (surfaces 61A and 62A of the plated copper 61 and 62) proceeded preferentially as compared to 65, and the dents of the concave-shaped portions 65 could be reduced to within 2 μm. FIG. 2F shows a state after the smoothing etching.

  Next, as shown in FIG. 2 (g), the plated copper (copper foil) 61 and 62 and the plating power supply conductive layers 59 and 60 on the surface of the substrate are etched, and a circuit is formed by a subtractive method. A wiring board 70 was obtained.

  As described above, since the concave portion (concave portion 65) on the substrate surface is reduced by the smoothing etching step, the surface of the plating layer on the substrate surface is flush with the surface of the plated metal inside the via hole (portion directly above the via hole). The smoothness is improved, and it is possible to mount a component on a via-on-via or just above the via hole even when the via shape has a large variation, or even on a substrate in which via holes 57 and 58 having different via diameters are mixed.

(A)-(g) is process drawing which shows typically one Embodiment of the manufacturing method of the printed wiring board to which the formation method of the via hole using via fill plating by this invention is applied. (A)-(g) is process drawing which shows typically other embodiment of the manufacturing method of the printed wiring board to which the formation method of the via hole using via fill plating by this invention is applied. It is a longitudinal cross-sectional view which shows the via hole shape of a general buildup multilayer wiring board. (A), (b) is a longitudinal cross-sectional view which shows the prior art example of the via hole which each uses via fill plating.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Glass epoxy board | substrate 11 Insulation layer 12, 13 Copper circuit 14, 15 Epoxy-type interlayer insulation sheet 16 Base material 17, 18 Via hole 19, 20 Plating electrically-conductive layer 21, 22, 23, 24 Plating copper 25 Protrusion shape part 30 Multilayer Printed circuit board 50 Glass epoxy board 51 Insulating layer 52, 53 Copper circuit 54, 55 Epoxy interlayer insulating sheet 56 Base material 57, 58 Via hole 59, 60 Plating power supply conductive layer 61, 62, 63, 64 Plating copper 65 Concave part 70 Multilayer printed circuit board

Claims (4)

A via hole forming method by via filling plating in which a bottomed via hole in which the conductor layer is exposed is plated on the insulating layer of a substrate having a conductor layer on at least one side of the insulating layer, and the via hole is filled with a plating metal In
Forming a bottomed via hole in which the conductor layer is exposed in the insulating layer of the substrate;
Forming a conductive layer for feeding power on the surface of the insulating layer and the side surface of the via hole;
An electroplating step of performing electroplating on the surface of the insulating layer and the via hole by a plating bath to which at least one of a plating inhibitor or a plating accelerator is added using the conductive layer for plating power supply as a power supply electrode;
Etching the substrate surface with the plating metal formed by the electrolytic plating step with a chemical solution that dissolves the plating metal, and a smoothing etching step for reducing irregularities on the substrate surface,
A via hole forming method including:   The via hole forming method according to claim 1, wherein the drilling step is a via filling plating which is a step of forming a plurality of via holes having different diameters.   The via hole forming method according to claim 1, wherein the smoothing etching step is a step of spraying a chemical solution for dissolving the plating metal onto the substrate surface by the plating metal formed by the plating step. The via hole forming method according to any one of claims 1 to 3, wherein the electrolytic plating step performs electrolytic plating of copper, and an aqueous solution containing ferric chloride is used as a chemical solution for dissolving the plating metal in the smoothing etching step.

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