KR910010644A - 콘택홀의 패턴 형성 방법 - Google Patents

콘택홀의 패턴 형성 방법 Download PDF

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Publication number
KR910010644A
KR910010644A KR1019890017555A KR890017555A KR910010644A KR 910010644 A KR910010644 A KR 910010644A KR 1019890017555 A KR1019890017555 A KR 1019890017555A KR 890017555 A KR890017555 A KR 890017555A KR 910010644 A KR910010644 A KR 910010644A
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KR
South Korea
Prior art keywords
sog film
forming
photoresist
contact hole
pattern
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Application number
KR1019890017555A
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English (en)
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KR920010129B1 (ko
Inventor
문승찬
Original Assignee
정몽헌
현대전자산업 주식회사
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Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019890017555A priority Critical patent/KR920010129B1/ko
Priority to US07/619,033 priority patent/US5157002A/en
Priority to JP2341157A priority patent/JPH0722163B2/ja
Publication of KR910010644A publication Critical patent/KR910010644A/ko
Application granted granted Critical
Publication of KR920010129B1 publication Critical patent/KR920010129B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

콘택홀의 패턴 형성 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명에 의한 공정 방법으로 콘택홀의 패턴을 형성하는 상태의 단면도.

Claims (6)

  1. 고집적 반도체 제조의 콘택홀 패턴형성 방법에 있어서, 실리콘 기판 상부에 1차 패턴을 형성하고 노출된 전영역 상부에 절연층을 형성하는 단계와, 상기 절연층 상부에 질화막 SOG막 및 포토레지스트를 순차적으로 각 소정 두께 형성하는 단계와 , 콘택홀이 형성될 부분의 포토레지스트만 남기고 다른 부분의 포토레지스트는 모두 제거한 다음, 포토레스트가 제거된 부분의 SOG막을 제거하는 단계와 남아있는 포토레지스트는 모두 제거한 다음 다시 젼영역 상분에 포토레지스트를 상기 SOG막 보다 높은 두께로 형성한 후, 건식식각 공정으로 상기 SOG막이 노출되기까지 포토레지스트를 제거하는 단계와, 상기 공정 후 포토레지스트를의 표면을 경화시킨 후 식각공정에 의해 잔존하는 SOG막을 제거하여 콘택홀의 패턴을 형성하여, 그로 인하여 미세한 콘택홀의 패턴을 해상도 높이고 또한 단차가 심한 영역에서도 SOG막의 평탄화 효과를 이용하여 미세한 코낵홀의 패턴을 정확하게 형성할수 있도록 한 것을 특징으로 하는 콘택홀의 패턴 형성 공정 방법.
  2. 제1항에 있어서, 상기 절연층 상부에 질화막, SOG막 포토레지스트를 순차적으로 각각 소정 두께 형성하는 단계는 , 상기 질화막은 200내지 300Å정도로 형성하고, 상기 SOG막은 1.0㎛이상으로 도포하고, 상기 포토레지스트는 1.0내지 1.5㎛로 도포하는 것을 특징으로하는 콘택홀의 패턴 형성 공정방법.
  3. 제1또는 제2항에 있어서, 상기의 SOG막을 소정 두께 형성한 후 핫프레이트에서 200℃에서 1분동안 굽기 공정을 실시한 것을 특징으로 하는 콘택홀의 패턴 형성공정방법.
  4. 제3항에 있어서, 상기의 SOG막을 소정 두께 형성한 후 , 대류오븐을 사용하여 200℃에서 30분 동안 굽기공정을 실시하는 것을 포함하는 것을 특징으로 하는 콘택홀의 패턴 형성공정방법.
  5. 제 1항에 있어서, 포토레지스트가 제거된 부분위 SOG막을 제거하는 단계는, 불소개스를 분위기로한 건식식각으로 SOG막 하부의 질화막층을 식각 정지점으로 설정한 후 노출된 SOG 막을 식각하는 것을 특징으로 하는 콘택홀의 패턴 형성 공정방법.
  6. 제1항에 있어서, 상기SOG막이 노출되기 까지 포토레지스트를 제거하는 단계는 RIE 또는 현상액에 의해 전 표면식각하는 것을 특징으로 하는 콘택홀의 패턴 형성공정방법
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890017555A 1989-11-30 1989-11-30 콘택홀의 패턴형성방법 KR920010129B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019890017555A KR920010129B1 (ko) 1989-11-30 1989-11-30 콘택홀의 패턴형성방법
US07/619,033 US5157002A (en) 1989-11-30 1990-11-28 Method for forming a mask pattern for contact hole
JP2341157A JPH0722163B2 (ja) 1989-11-30 1990-11-29 コンタクトホール用マスクパターン形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890017555A KR920010129B1 (ko) 1989-11-30 1989-11-30 콘택홀의 패턴형성방법

Publications (2)

Publication Number Publication Date
KR910010644A true KR910010644A (ko) 1991-06-29
KR920010129B1 KR920010129B1 (ko) 1992-11-16

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KR1019890017555A KR920010129B1 (ko) 1989-11-30 1989-11-30 콘택홀의 패턴형성방법

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US (1) US5157002A (ko)
JP (1) JPH0722163B2 (ko)
KR (1) KR920010129B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5298463A (en) * 1991-08-30 1994-03-29 Micron Technology, Inc. Method of processing a semiconductor wafer using a contact etch stop
US5723381A (en) * 1995-09-27 1998-03-03 Siemens Aktiengesellschaft Formation of self-aligned overlapping bitline contacts with sacrificial polysilicon fill-in stud
TW352471B (en) * 1997-09-20 1999-02-11 United Microelectronics Corp Method for preventing B-P-Si glass from subsiding
US6235545B1 (en) 1999-02-16 2001-05-22 Micron Technology, Inc. Methods of treating regions of substantially upright silicon-comprising structures, method of treating silicon-comprising emitter structures, methods of forming field emission display devices, and cathode assemblies
US6358856B1 (en) * 2000-11-21 2002-03-19 Advanced Micro Devices, Inc. Bright field image reversal for contact hole patterning
US6506673B2 (en) * 2001-06-11 2003-01-14 Agere Systems Guardian Corp. Method of forming a reverse gate structure with a spin on glass process

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220952A (ja) * 1983-05-31 1984-12-12 Toshiba Corp 半導体装置の製造方法
US4764484A (en) * 1987-10-08 1988-08-16 Standard Microsystems Corporation Method for fabricating self-aligned, conformal metallization of semiconductor wafer
JP2680358B2 (ja) * 1988-07-20 1997-11-19 株式会社東芝 半導体素子の製造方法
IT1225624B (it) * 1988-10-20 1990-11-22 Sgs Thomson Microelectronics Procedimento per formare contatti metallo-semiconduttore autoallineatiin dispositivi integrati contenenti strutture misfet

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Publication number Publication date
KR920010129B1 (ko) 1992-11-16
JPH0722163B2 (ja) 1995-03-08
US5157002A (en) 1992-10-20
JPH03240231A (ja) 1991-10-25

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