KR900019171A - 나이트라이드 층으로 전도층을 덮어 반도체 소자를 제조하는 방법 - Google Patents

나이트라이드 층으로 전도층을 덮어 반도체 소자를 제조하는 방법 Download PDF

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KR900019171A
KR900019171A KR1019900007242A KR900007242A KR900019171A KR 900019171 A KR900019171 A KR 900019171A KR 1019900007242 A KR1019900007242 A KR 1019900007242A KR 900007242 A KR900007242 A KR 900007242A KR 900019171 A KR900019171 A KR 900019171A
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layer
region
forming
gate
covering
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KR1019900007242A
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에스.왕 마틴
치우 광이
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디. 크레이그 노드런드
휴렛트 팩카드 캄파니
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Publication of KR900019171A publication Critical patent/KR900019171A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

나이트라이드 층으로 전도층을 덮어 반도체 소자를 제조하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제8도는 나이트라이드를 제거하기 위해 에칭하고 고온에서 어닐링 한 후의 제7도의 소자를 도시한 도면.

Claims (9)

  1. 기판의 플레이너 표면에 공간적으로 이격된 제1 및 제2필드 산화물 영역을 형성하는 단계와: 상기 필드 산화물영역들 사이에 게이트 영역을 생성하는 단계와: 상기 게이트영역 및 상기 제1필드 산화물 영역 사이에 소스확산영역을 형성하고 상기 게이트영역 및 상기 제2필드 산화물영역 사이에 트레인 영역을 형성하는 단계와: 전도층으로 상기 기판울 덮는 단계와: 나이트라이드 층으로 상기 전도층을 덮는 단계와: 저온에서 어닐링하여 실리콘상부의 상기 전도층 접합부가 상기 실리콘과 반응하여 실리콘 화합물을 형성하고, 상기 전도층의 어떤 나머지 부분이 상기 나이트 라이드 층과 반응하여 소자를 덮는 대략 균질의 나이트 라이드 층울 형성하는 단계와: 에칭하여 상기 나이트 라이드 층을 제거하는 단계와: 고온에서 어닐링하여 상기 실리콘 화합물을 실리사이드로 변환하는 단계를 포함하는 반도체 소자 제조방법.
  2. 제1항에 있어서, 상기 전도층이 티타늄을 포함하여 상기 나이트라이드 층이 티타늄 나이트라이드를 포함하는 방법.
  3. 제2항에 있어서, 티타늄 나이트라이드 피막이 순환기체의 어떠한 변화없이 상기 티타늄 피복직후에 도포되는 방법.
  4. 제1항에 있어서, 상기 에칭이 습식 에칭을 포함하는 방법.
  5. 제4항에 있어서, 상기 습식에칭이 황산에 의해 수행되는 방법.
  6. 제4항에 있어서, 상기 습식에칭이 수산화 암모늄에 의해 수행되는 방법.
  7. 제1항에 있어서, 상기 게이트영역을 생성하는 단계와 상기 기판의 플레이너 표면에 게이트 산화층을 형성하는 단계와, 상기 게이트 영역을 생성하기 위해 상기 게이트산화층에 실리콘패드를 형성하는 단계를 포함하는 방법.
  8. 제7항에 있어서, 상기 확산영역을 형성하는 단계가 : 유전제층으로 상기 패드 및 상기 기판을 피복하는 단계와: 상기 유전층을 지향성 에칭을 하여 상기 패드 주위에 산화물 스페이서를 제공하는 단계와: 이온주입과 드라이브-인을 수행하여 확산영역을 형성하는 단계를 포함하는 방법.
  9. 제7항에 있어서, 상기 패드를 형성하는 단계가 상기 게이트 산화물상에 폴리실리콘 층을 형성하고 그 다음 상기 폴리실리콘층 및 그 하부의 게이트 산화물을 에칭하는 단계를 포함하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900007242A 1989-05-22 1990-05-21 나이트라이드 층으로 전도층을 덮어 반도체 소자를 제조하는 방법 KR900019171A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/356,021 US4923822A (en) 1989-05-22 1989-05-22 Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer
US356,021 1989-05-22

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KR900019171A true KR900019171A (ko) 1990-12-24

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US (1) US4923822A (ko)
EP (1) EP0399141B1 (ko)
JP (1) JPH034527A (ko)
KR (1) KR900019171A (ko)
DE (1) DE69011203T2 (ko)
SG (1) SG10095G (ko)

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EP0399141B1 (en) 1994-08-03
SG10095G (en) 1995-06-16
EP0399141A3 (en) 1991-10-30
EP0399141A2 (en) 1990-11-28
JPH034527A (ja) 1991-01-10
US4923822A (en) 1990-05-08
DE69011203D1 (de) 1994-09-08
DE69011203T2 (de) 1995-03-16

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