KR900012355A - 반도체장치 패키지 - Google Patents

반도체장치 패키지

Info

Publication number
KR900012355A
KR900012355A KR1019900001013A KR900001013A KR900012355A KR 900012355 A KR900012355 A KR 900012355A KR 1019900001013 A KR1019900001013 A KR 1019900001013A KR 900001013 A KR900001013 A KR 900001013A KR 900012355 A KR900012355 A KR 900012355A
Authority
KR
South Korea
Prior art keywords
semiconductor device
device package
package
semiconductor
Prior art date
Application number
KR1019900001013A
Other languages
English (en)
Other versions
KR930009012B1 (ko
Inventor
히로미치 사와야
Original Assignee
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 도시바 filed Critical 가부시키가이샤 도시바
Publication of KR900012355A publication Critical patent/KR900012355A/ko
Application granted granted Critical
Publication of KR930009012B1 publication Critical patent/KR930009012B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
KR1019900001013A 1989-01-30 1990-01-30 반도체장치 패키지 KR930009012B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1020212A JPH02201949A (ja) 1989-01-30 1989-01-30 半導体装置
JP1-20212 1989-01-30

Publications (2)

Publication Number Publication Date
KR900012355A true KR900012355A (ko) 1990-08-03
KR930009012B1 KR930009012B1 (ko) 1993-09-18

Family

ID=12020860

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900001013A KR930009012B1 (ko) 1989-01-30 1990-01-30 반도체장치 패키지

Country Status (4)

Country Link
US (1) US5093713A (ko)
EP (1) EP0381054A3 (ko)
JP (1) JPH02201949A (ko)
KR (1) KR930009012B1 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5170312A (en) * 1991-11-04 1992-12-08 Motorola, Inc. Protection circuit on a lead of a power device
DE59402033D1 (de) * 1993-09-30 1997-04-17 Siemens Ag Zweipoliges SMT-Miniatur-Gehäuse für Halbleiterbauelemente und Verfahren zu dessen Herstellung
KR0155843B1 (ko) * 1995-07-07 1998-12-01 이대원 반도체장치
EP1566846B1 (de) * 1997-07-29 2016-02-03 OSRAM Opto Semiconductors GmbH Optoelektronisches Bauelement
GB2338827B (en) * 1998-06-27 2002-12-31 Motorola Gmbh Electronic package assembly
DE10125697B4 (de) 2001-05-25 2019-01-03 Infineon Technologies Ag Leistungshalbleitermodul und Verfahren zum Herstellen eines Leistungshalbleitermoduls
TW488054B (en) * 2001-06-22 2002-05-21 Advanced Semiconductor Eng Semiconductor package for integrating surface mount devices
DE10149774A1 (de) * 2001-10-09 2003-04-24 Bosch Gmbh Robert Verfahren zum Verpacken von elektronischen Baugruppen und Mehrfachchipverpackung
JP4100332B2 (ja) * 2003-11-12 2008-06-11 株式会社デンソー 電子装置およびその製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1614865A1 (de) * 1967-09-27 1970-12-23 Telefunken Patent Optoelektronische Halbleiteranordnung
US3715633A (en) * 1971-07-15 1973-02-06 J Nier Semiconductor unit with integrated circuit
US3935501A (en) * 1975-02-13 1976-01-27 Digital Components Corporation Micro-miniature light source assemblage and mounting means therefor
DE2510982A1 (de) * 1975-03-13 1976-09-30 Bosch Gmbh Robert Hybrides halbleiterbauelement
DE2610136A1 (de) * 1976-03-11 1977-09-22 Bosch Gmbh Robert Spannungsregler fuer generatoren
US4203792A (en) * 1977-11-17 1980-05-20 Bell Telephone Laboratories, Incorporated Method for the fabrication of devices including polymeric materials
JPS5753947A (en) * 1980-09-17 1982-03-31 Hitachi Ltd Transistor and electronic device containing it
JPS6041249A (ja) * 1983-08-17 1985-03-04 Nec Corp 混成集積回路装置
DE3540551C1 (en) * 1984-06-01 1990-02-15 Piller Gmbh Co Kg Anton Semiconductor module for fast switching arrangement
IT1221585B (it) * 1987-05-18 1990-07-12 S G S Microelettronica Spa Ora Circuito modulare a piu' piastrine a semiconduttore in capsulato in resina,e relativo procedimento di fabbrivazione
IT1222152B (it) * 1987-07-28 1990-09-05 Sgs Microelettronica Spa Dispositivo a piu' piastrine di materiale in contenitore di metallo e resina
US4783428A (en) * 1987-11-23 1988-11-08 Motorola Inc. Method of producing a thermogenetic semiconductor device
GB2219435B (en) * 1988-06-02 1991-07-03 Burr Brown Corp Plastic encapsulated multichip hybrid integrated circuit

Also Published As

Publication number Publication date
KR930009012B1 (ko) 1993-09-18
US5093713A (en) 1992-03-03
JPH02201949A (ja) 1990-08-10
EP0381054A3 (en) 1993-03-31
EP0381054A2 (en) 1990-08-08

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030901

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee