DE69030863D1 - Halbleiterspeicheranordnung - Google Patents
HalbleiterspeicheranordnungInfo
- Publication number
- DE69030863D1 DE69030863D1 DE69030863T DE69030863T DE69030863D1 DE 69030863 D1 DE69030863 D1 DE 69030863D1 DE 69030863 T DE69030863 T DE 69030863T DE 69030863 T DE69030863 T DE 69030863T DE 69030863 D1 DE69030863 D1 DE 69030863D1
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/108—Wide data ports
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1292996A JPH0693484B2 (ja) | 1989-11-10 | 1989-11-10 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69030863D1 true DE69030863D1 (de) | 1997-07-10 |
DE69030863T2 DE69030863T2 (de) | 1997-11-06 |
Family
ID=17789127
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69030863T Expired - Fee Related DE69030863T2 (de) | 1989-11-10 | 1990-11-09 | Halbleiterspeicheranordnung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5173875A (de) |
EP (1) | EP0427284B1 (de) |
JP (1) | JPH0693484B2 (de) |
KR (1) | KR930010104B1 (de) |
DE (1) | DE69030863T2 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5321658A (en) * | 1990-05-31 | 1994-06-14 | Oki Electric Industry Co., Ltd. | Semiconductor memory device being coupled by auxiliary power lines to a main power line |
KR100231393B1 (ko) * | 1991-04-18 | 1999-11-15 | 나시모토 류조 | 반도체집적회로장치 |
JP3236105B2 (ja) * | 1993-03-17 | 2001-12-10 | 富士通株式会社 | 不揮発性半導体記憶装置及びその動作試験方法 |
KR0170906B1 (ko) * | 1995-11-01 | 1999-03-30 | 김주용 | 반도체 기억장치의 파워라인 커플링 방지 회로 |
JP2002208275A (ja) * | 2001-01-11 | 2002-07-26 | Matsushita Electric Ind Co Ltd | 半導体集積回路およびその検査方法 |
KR100562497B1 (ko) * | 2003-01-22 | 2006-03-21 | 삼성전자주식회사 | 디커플링 커패시터를 포함하는 반도체 메모리 장치 |
KR101211683B1 (ko) * | 2008-12-31 | 2012-12-12 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3621302A (en) * | 1969-01-15 | 1971-11-16 | Ibm | Monolithic-integrated semiconductor array having reduced power consumption |
JPS59169166A (ja) * | 1983-03-16 | 1984-09-25 | Hitachi Ltd | 半導体装置 |
US4727518A (en) * | 1984-02-17 | 1988-02-23 | Intel Corporation | Apparatus for limiting minority carrier injection in CMOS memories |
JPH02303153A (ja) * | 1989-05-18 | 1990-12-17 | Seiko Epson Corp | 半導体集積回路 |
US5045726A (en) * | 1990-05-16 | 1991-09-03 | North American Philips Corporation | Low power programming circuit for user programmable digital logic array |
-
1989
- 1989-11-10 JP JP1292996A patent/JPH0693484B2/ja not_active Expired - Lifetime
-
1990
- 1990-11-08 US US07/610,587 patent/US5173875A/en not_active Expired - Lifetime
- 1990-11-09 EP EP90121467A patent/EP0427284B1/de not_active Expired - Lifetime
- 1990-11-09 DE DE69030863T patent/DE69030863T2/de not_active Expired - Fee Related
- 1990-11-10 KR KR1019900018175A patent/KR930010104B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR930010104B1 (ko) | 1993-10-14 |
JPH03153066A (ja) | 1991-07-01 |
DE69030863T2 (de) | 1997-11-06 |
EP0427284B1 (de) | 1997-06-04 |
KR910010705A (ko) | 1991-06-29 |
JPH0693484B2 (ja) | 1994-11-16 |
US5173875A (en) | 1992-12-22 |
EP0427284A3 (en) | 1992-03-04 |
EP0427284A2 (de) | 1991-05-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |