KR900004631B1 - 반도체 메모리 - Google Patents

반도체 메모리 Download PDF

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Publication number
KR900004631B1
KR900004631B1 KR1019850008167A KR850008167A KR900004631B1 KR 900004631 B1 KR900004631 B1 KR 900004631B1 KR 1019850008167 A KR1019850008167 A KR 1019850008167A KR 850008167 A KR850008167 A KR 850008167A KR 900004631 B1 KR900004631 B1 KR 900004631B1
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KR
South Korea
Prior art keywords
sub
sense amplifier
array
arrays
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019850008167A
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English (en)
Korean (ko)
Other versions
KR860004406A (ko
Inventor
쓰네오 마쓰무라
쓰네오 마노
준조 야마다
준이찌 이노우에
Original Assignee
닛뽕텔리그래프앤드델리포운코오포레이숀
신또 히사시
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 닛뽕텔리그래프앤드델리포운코오포레이숀, 신또 히사시 filed Critical 닛뽕텔리그래프앤드델리포운코오포레이숀
Publication of KR860004406A publication Critical patent/KR860004406A/ko
Application granted granted Critical
Publication of KR900004631B1 publication Critical patent/KR900004631B1/ko
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
KR1019850008167A 1984-11-02 1985-11-02 반도체 메모리 Expired KR900004631B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP59232083A JPS61110459A (ja) 1984-11-02 1984-11-02 半導体メモリ
JP59-232083 1984-11-02
JP232083 1985-11-02

Publications (2)

Publication Number Publication Date
KR860004406A KR860004406A (ko) 1986-06-20
KR900004631B1 true KR900004631B1 (ko) 1990-06-30

Family

ID=16933726

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850008167A Expired KR900004631B1 (ko) 1984-11-02 1985-11-02 반도체 메모리

Country Status (5)

Country Link
US (1) US4694428A (enExample)
JP (1) JPS61110459A (enExample)
KR (1) KR900004631B1 (enExample)
DE (1) DE3538530A1 (enExample)
GB (1) GB2166592B (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254461A (ja) * 1985-09-03 1987-03-10 Toshiba Corp 半導体記憶装置
US4980860A (en) * 1986-06-27 1990-12-25 Texas Instruments Incorporated Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry
JP2511415B2 (ja) * 1986-06-27 1996-06-26 沖電気工業株式会社 半導体装置
JPS6367771A (ja) * 1986-09-09 1988-03-26 Mitsubishi Electric Corp 半導体記憶装置
JPH0775116B2 (ja) * 1988-12-20 1995-08-09 三菱電機株式会社 半導体記憶装置
JPH02246099A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 大規模半導体集積回路装置とその欠陥救済法
JPH07114077B2 (ja) * 1989-06-01 1995-12-06 三菱電機株式会社 不揮発性半導体記憶装置
JP2515037B2 (ja) * 1990-05-14 1996-07-10 シャープ株式会社 半導体メモリ
JP2564695B2 (ja) * 1990-09-14 1996-12-18 富士通株式会社 半導体記憶装置
KR930008310B1 (ko) * 1991-02-05 1993-08-27 삼성전자 주식회사 반도체 메모리장치의 워드라인드라이버단 배치방법
US5652723A (en) 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
JP3150747B2 (ja) * 1992-02-24 2001-03-26 株式会社リコー 半導体メモリ装置とその製造方法
US5303196A (en) * 1992-05-22 1994-04-12 International Business Machines Corporation Open bit line memory devices and operational method
JPH0827715B2 (ja) * 1993-03-03 1996-03-21 日本電気株式会社 記憶装置
KR100253012B1 (ko) * 1993-08-26 2000-04-15 사와무라 시코 반도체 메모리 장치
DE69322384T2 (de) * 1993-09-10 1999-05-12 Stmicroelectronics S.R.L., Agrate Brianza, Mailand/Milano Herstellungsverfahren einer Zenerdiode für Flash-EEPROM Bauteile
JPH0798979A (ja) * 1993-09-29 1995-04-11 Toshiba Corp 半導体記憶装置
JPH07230696A (ja) * 1993-12-21 1995-08-29 Toshiba Corp 半導体記憶装置
US5506816A (en) * 1994-09-06 1996-04-09 Nvx Corporation Memory cell array having compact word line arrangement
KR0140097B1 (ko) * 1994-11-30 1998-07-15 김광호 읽기변환쓰기기능을 가지는 메모리 모듈
US5606529A (en) * 1994-12-20 1997-02-25 Hitachi, Ltd. Semiconductor disk storage
US5636158A (en) * 1995-03-13 1997-06-03 Kabushiki Kaisha Toshiba Irregular pitch layout for a semiconductor memory device
US5546349A (en) * 1995-03-13 1996-08-13 Kabushiki Kaisha Toshiba Exchangeable hierarchical data line structure
US5600603A (en) * 1995-08-22 1997-02-04 Intel Corporation Common centroid differential sensing scheme
KR970051170A (ko) * 1995-12-29 1997-07-29 김주용 메모리 셀 어레이 및 그를 이용한 프로그램 방법
US6381166B1 (en) * 1998-09-28 2002-04-30 Texas Instruments Incorporated Semiconductor memory device having variable pitch array
US7184290B1 (en) * 2000-06-28 2007-02-27 Marvell International Ltd. Logic process DRAM
TW449885B (en) 2000-07-13 2001-08-11 Nanya Technology Corp Arrangement of DRAM cells with vertical transistors and deep trench capacitors
KR100706233B1 (ko) * 2004-10-08 2007-04-11 삼성전자주식회사 반도체 기억 소자 및 그 제조방법
KR100886353B1 (ko) * 2007-04-02 2009-03-03 삼성전자주식회사 이중 패터닝 기술을 사용한 반도체 메모리 장치 및 그레이아웃 방법
US8064255B2 (en) * 2007-12-31 2011-11-22 Cypress Semiconductor Corporation Architecture of a nvDRAM array and its sense regime
US8059458B2 (en) * 2007-12-31 2011-11-15 Cypress Semiconductor Corporation 3T high density nvDRAM cell

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601710B2 (ja) * 1979-09-03 1985-01-17 株式会社日立製作所 半導体メモリ
JPS57198592A (en) * 1981-05-29 1982-12-06 Hitachi Ltd Semiconductor memory device
JPS58111183A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd ダイナミツクｒａｍ集積回路装置
JPS59161061A (ja) * 1983-02-10 1984-09-11 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
DE3538530A1 (de) 1986-05-07
GB8526977D0 (en) 1985-12-04
US4694428A (en) 1987-09-15
GB2166592B (en) 1988-01-06
KR860004406A (ko) 1986-06-20
DE3538530C2 (enExample) 1988-01-21
JPH0377668B2 (enExample) 1991-12-11
JPS61110459A (ja) 1986-05-28
GB2166592A (en) 1986-05-08

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