KR900000767A - 순서 선택 우선의 임의/순서 선택회로 - Google Patents

순서 선택 우선의 임의/순서 선택회로 Download PDF

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Publication number
KR900000767A
KR900000767A KR1019880008111A KR880008111A KR900000767A KR 900000767 A KR900000767 A KR 900000767A KR 1019880008111 A KR1019880008111 A KR 1019880008111A KR 880008111 A KR880008111 A KR 880008111A KR 900000767 A KR900000767 A KR 900000767A
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KR
South Korea
Prior art keywords
selection
order selection
flip
order
random
Prior art date
Application number
KR1019880008111A
Other languages
English (en)
Other versions
KR950009681B1 (ko
Inventor
배종곤
Original Assignee
이만용
금성반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이만용, 금성반도체 주식회사 filed Critical 이만용
Priority to KR1019880008111A priority Critical patent/KR950009681B1/ko
Priority to US07/372,605 priority patent/US5003201A/en
Priority to JP1168280A priority patent/JPH02118801A/ja
Publication of KR900000767A publication Critical patent/KR900000767A/ko
Application granted granted Critical
Publication of KR950009681B1 publication Critical patent/KR950009681B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/15033—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of bistable devices

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Multi-Process Working Machines And Systems (AREA)

Abstract

내용 없음

Description

순서 선택 우선의 임의/순서 선택회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 종래의 임의 선택 회로도.
제2도는 종래의 순서 선택 회로도.
제5도는 본 발명에 따른 순서 선택 우선의 임의 선택과 순서 선택을 겸한 회로도.

Claims (1)

  1. 임의 선택과 순서 겸용 회로에 있어서, 클럭 펄스는 임의 선택과 순서 선택 절환용 스위치(Sn+1)의 제어를 받는 트랜스미션 케이트(T1,T4,…Tk)를 통해 플립플롭(F1-Fn)의 클럭단에 인가되고, 임의 선택시 전원(VDD)이 트랜스미션 케이트(T2,T5,…Tk+1)를 통해 플립플롭(F1-Fn)클럭단에 인가되어 순서 선택 동작 중 상태가 유지되도록 되며, 각 플립플롭(F1-Fn)의 출력은 상기 스위치SN+1)에 의해 제어되는 트랜스미션 케이트(T3,T6,…Tk+1)를 통해 2진해독기(1)의 각 입력단에 인가되도록 되는 동시에 다음단의 플립플롭의 클럭단에 인가되도록 되고, 2진 해독기기(1)의 입력단은 임의 선택을 위한 스위치(S1-Sn)에 각각 접속되어 임의 선택후 이전의 순서 선택을 계속 행할 수 있는 것을 특징으로 하는 순서선택 우선의 임의/순서 선택 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880008111A 1988-06-30 1988-06-30 순서 선택 우선의 임의/순서 선택회로 KR950009681B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019880008111A KR950009681B1 (ko) 1988-06-30 1988-06-30 순서 선택 우선의 임의/순서 선택회로
US07/372,605 US5003201A (en) 1988-06-30 1989-06-28 Option/sequence selection circuit with sequence selection first
JP1168280A JPH02118801A (ja) 1988-06-30 1989-06-29 順序選択優先の任意／順序選択回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880008111A KR950009681B1 (ko) 1988-06-30 1988-06-30 순서 선택 우선의 임의/순서 선택회로

Publications (2)

Publication Number Publication Date
KR900000767A true KR900000767A (ko) 1990-01-31
KR950009681B1 KR950009681B1 (ko) 1995-08-26

Family

ID=19275777

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880008111A KR950009681B1 (ko) 1988-06-30 1988-06-30 순서 선택 우선의 임의/순서 선택회로

Country Status (3)

Country Link
US (1) US5003201A (ko)
JP (1) JPH02118801A (ko)
KR (1) KR950009681B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04214299A (ja) * 1990-12-10 1992-08-05 Mitsubishi Electric Corp シフトレジスタ
JP3372970B2 (ja) * 1992-09-02 2003-02-04 シャープ株式会社 自己同期型転送制御回路
US5504441A (en) * 1994-08-19 1996-04-02 International Business Machines Corporation Two-phase overlapping clocking technique for digital dynamic circuits
US6037801A (en) * 1997-10-27 2000-03-14 Intel Corporation Method and apparatus for clocking a sequential logic circuit
JP2000114935A (ja) * 1998-10-02 2000-04-21 Nec Corp 順序回路
US9910819B2 (en) * 2013-03-11 2018-03-06 Microchip Technology Incorporated Two-wire serial interface and protocol

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1415169A (en) * 1971-11-29 1975-11-26 Philips Nv Timed programme switching arrangement
US4027175A (en) * 1973-09-20 1977-05-31 National Research Development Corporation Threshold logic gates
JPS5532180A (en) * 1978-08-29 1980-03-06 Toyoda Mach Works Ltd Sequence controller capable of connecting plurality of external equipments
GB2049958B (en) * 1979-03-15 1983-11-30 Nippon Electric Co Integrated logic circuit adapted to performance tests
US4568841A (en) * 1983-03-28 1986-02-04 Digital Equipment Corporation Flexible timing circuit
JPS60109921A (ja) * 1983-11-18 1985-06-15 Fujitsu General Ltd シ−ケンス回路
US4802120A (en) * 1984-10-30 1989-01-31 Tandy Corporation Multistage timing circuit for system bus control
JPH01149516A (ja) * 1987-12-04 1989-06-12 Mitsubishi Electric Corp クロック発生装置
US4873671A (en) * 1988-01-28 1989-10-10 National Semiconductor Corporation Sequential read access of serial memories with a user defined starting address

Also Published As

Publication number Publication date
JPH02118801A (ja) 1990-05-07
US5003201A (en) 1991-03-26
KR950009681B1 (ko) 1995-08-26

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