KR890013760A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR890013760A
KR890013760A KR1019890002269A KR890002269A KR890013760A KR 890013760 A KR890013760 A KR 890013760A KR 1019890002269 A KR1019890002269 A KR 1019890002269A KR 890002269 A KR890002269 A KR 890002269A KR 890013760 A KR890013760 A KR 890013760A
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South Korea
Prior art keywords
circuit board
printed circuit
lead pins
semiconductor device
substrate
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KR1019890002269A
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English (en)
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KR0132714B1 (ko
Inventor
다까유끼 오끼나가
간지 오오쯔까
히로시 아까사끼
Original Assignee
미다 가쓰시게
가부시끼가이샤 히다찌 세이사꾸쇼
오오노 미노루
히다찌 쵸엘.에스.아이 엔지니어링 코포레이션
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Publication of KR890013760A publication Critical patent/KR890013760A/ko
Application granted granted Critical
Publication of KR0132714B1 publication Critical patent/KR0132714B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

내용 없음.

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명 의 제 1 실시예에 따른 반도체 장치를 도시한 요부 단면도.
제2도는 본 발명의 제 2 실시예에 따른 반도체 장치를 도시 한 요부 단면도.
제 3 도는 본 발명의 제3실시예에 따른 반도체 장치를 도시한 요부 단면도.
제4도는 본 발명의 제4실시예에 따른 반도체 장치를 도시한 요부 단면도.

Claims (14)

  1. 기판이, 기판상에 장착된 반도체 펠릿, 및 기판으로부터 최소한 인쇄회로 기판의 상부 표면까지 수직으로 연장되는 다수의 리드핀을 포함하는, 구멍 부분울 포함하는 인쇄 회로 기판상에 땜납으로 표면-장착하기에 적합한 반도체 장치에 있어서, 구멍내로 삽입되기 위해 몇개의 리드핀이 나머지 리드핀보다 긴 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 각각의 구멍이 인쇄 회로 기판의 상부 표면으로부터 인쇄회로 기판의 배면까지 통과하는 관통 구멍인 것을 특징으로 하는 반도체 장치.
  3. 제2항에 있어서, 더 긴 리드핀이 구멍내로 연장되고, 더 긴 리드핀의 단부가 인쇄 회로 기판의 배면으로부터 약간 돌출하는 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 각각의 더 긴 리드핀이 기판내에 삽입되어 고정될 굵은 부분 및 구멍내에 삽입되어 고정될 가는 부분을 갖고 있는 것을 특징으로 하는 반도체 장치.
  5. 제4항에 있어서, 더 긴 리드핀의 굵은 부분의 직경이 나머지 리드핀보다 큰 것을 특징으로 하는 반도체 장치.
  6. 제1항에 있어서, 더 긴 리드핀들이 나머지 핀들과 상이한 물질로 제조되는 것을 특징으로 하는 반도체 장치.
  7. 제1항에 있어서, 더 긴 리드핀들이 나머지 리드핀들 보다 굵은 것을 특징으로 하는 반도체 장치.
  8. 제1항 내지 제 7항중 어느 한 항에 있어서, 4모서리에 4개의 더 긴 리드핀이 있는 것을 특징으로 하는 반도체 장치.
  9. 제1항 내지 제 7 항중 어느 한 항에 있어서, 기판의 대각선상에 2개의 더 긴 리드핀이 있는 것을 특징으로 하는 반도체 장치 .
  10. 인쇄 회로기판 ; 및 이 인쇄 회로 기판상에 땜 납으로 표면 장착되고, 이 기판상에 장착된 반도체 펠릿. 및 기판으로부터 인쇄회로 기판의 상부 표면까지 연장되는 다수의 리드핀을 각각 갖고 있는 1개 이상의 핀-그리드 어레이를 포함하는 반도체장치에 있어서, 다수의 안내 부재들이 대응리드핀을 수용하기 위해 인쇄 회로기판의 상부상의 랜드에 제공되어 접착되는 것을 특징으로 하는 반도체 장치 .
  11. 제10항에 있어서, 인쇄 회로 기판의 4모서리에 4개의 안내 부재가 있는 것을 특징으로 하는 반도체 장치.
  12. 인쇄 회로 기판상에 다수의 리드핀을 갖고 있는 핀-그리드 어레이 반도체 장치를 땜납으로 표면 -장착하기 위한 방법에 있어서, 나머지 리드핀들 보다 더 긴 몇개의 리드핀들을 준비하는 스텝, 더 긴 리드핀을 각각 수용하기 위한 구멍을 갖고 있는 인쇄 회로 기판을 제공하는 스텝, 땜납 페이스트를 인쇄 회로기판의 상부상에 형성된 랜드의 상부에 제공하는 스텝 더 긴 리드핀이 구멍내에 삽입되도록 인쇄 회로기판의 상부상에 반도체 장치를 배치함으로써, 인쇄 회로 기판상에 반도체 장치 를 임시로 고정하는 스텝, 및 땜납을 용융시키기 위해 리플로우 노내에서 인쇄 회로 기판과 어레이 장치의 조립체를 가열하는 스텝을 포함하는 것을 특징으로 하는 방법 .
  13. 인쇄회로 기판상에 다수의 리드핀들을 갖고 있는 핀 -그리드 어레이 반도체 장치를 땜납으로 표면- 장착하기 위한 방법에 있어서, 대응 리드핀을 수용하기 위해 인쇄 회로 기판의 상부상의 랜드에 접착된 다수의 안내 부재를 제공하는 스텝, 안내 부재의 상부 및 랜드의 표면에 땜납 페이스트를 제공하는 스텝, 리드핀이 대응 안내 부재내에 삽입되도록 인쇄 회로 기판상에 반도체 장치 를 배치함으로써, 인쇄 회로 기판상에 어레이 장치를 임시로 고정하는 스텝, 및 땜납을 용융시키기 위해 리플로우 노내에서 인쇄 회로 기판과 반도체 장치의 조립체를 가열하는 스텝을 포함하는 것을 특징으로 하는 방법.
  14. 인쇄 회로 기판 ; 및 인쇄 회로 기판상에 땜납으로 표면 -장착되고, 기판이, 이 기판상에 장착된 반도체 펠릿, 및 기판으로부터 최소한 인쇄 회로 기판의 상부 표면까지 연장되는 다수의 리드핀을 각각 갖고 있는 1개 이상의 핀 -그리드 어레이를 포함하는 전기 회로 기판에 있어서, 몇개 의 리드핀들이 나머지 리드핀들보다 길고, 인쇄 회로 기판이 더 긴 리드핀들을 각각 수용하기 위한 구멍을 갖추고 있는 것을 특징으로 하는 전기 회로기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890002269A 1988-02-26 1989-02-25 반도체 장치 KR0132714B1 (ko)

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JP63-42058 1988-02-26
JP63042058A JPH01217993A (ja) 1988-02-26 1988-02-26 半導体装置

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US5107329A (en) 1992-04-21
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