CN1906758B - 复合陶瓷基板 - Google Patents
复合陶瓷基板 Download PDFInfo
- Publication number
- CN1906758B CN1906758B CN2005800017162A CN200580001716A CN1906758B CN 1906758 B CN1906758 B CN 1906758B CN 2005800017162 A CN2005800017162 A CN 2005800017162A CN 200580001716 A CN200580001716 A CN 200580001716A CN 1906758 B CN1906758 B CN 1906758B
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- ceramic substrate
- foot
- external terminal
- resin
- composite ceramic
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Abstract
已有的复合陶瓷基板,由于整个复合陶瓷基板随着母基板的挠曲而挠曲,因此在安装着从动零部件和主动零部件等安装零部件的陶瓷基板情况下,这些安装的零部件不能够随着陶瓷基板的挠曲而挠曲,表面装配零部件的外部连接用端子有可能从陶瓷基板的电极上脱落,有断线的可能。本发明的复合陶瓷基板(10),具有安装了表面装配零部件(11)的陶瓷基板(12)、将在该陶瓷基板(12)上形成的布线图案(13)与母基板(20)的表面电极加以连接用的外部端子电极(14)、以及由树脂形成为以端面支持该外部端子电极(14)的凸状的脚部(15),外部端子电极(14)通过设置在脚部(14)内的通路孔导体(15B)与布线图案(13)连接。
Description
发明领域
本发明涉及复合陶瓷基板,更详细地说,涉及内装电路元件且将陶瓷基板和树脂层叠层而形成的复合陶瓷基板。
背景技术
作为已有的这种技术,有专利文献1(特开平09-186042号公报)所述的叠层电子零部件和专利文献2(特开2003-124435号公报)所述的高频半导体器件。
专利文献1所述的叠层电子零部件以内部介入电路元件的状态叠层多枚绝缘片,构成由相对的主面和将该主面之间加以连结的侧面组成的叠层体,该叠层体的外表面具有与所述电路元件电连接的多个外部电极,通过该外部电极装配于电路基板的叠层电子零部件中,在所述叠层体的朝着所述电路基板侧的面的至少是大致中央部设置凹部。通过这样在叠层体的电路基板(具体地说是具有挠性的印刷电路板)一侧的面上设置凹部,即使在电路基板弯曲的情况下,印刷电路板的弯曲面也不与叠层体的电路基板一侧的面接触,因此能够避免对叠层体施加顶压力,防止叠层体从印刷电路板脱离和叠层体的破损。
专利文献2所述的高频半导体器件在陶瓷基板的下部形成由环氧树脂和无机充填物组成的复合树脂材料层,该复合树脂材料层的下部具有平坦的形状,并且形成外部连接用电极,在所述复合树脂材料层的内部埋设与陶瓷基板连接的半导体元件和从动零部件。利用这样的结构,可以将基板下表面充分利用为装配区域,提高装配密度,进一步在复合树脂材料层内埋设半导体元件和从动零部件,从而提高机械性能、耐湿性能等的可靠性。
但是,在专利文献1所述的叠层电子零部件的情况下,虽然可以通过在中央部分形成凹部以避免顶压力,但是整个叠层体随着印刷电路板的挠曲而挠曲,在叠层体的上表面或上下两面未装配表面装配零部件的叠层体的情况下没有问题,但在装配了从动零部件和主动零部件等装配零部件的叠层体的情况下,这些装配零部件不能够随叠层体的挠曲而挠曲,表面装配的零部件的外部连接用端子有可能脱离叠层体表面的电极,从而发生断线。
而在专利文献2所述的高频半导体器件的情况下,在陶瓷基板下表面和上表面装配主动零部件和从动零部件等表面装配零部件,从而可以使基板零部件小型化,但即使在这种情况下,也由于陶瓷基板随印刷电路板的挠曲而挠曲,表面装配零部件不能够随陶瓷基板的挠曲而挠曲,与专利文献1的叠层电子零部件的情况相同,产生装配零部件的外部连接用端子脱离叠层体表面的电极而发生断线的问题。
本发明是为了解决上述问题而完成的,其目的在于提供一种复合陶瓷基板,该基板能够防止母基板的挠曲引起的复合陶瓷基板脱离母基板所导致的断开和脱离,同时能够防止复合陶瓷基板本身脱离表面装配零部件和基板所导致的断线和表面装配零部件的损伤。
发明内容
本发明的第1方面所述的复合陶瓷基板,具有安装了表面装配零部件的陶瓷基板;将在该陶瓷基板上形成的布线图案与母基板的表面电极加以连接用的外部端子电极;由树脂形成为以端面支持该外部端子电极的凸状的脚部;以及设置在该脚部内并将上述外部端子电极与上述布线图案加以连接的通路孔导体,所述凸状的脚部形成为比安装在下表面的表面装配零部件中突出尺寸最大的表面装配零部件还向下方突出.
又,本发明的第2方面所述的复合陶瓷基板,是在1方面所述的发明中,上述表面装配零部件安装在上述陶瓷基板的第1主面和/或第2主面上,上述凸状的脚部设置在上述陶瓷基板的第2主面上。
又,本发明的第3方面所述的复合陶瓷基板,是在2方面所述的发明中,在上述陶瓷基板的第2主面的周边部,形成上述凸状的脚部。
又,本发明的第4方面所述的复合陶瓷基板,是在1方面所述的发明中,由一个上述凸状的脚部的端面,支持多个上述外部端子电极。
又,本发明的第5方面所述的复合陶瓷基板,是在4方面所述的发明中,在上述陶瓷基板的第2主面的角落部,没有配置上述外部端子电极。
又,本发明的第6方面所述的复合陶瓷基板,是在5方面所述的发明中,上述角落部的高度低于上述外部端子电极的高度。
又,本发明的第7方面所述的复合陶瓷基板,是在第2方面至第6方面中的任一项所述的发明中,上述第2主面上安装的上述表面装配零部件,安装在上述凸状脚部之间。
又,本发明的第8方面所述的复合陶瓷基板,是在第7方面所述的发明中,用与形成上述凸状脚部的树脂相同的树脂覆盖所述表面装配零部件。
又,本发明的第9方面所述的复合陶瓷基板,是在第8方面所述的发明中,在上述凸状脚部与覆盖上述表面装配零部件的树脂之间,形成圆角。
又,本发明的第10方面所述的复合陶瓷基板,是在第8方面或第9方面所述的发明中,在覆盖上述表面装配零部件的树脂的表面上,形成缝隙。
又,本发明的第11方面所述的复合陶瓷基板,是在第1方面至第10方面中的任一项所述的发明中,上述凸状的脚部的角形成圆角。
又,本发明的第12方面所述的复合陶瓷基板,是在第1方面至第11方面中的任一项所述的发明中,由具有可挠性的导电性树脂,形成上述通路孔导体。
又,本发明的第13方面所述的复合陶瓷基板,是在第1方面至第12方面中的任一项所述的发明中,上述陶瓷基板是将多个低温共烧陶瓷层叠层形成的多层陶瓷基板。
又,本发明的第14方面所述的复合陶瓷基板,是在第1方面至第13方面中的任一项所述的发明中,上述表面装配零部件具有阵列状的外部端子电极。
如果采用本发明的第1方面至第14方面所述的发明,则可以提供一种复合陶瓷基板,该基板能够防止母基板的挠曲引起的复合陶瓷基板脱离母基板所导致的断线和脱离,同时能够防止复合陶瓷基板本身脱离表面装配零部件和基板导致断线和表面装配零部件的损伤。
附图说明
图1(a)~(c)是分别示出本发明的复合陶瓷基板的一个实施形态的剖视图,(a)示出装配在母基板上之后的状态,(b)示出装配后的母基板挠曲的状态,(c)示出已有的复合陶瓷基板的情况下的断线状态.
图2(a)~(e)是示出图1所示的复合陶瓷基板的制造工序的主要部分的工序图。
图3(a)、(b)是示出本发明的复合陶瓷基板的另一实施形态的剖视图。
图4(a)、(b)是分别示出本发明的复合陶瓷基板的又一实施形态的剖视图,(a)是该剖视图,(b)是示意性表示已有的陶瓷多层基板与表面装配零部件之间的接合关系的剖视图。
图5是示出本发明的复合陶瓷基板的又一实施形态的剖视图。
图6(a)、(b)是分别示出本发明的复合陶瓷基板的又一实施形态的剖视图,(c)、(d)是对(b)的用○围起的部分进行放大显示的剖视图。
图7(a)、(b)分别是使图6(a)所示的复合陶瓷基板的母基板侧朝上的立体图,(b)是相当于表示脚部的变例的(a)的立体图剖视图。
图8(a)、(b)分别是图6(a)所示的复合陶瓷基板的脚部的变例,是使母基板侧朝上的立体图。
图9(a)、(b)分别是图6(a)所示的复合陶瓷基板的脚部以及外部端子电极的变例,是使母基板侧朝上的立体图。
图10是图6(a)所示的复合陶瓷基板的脚部以及外部端子电极的变例,是使母基板侧朝上的立体图。
图11是示出本发明的复合陶瓷基板的又一实施形态的剖视图。
图12是示出本发明的复合陶瓷基板的又一实施形态的剖视图。
图13是本发明的复合陶瓷基板的又一实施形态,是表示包含中空型的陶瓷多层基板的复合陶瓷基板的剖视图。
图14是本发明的复合陶瓷基板的又一实施形态,是表示包含中空型的陶瓷多层基板的复合陶瓷基板的剖视图。
图15是本发明的复合陶瓷基板的又一实施形态,是表示包含中空型的陶瓷多层基板的复合陶瓷基板的剖视图。
标号说明
10、10A、10B、10C、10D、10E、10F、10H 复合陶瓷基板
11、11B 表面装配零部件
12 陶瓷多层基板(陶瓷基板)
12A 陶瓷层(低温共烧陶瓷层)
13 布线图案
14 外部端子电极
15 脚部
15A 树脂部(树脂)
15B 通路孔导体
18 复合树脂层(树脂)
18A 缝隙
20 母基板
21 表面电极
具体实施方式
以下,根据图1~图15所示的各实施形态对本发明进行说明。
实施形态1
本实施例的复合陶瓷基板10,如图1(a)、(b)所示,具有安装着表面装配零部件11的陶瓷基板12、将在陶瓷基板12上形成的布线图案13与母基板20的表面电极21加以连接用的多个外部端子电极14、由树脂形成以用端面支持这些外部端子电极14的凸状的脚部15、以及设置在该脚部15内且将多个外部端子电极14与布线图案13加以连接的通路孔导体15B。表面装配零部件11安安装在陶瓷基板12的第1主面(以下称为「上表面」)一侧,外部端子电极14形成在陶瓷基板12的第2主面(以下称为「下表面」)一侧。
作为表面装配零部件11,装配有例如电容器、电感器、电阻等从动零部件和半导体元件、砷化镓半导体元件等主动零部件。这些表面装配零部件11由软钎料或导电性树脂11A接合并安装于陶瓷基板12的上表面,或者通过Au、Al、Cu线进行引线接合以进行安装。
陶瓷基板12可以是将一块陶瓷生片烧结而成的基板,也可以是将多块陶瓷生片的叠层体烧结而成的陶瓷多层基板。因此下面对陶瓷多层基板也标注标号「12」进行说明。如图1所示,陶瓷基板12作为陶瓷多层基板形成时,陶瓷多层基板12如图1(a)、(b)所示,是多层陶瓷层12A叠层形成的。
最好是陶瓷基板12为将低温共烧陶瓷(LTCC:Low Temperature Co-firedCeramic)材料烧结而成的基板。所谓低温共烧陶瓷材料,是在1050℃以下的温度条件下能够烧结,可以与电阻率小的银和铜等同时烧结的陶瓷材料。具体地说,有例如将硼硅酸类玻璃混合在氧化铝和镁橄榄石等陶瓷粉末中而形成的玻璃复合类LTCC材料、采用ZnO-MgO-Al2O3-SiO2类的结晶化玻璃的结晶化玻璃类LTCC材料、以及采用BaO-Al2O3-SiO2类陶瓷粉末和Al2O3-CaO-SiO2-MgO-B2O3类的陶瓷粉末等的非玻璃类LTCC材料等。将低温共烧陶瓷材料用作陶瓷基板13的材料,从而可以将Ag或Cu等低电阻、低熔点的金属用于布线图案13,并且可以在1050℃以下的温度条件下同时烧结陶瓷基板12和布线图案13。
陶瓷基板12,如图1(a)、(b)所示,作为陶瓷多层基板12形成的情况下,形成在陶瓷多层基板12的布线图案13如图1(a)所示,由沿着陶瓷层12A的面形成的面内导体13A以及连接上下的面内导体13A的通路孔导体13B形成。布线图案13中分别形成在陶瓷多层基板12的上下两面的面内导体13A作为表面电极13A形成。布线图案13最好以例如Ag或Cu等导电性金属作为主成分,面内导体13A和通路孔导体13B可以是由相同的金属成分形成的导体,也可以是由不同的金属成分形成的导体。
而且,外部端子电极14如图1的(a)、(b)所示,在从陶瓷多层基板12的下表面突出形成的脚部15的突出端面(母基板20的表面电极与21之间的接合面)上形成。该脚部15具有树脂部15A和贯通树脂部15A的通路孔导体15B,形成在例如陶瓷多层基板12的周边部的多处。通路孔导体15B将形成在陶瓷多层基板12下表面的表面电极(面内导体)13A与外部端子电极14电连接。还有,将陶瓷多层基板12的布线图案13与母基板20的表面电极21加以连接用的外部端子电极14也可以由后文所述那样的金属箔形成,但也可以将脚部15内的通路孔导体15B的端面原封不动用作外部端子电极。又,通路孔导体15B也可以与陶瓷多层基板12的通路孔导体13B直接连接。
最好是外部端子电极14由例如铜等金属箔形成。通过用金属箔形成外部端子电极14,可以以低电阻廉价地形成外部端子电极14。另外,通过使外部端子电极14的树脂侧粗糙化,可以更牢固地将外部端子电极14与脚部15接合。外部端子电极14不选择厚膜电极而选择铜箔等金属箔的原因在于,在树脂侧、即复合树脂制的脚部15内无法烧结外部端子电极,而且铜箔与树脂组合时可以使用印刷电路布线基板的制造方法。
形成脚部15的树脂部15A没有特别限制,但最好是利用树脂材料与无机填料混合的复合树脂材料形成。树脂材料没有特别限制,但是可以使用例如热固化树脂或光固化树脂,最好是使用环氧树脂、酚醛树脂、氰酸盐树脂等热固化树脂。无机物充填剂没有特别限制,但是金属粉末有导电性,会妨碍树脂部的聚均匀性,因此最好是采用例如氧化铝、二氧化硅、二氧化钛等。
最好是形成脚部15的通路孔导体15B具有挠性,以便能够在树脂部15A挠曲时跟随着挠曲,而且最好由例如软钎料或导电性树脂形成。导电性树脂虽然没有特别限定,但作为导电性树脂可以使用将例如Au、Ag、Cu、Ni等金属颗粒与环氧树脂、酚醛树脂、氰酸盐树脂等热固化树脂混合的化合物。脚部15的厚度(高度)虽然取决于陶瓷多层基板12的面积和树脂材料的种类等,但为了能够使母基板20挠曲又不影响陶瓷多层基板12,同时保持脚部15本身的强度,以30~500μm为佳,30~300μm则更佳。
然后,本实施形态的复合陶瓷基板可以按照以下说明的要领进行制造。再有,图2(a)~(e)示出复合陶瓷基板的制造工序的概要。
(1)陶瓷生片的制作
本实施形态中,首先,使例如中心颗粒直径1.0μm的氧化铝颗粒与中心颗粒直径1.0μm的软化点为600℃的硼硅酸玻璃以55∶45的重量比例进行混合,在该混合物中添加有机溶剂、分散剂、有机粘接剂以及增塑剂,配制完浆液之后,将该浆液涂敷在由聚对苯二甲酸乙二醇酯类树脂构成的载体薄膜(キヤリアフイルム)上,制作由厚度为10~200μm左右的低温共烧陶瓷材料构成的陶瓷生片。
然后,使通过激光加工和冲孔加工形成直径0.1mm左右的通路孔的陶瓷生片紧贴在平滑的支持台上,以此状态,从载体薄膜侧利用橡皮刮板,将以Ag粉末或Cu粉末为主成分的金属粉末、热固化树脂、以及有机溶剂混合而得到的导电糊装入陶瓷生片的通路孔导体用孔内,同时除去多余的导电糊,形成通路孔导体用的通路糊层。这时,将吸附抽吸机构附设在支持台上,使通路孔内形成负压,从而能够可靠地将电极糊填充到通路孔内。然后,利用丝网印刷,以规定的图案分别将导电糊印刷在各陶瓷生片上,干燥之后,使成为面内导体和通路孔导体的印刷糊层和导体糊层形成为布线图案层。
(2)陶瓷多层基板的制作
按照规定的顺序,将形成布线图案层的陶瓷生片叠层,得到叠层体后,在压力0.1~1.5Mpa、温度40℃~100℃的条件下,将各陶瓷生片压接,得到生叠层体。对该生叠层体进行脱粘接剂处理之后,将Ag类用作布线图案层的情况下,在空气中以850℃前后的条件对该叠层体进行烧结,将Cu类用作布线图案层的情况下,在N2气体氛围中以950℃左右的条件下对该叠层体进行烧结,得到如图2(a)所示的陶瓷多层基板12。其后根据需要,用湿式电镀等方法使Ni/Sn或Ni/Au等在上下电极上成膜。
(3)外部端子电极的制作
在这里,可以利用已众所周知的蚀刻法进行铜箔加工,制作安装用的外部端子电极14。也就是将厚度10~40μm左右的铜箔粘贴在载体薄膜上,通过涂敷光刻胶、曝光、显影、蚀刻以及剥离抗蚀膜,使铜箔形成图案,如图2(b)所示制作外部端子电极14。
(4)脚部用的树脂片的制作
首先,制作用于制作脚部15的树脂片。即分别利用刮板法将例如环氧树脂、酚醛树脂、氰酸盐树脂等热固化树脂与例如Al2O3、SiO2、TiO2等无机填料加以混合得到的复合树脂材料在载体薄膜上形成片状,制作图2(c)所示的半固化状态(B阶段)的树脂片15”A。这时,对这些树脂片进行热处理,以使其进行环氧树脂类热固化树脂的交联反应,调整到环氧树脂类热固化树脂不从载体薄膜上流出的程度的粘度。再有,最佳的热处理时间因热固化树脂的特性不同而不同。
(5)脚部的制作
接着,在该树脂片15”A上,用激光等将通路孔设置在规定部位,如图2(c)所示,将软钎料或导电性树脂作为通路孔导体15B填充在通路孔内。制作完规定片数的该树脂片15”A之后,针对各树脂片15”A,利用激光加工和冲孔加工等方法将树脂片15”A(参考该图的(d))加工成所要的形状(脚部形状),使规定片数的树脂片15”A重叠,获得脚部15所需的膜厚。这时,也可以在将树脂片15”A重叠成规定片数之后,进行激光加工和冲孔加工。将软钎料用作通路孔导体15B的情况下,软钎料与陶瓷多层基板12下表面的面内导体12A和外部端子电极14接合时,采用软熔工序。即也可以在陶瓷多层基板12上叠片形成脚部15之后进行软熔,或者可以在表面装配零部件安装之后进行软熔,与表面装配零部件安装之后的软熔同时进行熔化和接合。
(6)复合陶瓷基板的制作
如图2(e)所示,按照外部端子电极14、脚部15、陶瓷多层基板12的顺序,自下方朝上方进行定位之后,进行叠层,通过加热、加压进行叠片加工。也就是使脚部15粘合在陶瓷多层基板12下表面,进而将外部端子电极14粘合在该脚部15下表面,以制作图1(a)所示的复合陶瓷基板10。这时,为了维持脚部15的形态,可靠地与陶瓷多层基板12接合,采用各向同性加压的压力加工方法,将陶瓷多层基板12与脚部15和外部端子电极14压接。可以在例如170℃的条件下对合并后的复合陶瓷基板12和脚部15进行1小时热处理,以进行脚部15的树脂部15A的正式固化处理。然后,采用软钎料或导电性树脂将表面装配零部件11安装于陶瓷多层基板12的上表面,从而可以得到本实施形态的复合陶瓷基板10作为模块构件。复合陶瓷基板10的外部端子电极14在安装时构成为没有焊脚(フイレツト)的LGA(ランドグリツドアレイ/焊盘栅格阵列)结构(参考图7)。
在这里,若脚部15的厚度、即从陶瓷多层基板12突出的尺寸在例如陶瓷多层基板12为□10mm的情况下至少有50μm,则将发挥其功能。脚部15的突出尺寸需要结合陶瓷多层基板12的尺寸进行适当变更,若陶瓷多层基板12的尺寸小,则也可以使脚部15的突出尺寸减小,反之,若陶瓷多层基板12的尺寸大,则也可以使脚部15的突出尺寸增大。最好是使脚部15沿着陶瓷多层基板12下表面的周边部形成。通过沿着陶瓷多层基板12下表面的周边部设置脚部15,可以使在母基板上的安装稳定,提高可靠性。
采用安装器具将本实施形态的复合陶瓷基板10装配于母基板20的情况下,最好是如图3(a)所示,预先将容器16覆盖在复合陶瓷基板10上表面的表面装配零部件11上,利用安装器具简便地处理复合陶瓷基板10.作为容器16,没有特别限制,可以采用例如银镍锌合金和磷青铜等金属材料.
又,出于同样的目的,如图3(b)所示,将以热固化树脂为主要成分的复合树脂材料涂敷在复合陶瓷基板10上表面的整个面上,也可以形成覆盖表面装配零部件11的树脂层17。这种情况下,最好使使用的树脂层17的热膨胀系数与形成脚部15的树脂部15A的热膨胀系数大致相同。以此可以防止软熔工序等热处理工序中复合陶瓷基板10自身的弯曲和裂缝。因此,作为树脂层17,最好不是由热固化性树脂单独形成,而是如上述那样利用与脚部15的树脂部15A相同的复合树脂材料形成。通过利用相同的复合树脂材料形成脚部15的树脂部15A和树脂层17,能够可靠地防止复合陶瓷基板10自身的弯曲和裂缝。
若使用安装器具将复合陶瓷基板10作为模块部件装配于印刷电路布线基板等的母基板20,则如图1(a)所示,复合陶瓷基板10通过外部端子电极14与母基板20的表面电极21电连接。而且,如图1(b)所夸张表示,即使母基板20有挠曲,由于脚部15有可挠性,因此如该图所示,陶瓷多层基板12本身也不跟随母基板20的挠曲而变形。因此,不担心如以往那样陶瓷多层基板12受到损伤、或者如图1(c)所示那样表面装配零部件11的一部分从陶瓷多层基板12脱离从而发生断线或脱开。
如上所述,如果采用本实施形态,则具有安装表面装配零部件11的陶瓷多层基板12、将陶瓷基板12的布线图案13与母基板20的表面电极21加以连接用的外部端子电极14、由复合树脂材料形成以在端面支持外部端子电极14的凸状的脚部15、以及设置在该脚部15内且将外部端子电极14与布线图案13加以连接的通路孔导体15B,因此如图1(b)所示,母基板20挠曲时,脚部15可以随着母基板20的挠曲而挠曲,从而可以防止陶瓷多层基板12自身的挠曲。因此,复合陶瓷基板10本身脱离母基板20而发生断线,或者如图1(c)所示,表面装配零部件11脱离陶瓷多层基板12而发生断线,或者表面装配零部件11自身受到损伤之类的情况不会发生,可以显著提高可靠性。
实施形态2
本实施形态的复合陶瓷基板10A除了如图4(a)所示那样,与实施形态1的复合陶瓷基板10相反,仅在陶瓷多层基板12的下表面装配表面装配零部件11B以外,形成与实施形态1的复合陶瓷基板10同样的结构。
在制造本实施形态的复合陶瓷基板10A的情况下,与实施形态1的情况同样制作陶瓷多层基板12之后,在陶瓷多层基板12的下表面上装配表面装配零部件11B,然后采用与实施形态1相同的要领,制作脚部15和外部端子电极14,使这两者14、15位于表面装配零部件11的外侧,并且将这两者安安装在陶瓷多层基板12上,这样可以制造复合陶瓷基板10A。
本实施形态中,在与脚部15一样将表面装配零部件11B装配在陶瓷多层基板12的下表面上的关系的基础上,使脚部15形成比突出尺寸(厚度)最大的表面装配零部件11B更向下方突出的结构。
从而,采用本实施形态,则由于有效地利用陶瓷多层基板12的脚部15间的空间进行表面装配零部件11B的安装,因此可以期待与实施形态1同样的作用效果,除此之外,还可以实现复合陶瓷基板10A的进一步小型化和低高度化.而且,即使母基板20挠曲,脚部15也可以随着母基板20的挠曲而挠曲,从而可以防止陶瓷多层基板12自身的挠曲,不会如图4(b)所示那样,因表面装配零部件11B脱离陶瓷多层基板12而发生断线,或者表面装配零部件11自身受到损伤,可以显著提高可靠性.
实施形态3
本实施形态的复合陶瓷基板10B如图5(a)所示,不仅在实施形态2中的陶瓷多层基板12下表面,还在上表面也装配表面装配零部件11,除此以外,形成与实施形态2的复合陶瓷基板10A同样的结构。
在制造本实施形态的复合陶瓷基板10B的情况下,与实施形态2的情况一样,在陶瓷多层基板12下表面装配表面装配零部件11B之后,采用与实施形态1、2相同的要领,制作脚部15和外部端子电极14,使这两者14、15位于表面装配零部件11的外侧,并且将这两者安安装在陶瓷多层基板12上,然后采用与实施形态1相同的要领,在陶瓷多层基板12上表面安装表面装配零部件11,从而可以制造复合陶瓷基板10B。这时,可以根据各要求的功能适当选择装安装陶瓷多层基板12的上表面和下表面的表面装配零部件11、11A。
因此,如果采用本实施形态,则在陶瓷多层基板12上表面安装表面装配零部件11,同时有效地利用陶瓷多层基板12的脚部15的空间安装表面装配零部件11B,因此可以期待得到与实施形态1、2同样的作用效果,除此之外,可以实现基于更高密度安装的高功能化。
实施形态4
本实施形态的复合陶瓷基板10C如图6(a)、(b)所示,除了用复合树脂层18覆盖装配在实施形态2的陶瓷多层基板12下表面上的表面装配零部件11B以外,形成与实施形态2的复合陶瓷基板10A同样的结构。
在制造本实施形态的复合陶瓷基板10C的情况下,与实施形态2的情况一样,在陶瓷多层基板12下表面上安装表面装配零部件11B之后,安装复合树脂层18、脚部15、以及外部端子电极14。安装这三者14、15、18时,可以利用例如以下两种方法进行安装。
第1种方法是在对复合树脂层18进行碾压(laminate)之后,对脚部15进行碾压的方法。即与实施形态1一样制作具有通路孔导体15B的树脂片。形成多块树脂片以形成足够埋设表面装配零部件11B的厚度。然后,使多块树脂片重叠之后,对该叠层树脂片和陶瓷多层基板12进行定位,将叠层树脂片碾压在陶瓷多层基板12上,埋设表面装配零部件11B,从而形成复合树脂层18。然后,使与实施形态1同样制作的外部端子电极14及脚部15相对陶瓷多层基板12定位,采用与实施形态1同样的要领将外部端子电极14和脚部15碾压在陶瓷多层基板12的复合树脂层18上,利用各向同性压力加工法,将脚部15压接在复合树脂层18的周边部上,使复合树脂层18和脚部15的树脂部15A正式固化,制作复合陶瓷基板10C。
第2种方法是同时使复合树脂层18和脚部15成型的方法。也就是使成为外部端子电极14的铜箔和叠层树脂片相对陶瓷多层基板12定位之后,将这两者碾压在陶瓷多层基板12下表面上,利用叠层树脂片埋设表面装配零部件11B,形成树脂层。然后,用具有凸状的模具从下表面对树脂层进行压力加工,在凹部形成复合树脂层18,同时在凸部形成脚部15。然后,使复合树脂层18和脚部的树脂部15A正式硬化,制作复合陶瓷基板10C。
本实施形态中,在形成脚部15和复合树脂层18时,构成它们的复合树脂材料处于流动性良好的状态,因此在图6(b)中用○围起的(c)部分、即复合树脂层18与脚部15的边界部分,复合树脂材料固化时形成平滑的圆角.而在图6(b)中用○围起的(d)部分即脚部15的角以及其他的角也形成复合树脂材料固化时平滑的圆角.
以图7(a)、(b)所示的形态在复合树脂层18的周边部,形成本实施形态中的脚部15。图7(a)所示的脚部15沿着复合树脂层18的周边部整个周围,保持规定间隔形成多个,以各自的下表面支持外部端子电极14。另外,该图7(b)所示的脚部15具有在复合树脂层18左右两边整个长度上分别形成细长形状的第1部分、以及沿着余下的两边与第1部分的两端部保持间隙分别形成第2部分,以第1、第2部分保持规定间隔对多个外部端子电极14进行支持。
因此,采用本实施形态,则设置成用复合树脂层18保护安装在陶瓷多层基板12下表面的表面装配零部件11B,同时使脚部15向复合树脂层18的周边部突出地进行设置,因此可以可靠地防止表面装配零部件11B脱离陶瓷多层基板12,同时与仅通过复合树脂层在母基板上装配复合陶瓷基板的情况相比,可以利用脚部15缓和母基板的挠曲所产生的影响,从而可以更可靠地防止表面装配零部件11B断线,提高可靠性。
又,采用本实施形态,则复合树脂层18与脚部15之间的边界线(参考图6(c))有平滑的圆角,因此可以防止应力集中于边界线,防止发生裂缝等,进而提高可靠性。另外,由于脚部15的角(参考该图的(d))和其他角也有平滑的圆角,因此碎屑等不易产生,从而可以提高可靠性。
又,采用本实施形态,则在复合树脂层18的周边部形成脚部15,因此即使在复合树脂层18中埋设的表面装配零部件11B部分露出的情况下,露出的零部件在母基板上进行安装时和处理时也不易接触外部,从而可以防止表面装配零部件11B的破损,提高可靠性。
实施形态5
本实施形态中,如图8(a)、(b)所示,除了使脚部15的形态不同以外,形成与实施形态4同样的结构,因此对与实施形态4相同或相当的部分标注同一标号,仅对本实施形态的特征部分进行说明。本实施形态中,图8(a)所示的脚部15在复合树脂层18的外缘部在整个一周上成一整体地以呈方框状突出的方式形成,支持在其下表面整个一周保持规定间隔配置的多个外部端子电极14。因此,在方框状的脚部15的内侧,矩形的凹陷部作为复合树脂层18的下表面而形成。该矩形的凹陷部也可以如该图(b)所示,作为圆形的凹陷部而形成。可以用与实施形态4相同的方法形成这些脚部15。即使在本实施形态中,也可以期待得到与实施形态4同样的作用效果。
又,图8(a)所示的方框状的脚部15也可以作为图1、图3、图4(a)、(b)以及图5所示的复合陶瓷基板的脚部使用。在这种情况下,在脚部15的内侧,没有形成复合树脂层18,陶瓷多层基板12的下表面和表面装配零部件11B露出。
实施形态6
本实施形态中,如9(a)、(b)所示,除了分别使脚部15的形态和外部端子电极14的配置方式不同之外,形成与实施形态5同样的结构,因此对与实施形态5相同或相当的部分标注同一标号,仅对本实施形态的特征部分进行说明。图9(a)所示的脚部15以与图8(a)所示的脚部15实质上相同的方式形成。该脚部15用角落部以外的部位支持多个外部端子电极14,在角落部未配置外部端子电极。通过采用这样的结构,在复合陶瓷基板装配在母基板等装配基板上的情况下,可以提高复合陶瓷基板的耐冲击性。
也就是说,若装配了复合陶瓷基板的装配基板因掉落等原因受到冲击,则因该冲击而在装配基板上产生复杂的挠曲,挠曲所产生的应力通过外部端子电极14传递到脚部15。在脚部15,由各外部端子电极14传递的应力通过脚部15容易集中到其角落部(通过在相互垂直的方向上排列的外部端子电极14的中心的直线交叉的点)。但是,在本实施形态中,在角落部没有配置外部端子电极14,因此,没有受到在角落部集中应力作用的外部端子电极14,没有该部分的外部端子电极14发生断线,可以提高耐冲击性。另外,该集中应力主要作用在配置脚部15上的外部端子电极14的平面角落部,因此如该图(b)所示,使角落部的高度位置后退到比排列外部端子电极14的脚部15的下端面更靠复合树脂层18一侧,比脚部15的下端面位置更低,以此消除对角落部的应力集中,从而可以进一步提高耐冲击性。
另外,即使在方框状的脚部15的角落部不配置外部端子电极14,或降低该角落部,冲击力也会作用于安装在装配基板上的外部端子电极14上。因此,如图10所示,将外部端子电极14从脚部15下表面延伸设置到外侧面,不仅接合外部端子电极14下表面,而且在外部端子电极14的侧面形成软钎料等的角焊,从而可以增强与装配基板的接合强度,提高耐冲击性。
实施形态7
本实施形态的复合陶瓷基板10D如图11所示,形成以下所述结构,也就是将装配在实施形态3的陶瓷多层基板12下表面的表面装配零部件11B,形成与实施形态4相同的复合树脂层18,同时在该复合树脂层18上设置缝隙18A。缝隙18A形成底部具有圆角,逐一区划多个表面装配零部件11B的结构。缝隙18A在例如实施形态4中将复合树脂层18和脚部15压制成型时,可以利用各向同性加压的冲压成型方法形成。就这样,可以使缝隙18A的形态在某种程度上跟踪表面装配零部件11B的凹凸。
因此,如果采用本实施形态,则使缝隙18A形成分别跟踪多个表面装配零部件11B的形状,从而在表面装配零部件11B的外侧存在一定值以上的厚度的复合树脂层18,其结果是可以防止表面装配零部件11B从复合树脂层18露出,从而可以更可靠地保护表面装配零部件11B。
实施形态8
本实施形态的复合陶瓷基板10E如图12所示,复合树脂层19由中央部向多个外部端子电极14逐渐变厚,在周边部形成多个脚部15。即把设置在陶瓷多层基板12下表面的表面电极13A的厚度做得比设在陶瓷多层基板12内部的面内导体的厚度更厚。对着复合树脂层19的中央部平稳地形成弯曲的凹部。换句话说,本实施形态虽然没有在复合树脂层19内放置表面装配零部件,但是也可以内装表面装配零部件。再有,图12中省略陶瓷多层基板12的布线图案。
因此,如果采用本实施形态,则可以起到与实施形态1同样的作用效果。即从复合树脂层19的周边部向中央部逐渐凹陷而并非是平面,因此即使在母基板挠曲而接触到复合陶瓷基板10E的情况下,接点也不会是一个点,因此可以使力分散,从而可以防止在接触部分产生的裂缝。
实施形态9
本实施形态的复合陶瓷基板10F如图13所示,除了陶瓷多层基板12’有空穴C外,形成与实施形态1同样的结构.在设置空穴C的情况下,在制作例如陶瓷多层基板12’时,制作需要的片数(该图中为2片)的具有空穴C用的贯通孔的陶瓷生片.然后,在具有贯通孔的陶瓷生片上形成通路孔导体和面内导体,叠层于其他没有贯通孔的陶瓷生片上,制作生陶瓷叠层体.通过烧结该生陶瓷叠层体,可以制作带有空穴的陶瓷多层基板12’.其后,按照与实施形态1相同的步骤安装脚部15.如果采用本实施形态,则可以通过在空穴C内装配表面装配零部件11B,使复合陶瓷基板的高度进一步降低.
实施形态10
本实施形态的复合陶瓷基板10G如图14所示,除了陶瓷多层基板12’具有空穴C外,形成以图11所示的实施形态7为标准的结构。可以与实施形态9一样形成空穴C。本实施形态在复合树脂层18的下表面没有形成图11所示的缝隙18A,但在本实施形态中也可以设置图11所示的缝隙18A。如果采用本实施形态,则通过在空穴C内安装表面装配零部件11B,可以使复合陶瓷基板11G的高度比图11所示的复合陶瓷基板11D的高度更低。这种情况下,如图14所示,配置在空穴C内的表面装配零部件11B的高度也可以比空穴C的深度更高。也就是说,即使不形成难度大、深度深的空穴,也可以实现低高度化,以完全容纳表面装配零部件11B。
实施形态11
本实施形态的复合陶瓷基板10H如图15所示,陶瓷多层基板12”具有二级结构的空穴C’,在空穴C’的底面安装半导体元件等由主动零部件构成的表面装配零部件11C。二级结构的空穴C’是每次准备规定片数的中央部有大小不同两种贯通孔的陶瓷生片,使这两种陶瓷生片分别以规定的片数叠层,然后将其叠层在没有贯通孔的陶瓷生片上,通过对其进行烧结,可以制作具有两级结构的空穴C’的陶瓷多层基板12’。表面装配零部件11C如该图所示,其端子电极通过在内侧的阶梯部平面形成的表面电极13A和接合线11D连接。在空穴C’形成复合树脂层18,利用该复合树脂层18密封表面装配零部件11C。又在复合树脂层18下表面的周边部形成脚部15,在其内侧以规定的图案形成表面电极18B。脚部15根据需要采用在上述各实施形态中说明的各种形态。然后,在复合树脂层18下表面安装表面装配零部件18B,该表面装配零部件11B通过表面电极11B与陶瓷多层基板12的布线图案13连接。
因此,采用本实施形态,则在空穴C’的底面安装表面装配零部件11C,在密封表面装配零部件11C的复合树脂层18下表面也安装其他表面装配零部件18B,因此可以用更高密度安装表面装配零部件,进一步实现多功能化。
再有,本发明并非局限于上述各实施形态,只要不违反本发明的宗旨,都包含在本发明内。
工业上的实用性
本发明可以适用于安装半导体等的主动零部件和电容器等的从动零部件等的表面装配零部件的复合陶瓷基板。
Claims (9)
1.一种复合陶瓷基板,其特征在于,具有
安装表面装配零部件的陶瓷基板;
将在该陶瓷基板上形成的布线图案与母基板的表面电极加以连接用的外部端子电极;
由树脂形成为以端面支持该外部端子电极的凸状的脚部;以及
设置在该脚部内并将所述外部端子电极与所述布线图案加以连接的通路孔导体,
所述凸状的脚部形成为比安装在下表面的表面装配零部件中突出尺寸最大的表面装配零部件还向下方突出,
所述表面装配零部件安装在所述陶瓷基板的第1主面和/或第2主面上,
所述凸状的脚部设置在所述陶瓷基板的第2主面上,
在所述陶瓷基板的第2主面的周边部,形成所述凸状的脚部,
由一个所述凸状的脚部的端面,支持多个所述外部端子电极,
在所述陶瓷基板的第2主面的角落部,没有配置所述外部端子电极,
所述角落部的高度低于所述外部端子电极的高度。
2.根据权利要求1所述的复合陶瓷基板,其特征在于,
所述第2主面上安装的所述表面装配零部件,安装在所述凸状脚部之间。
3.根据权利要求2所述的复合陶瓷基板,其特征在于,
用与形成所述凸状脚部的树脂相同的树脂覆盖所述表面装配零部件。
4.根据权利要求3所述的复合陶瓷基板,其特征在于,
在所述凸状脚部与覆盖所述表面装配零部件的树脂之间,形成圆角。
5.根据权利要求3或4所述的复合陶瓷基板,其特征在于,
在覆盖所述表面装配零部件的树脂的表面上,形成缝隙。
6.根据权利要求1~4中的任一项所述的复合陶瓷基板,其特征在于,
所述凸状的脚部的角形成圆角。
7.根据权利要求1~4中的任一项所述的复合陶瓷基板,其特征在于,
由具有可挠性的导电性树脂,形成所述通路孔导体。
8.根据权利要求1~4中的任一项所述的复合陶瓷基板,其特征在于,
所述陶瓷基板是将多个低温共烧陶瓷层叠层形成的多层陶瓷基板。
9.根据权利要求1~4中的任一项所述的复合陶瓷基板,其特征在于,
所述表面装配零部件具有阵列状的外部端子电极。
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JP4795067B2 (ja) | 2006-03-28 | 2011-10-19 | ソニーケミカル&インフォメーションデバイス株式会社 | 電気部品付基板の製造方法 |
JP4873005B2 (ja) * | 2006-03-29 | 2012-02-08 | 株式会社村田製作所 | 複合基板及び複合基板の製造方法 |
WO2007116544A1 (ja) * | 2006-04-10 | 2007-10-18 | Murata Manufacturing Co., Ltd. | 複合基板及び複合基板の製造方法 |
WO2007132612A1 (ja) * | 2006-05-17 | 2007-11-22 | Murata Manufacturing Co., Ltd. | 複合基板及びその製造方法 |
JP4957163B2 (ja) * | 2006-10-10 | 2012-06-20 | 株式会社村田製作所 | 複合部品 |
EP1956652A1 (en) * | 2007-02-08 | 2008-08-13 | Nederlandse Organisatie voor Toegepast-Natuuurwetenschappelijk Onderzoek TNO | Sealed ball grid array package |
JP4434268B2 (ja) * | 2007-11-28 | 2010-03-17 | Tdk株式会社 | 電子部品モジュール |
CN102369600B (zh) * | 2009-04-02 | 2014-09-10 | 株式会社村田制作所 | 电路基板 |
JP5344036B2 (ja) | 2009-05-12 | 2013-11-20 | 株式会社村田製作所 | 回路基板及びその製造方法 |
US20120314390A1 (en) * | 2010-03-03 | 2012-12-13 | Mutual-Tek Industries Co., Ltd. | Multilayer circuit board |
TWI411073B (zh) * | 2010-08-13 | 2013-10-01 | Unimicron Technology Corp | 嵌埋被動元件之封裝基板及其製法 |
GB2499850B (en) * | 2012-03-02 | 2014-07-09 | Novalia Ltd | Circuit board assembly |
JP2015088519A (ja) * | 2013-10-28 | 2015-05-07 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US9190367B1 (en) | 2014-10-22 | 2015-11-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor process |
BR112015029665A2 (pt) * | 2014-12-26 | 2017-07-25 | Intel Corp | arquitetura de montagem que emprega suporte orgânico para produção de montagem compacta e aprimorada. |
JP2015181204A (ja) * | 2015-07-10 | 2015-10-15 | 大日本印刷株式会社 | 電子モジュール |
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US10194526B1 (en) * | 2018-08-27 | 2019-01-29 | Tactotek Oy | Electrical node, method for manufacturing an electrical node, electrical node strip or sheet, and multilayer structure comprising the node |
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KR102210868B1 (ko) * | 2020-10-27 | 2021-02-02 | (주)샘씨엔에스 | 포토 공정을 이용한 세라믹 기판의 제조 방법 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1412838A (zh) * | 2001-10-17 | 2003-04-23 | 松下电器产业株式会社 | 高频半导体装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3483308A (en) * | 1968-10-24 | 1969-12-09 | Texas Instruments Inc | Modular packages for semiconductor devices |
US5917707A (en) * | 1993-11-16 | 1999-06-29 | Formfactor, Inc. | Flexible contact structure with an electrically conductive shell |
JPH01217993A (ja) * | 1988-02-26 | 1989-08-31 | Hitachi Ltd | 半導体装置 |
JPH0983090A (ja) | 1995-09-19 | 1997-03-28 | Murata Mfg Co Ltd | 電子部品 |
JPH09186042A (ja) | 1996-01-08 | 1997-07-15 | Murata Mfg Co Ltd | 積層電子部品 |
TW335544B (en) * | 1996-03-18 | 1998-07-01 | Olin Corp | Improved solder joint reliability |
JPH09298255A (ja) * | 1996-05-01 | 1997-11-18 | Shinko Electric Ind Co Ltd | セラミック回路基板及びこれを用いた半導体装置 |
JPH10261874A (ja) | 1997-03-19 | 1998-09-29 | Murata Mfg Co Ltd | 多層回路基板 |
JP2000101348A (ja) * | 1998-09-17 | 2000-04-07 | Toyo Commun Equip Co Ltd | 電子部品用パッケージ |
JP2004254037A (ja) * | 2003-02-19 | 2004-09-09 | Kyocera Corp | 撮像装置 |
-
2005
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---|---|---|---|---|
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Non-Patent Citations (2)
Title |
---|
JP特开2000-101348A 2000.04.07 |
JP特开平9-186042A 1997.07.15 |
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