KR890005997A - Ad변환기 - Google Patents

Ad변환기 Download PDF

Info

Publication number
KR890005997A
KR890005997A KR1019880012254A KR880012254A KR890005997A KR 890005997 A KR890005997 A KR 890005997A KR 1019880012254 A KR1019880012254 A KR 1019880012254A KR 880012254 A KR880012254 A KR 880012254A KR 890005997 A KR890005997 A KR 890005997A
Authority
KR
South Korea
Prior art keywords
converter
reference voltage
switch
period
differential
Prior art date
Application number
KR1019880012254A
Other languages
English (en)
Other versions
KR910006483B1 (ko
Inventor
마사오 호쯔따
도시히꼬 시미즈
겐지 마이오
요시또 네지메
Original Assignee
미다 가쓰시게
가부시키가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62237137A external-priority patent/JPS6481416A/ja
Priority claimed from JP63166711A external-priority patent/JPH0217725A/ja
Application filed by 미다 가쓰시게, 가부시키가이샤 히다찌세이사꾸쇼 filed Critical 미다 가쓰시게
Publication of KR890005997A publication Critical patent/KR890005997A/ko
Application granted granted Critical
Publication of KR910006483B1 publication Critical patent/KR910006483B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/20—Increasing resolution using an n bit system to obtain n + m bits
    • H03M1/202—Increasing resolution using an n bit system to obtain n + m bits by interpolation
    • H03M1/206—Increasing resolution using an n bit system to obtain n + m bits by interpolation using a logic interpolation circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1235—Non-linear conversion not otherwise provided for in subgroups of H03M1/12
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
    • H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
    • H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

내용 없음

Description

AD변환기
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예를 도시한 블록도.
제2도 및 제3도는 제1도의 동작을 설명하기 위한 타이밍도 및 입력 레벨을 도시한 도면.
* 도면의 주요부분에 대한 부호의 설명
1 : AD변환기 3 : 가산 회로
4 : 클럭 발생 회로 101 : 저항렬
102 : 비교기 103 : 인코더
105 : 스위치

Claims (5)

  1. N개의 레벨을 갖는 기준 전압을 M개마다 다른쪽에 서로 접속된 스위치(105)에 의해 샘플링 주기마다 순차적으로 전환해서 N/M개의 비교기(102)에 접속하고, 각 샘플링 주기마다 얻어지는 AD변환값을 일정기간 걸쳐서 가산하는 것을 특징으로 하는 AD변환기.
  2. 특허청구의 범위 제1항에 있어서, 상기 비교기는 차동증폭기 구성의 입력단을 갖고 상기 차동증폭기를 구성하는 차동 트랜지스터쌍을 M쌍 준비하고, 상기 차동 트랜지스터쌍의 동작 전류를 전류 스위치에 의해 전환하여 각 차동 트랜지스터쌍의 한쪽이 각 기준전압에 접속되고, 다른쪽이 입력단자에 접속되는 것에 의해서 상기 스위치의 동작을 실행하는 것을 특징으로 하는 AD변환기.
  3. 특허청구의 범위 제1항에 있어서, 상기 기준 전압은 저항렬(101)에 의해 발생되고, 상기 저항렬은 상기 저항렬을 구성하는 저항의 값을 순차적으로 다르게 하여 비직선성을 갖는 기준 전압을 갖는 것을 특징으로 하는 AD변환기.
  4. 특허청구의 범위 제1항에 있어서, 상기 저항렬에 의해서 발생하는 기준 전압이 역 γ특성을 갖는 AD변환기.
  5. M개마다 다른쪽 끝이 서로 접속된 스위치(105)와 AD변환값을 일정 기간에 걸쳐서 가산하는 가산기(3)을 갖는 AD변환기(1)에 있어서, 1가산 기간이 샘플링 주기의 nM(n=1,2 ...)배인 것을 특징으로 하는 AD변환기.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880012254A 1987-09-24 1988-09-24 Ad변환기 KR910006483B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP62237137A JPS6481416A (en) 1987-09-24 1987-09-24 Ad converter
JP62-237137 1987-09-24
JP63-166711 1988-07-06
JP63166711A JPH0217725A (ja) 1988-07-06 1988-07-06 Ａｄ変換器

Publications (2)

Publication Number Publication Date
KR890005997A true KR890005997A (ko) 1989-05-18
KR910006483B1 KR910006483B1 (ko) 1991-08-26

Family

ID=26490991

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880012254A KR910006483B1 (ko) 1987-09-24 1988-09-24 Ad변환기

Country Status (2)

Country Link
US (1) US4939518A (ko)
KR (1) KR910006483B1 (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179772A (ja) * 1989-12-08 1991-08-05 Toshiba Corp 半導体装置
JP2875922B2 (ja) * 1992-03-05 1999-03-31 三菱電機株式会社 Ａ／ｄ変換器
US5793556A (en) * 1994-10-19 1998-08-11 International Business Machines Corporation High speed PES demodulator
US6298459B1 (en) * 1997-07-18 2001-10-02 Fujitsu Limited Analog to digital converter with encoder circuit and testing method therefor
US6703951B2 (en) 1997-07-18 2004-03-09 Fujitsu Limited Analog to digital converter with encoder circuit and testing method therefor
US6859762B2 (en) * 2001-07-03 2005-02-22 Mitutoyo Corporation Low voltage low power signal processing system and method for high accuracy processing of differential signal inputs from a low power measuring instrument
JP2003101411A (ja) * 2001-09-20 2003-04-04 Matsushita Electric Ind Co Ltd 並列型ａ／ｄ変換器
WO2005002047A1 (en) * 2003-06-27 2005-01-06 Cypress Semiconductor Corp. Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs
US6809675B1 (en) 2004-03-05 2004-10-26 International Business Machines Corporation Redundant analog to digital state machine employed to multiple states on a single line
US7852253B2 (en) * 2009-02-18 2010-12-14 Freescale Semiconductor, Inc. Digitally adjustable quantization circuit
US8362937B2 (en) * 2009-06-12 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits for converting analog signals to digital signals, systems, and operating methods thereof
JP2011040904A (ja) * 2009-08-07 2011-02-24 Renesas Electronics Corp Ｄ−ａ変換回路
JP5684080B2 (ja) * 2011-09-22 2015-03-11 株式会社東芝 アナログ／デジタル変換器
JP5684081B2 (ja) * 2011-09-22 2015-03-11 株式会社東芝 アナログ／デジタル変換器
DE102014226136B3 (de) * 2014-12-16 2016-02-11 Dialog Semiconductor (UK) Ltd Messschaltung
US9602120B1 (en) * 2016-04-04 2017-03-21 International Business Machines Corporation Analog to digital converter with digital reference voltage signal

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2207416C3 (de) * 1972-02-11 1974-10-17 Zschimmer, Gero, 1000 Berlin Verfahren zum Messen einer Spannung mit Hilfe eines Analog-Digital-Wandlers
US4495210A (en) * 1980-05-28 1985-01-22 Societe D'assistance Technique Pour Produits Nestle S.A. Caffeine adsorption
JPS6048622A (ja) * 1983-08-29 1985-03-16 Shimadzu Corp Ａ／ｄ変換装置
US4745393A (en) * 1985-09-25 1988-05-17 Hitachi, Ltd Analog-to-digital converter
US4774498A (en) * 1987-03-09 1988-09-27 Tektronix, Inc. Analog-to-digital converter with error checking and correction circuits
US4742330A (en) * 1987-05-01 1988-05-03 The Regents Of The University Of California Flash A/D converter using capacitor arrays
US4763106A (en) * 1987-07-20 1988-08-09 Zdzislaw Gulczynski Flash analog-to-digital converter

Also Published As

Publication number Publication date
KR910006483B1 (ko) 1991-08-26
US4939518A (en) 1990-07-03

Similar Documents

Publication Publication Date Title
KR890005997A (ko) Ad변환기
KR920020847A (ko) 샘플밴드-갭 전압 기준 회로
KR880012020A (ko) 디지탈/아날로그 변환기
KR910015127A (ko) Da 변환기
KR890016779A (ko) 디지탈·아날로그변환회로
KR970024619A (ko) 비교기의 입력 바이어스전류가 보상된 아날로그 디지탈 변환기
KR840004333A (ko) 아날로그 디지탈 변환장치
KR880013328A (ko) 디지탈·애널로그 변환장치
KR920003670A (ko) D/a 변환기
KR900001134A (ko) 아나로그/디지탈 변환회로
KR940003152A (ko) 수정된 부호 절대값 디지탈-아날로그 변환기 및 그 작동방법
KR100514320B1 (ko) 디지털/아날로그 변환기
KR940010532A (ko) 인터페이스회로
KR880010578A (ko) 병렬형 d/a 콘버터의 직선성 보상회로
KR890004505A (ko) A/d 변환기
KR880011802A (ko) 반도체장치
JPH06268523A (ja) Ｄ／ａ変換器
KR840005288A (ko) 샘플회로
SU966887A1 (ru) Разр дный преобразователь тока
SU1640824A1 (ru) Цифроаналоговый преобразователь
JP2745153B2 (ja) ディジタルアナログ変換回路
SU639139A1 (ru) Цифро-аналоговый преобразователь
SU1582350A1 (ru) Коммутатор напр жени
KR880004397A (ko) 아날로그 신호 비교회로
SU1316009A1 (ru) Логарифмический преобразователь

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19960819

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee