KR880003440A - 절연 게이트 전계효과 트랜지스터 제조방법 - Google Patents

절연 게이트 전계효과 트랜지스터 제조방법 Download PDF

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KR880003440A
KR880003440A KR1019870008614A KR870008614A KR880003440A KR 880003440 A KR880003440 A KR 880003440A KR 1019870008614 A KR1019870008614 A KR 1019870008614A KR 870008614 A KR870008614 A KR 870008614A KR 880003440 A KR880003440 A KR 880003440A
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effect transistor
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로날드 와이트 케니드
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이반 밀러 레르너
엔· 브이· 필립스 글로아이람펜파브리켄
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/772—Field effect transistors
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • Y10S148/00—Metal treatment
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Abstract

내용 없음

Description

절연 게이트 전계효과 트랜지스터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 제2도의 Ⅱ-Ⅱ라인을 따라 취해진 본 발명을 실현하는 방법에 의해 제조된 인터디지트 절연 게이트 전계효과 트랜지스터(IGFET)의 부분에 대한 개략 단면도.
제2도는 제1도에 도시된 절연 게이트 전계효과 트랜지스터의 부분에 대한 개략 평면도.
제3a 내지 3d도는 제1 및 2도에 도시된 IGEFET를 제조하는 발명을 실현하는 방법의 여러 단계를 도시하는 도면.

Claims (10)

  1. 전선게이트 전계효과 트랜지스터를 제조하는 방법에서, 전도게이트 영역을 갖고 있는 절연게이트 구조를 형성하기 위하여 반도체 바디의 한 표면의 절연층에 전도게이트 층을 제공하는 단계와, 한 전도형의 소스영역을 형성하기 위해 반도체 바디에 불순물을 주입시키는 단계와, 절연게이트 구조를 덮기 위하여 반도체 바디의 표면에 절연재료를 성장시키는 단계와, 소스영역의 표면을 노출시키기 위하여 한 표면위의 절연층에 있는 접촉창을 개방시키므로써 바디영역에 소스영역을 쇼트시키는 단계와, 노출된 소스영역의 면적을 남기기 위하여 소스영역의 표면을 덮는 마스킹 영역을 제공하는 단계와, 바디영역의 면적 또는 밑에는 면적을 노출시키기 위하여 소스영역의 상기 노출된 면적을 에칭하는 단계와, 마스킹 영역을 제거하여 바디영역의 노출된 영역을 소스영역에 쇼트시키기 위하여 접촉창에 금속을 제공하는 단계를 포함하며, 상기 바디영역의 일부는 게이트영역 아래 있는 채널 영역을 형성하는 절연게이트 전계효과 트랜지스터 제조방법에 있어서, 소스영역의 노출된 면적이 접촉창에 의해 부분적으로 그리고 마스킹 영역에 의해 부분적으로 규정되는 주변을 갖도록 한 방향으로 마스킹 영역이 완전히 접촉창을 가로질러 연장되게 소스영역의 표면을 덮는 마스킹 영역을 제공하는 단계를 포함하는 것을 특징으로 하는 절연게이트 전계효과 트랜지스터 제조방법.
  2. 제1항에 있어서, 접촉창이 규정되게 절연재료가 절연게이트 구조의 엣지에 남아 있게 되도록 반도체 바디의 표면을 향하여 이방성으로 절연재료를 에칭하므로써 접촉창을 개방하는 단계를 더 포함하는 것을 특징으로 하는 절연게이트 전계효과 트랜지스터 제조방법.
  3. 제1 또는 2항에 있어서, 마스킹 영역 제조단계는 소스영역의 다수 노출된 면적이 규정되도록 접촉창을 가로질러 각각 완전히 연장되는 다수의 마스킹 영역을 제공하는 단계를 포함하며, 상기 노출된 영역은 접촉창에 의해 부분적으로 규정되고 하나 또는 그 이상의 마스킹 영역에 의해 부분적으로 규정되는 주변을 갖고 있는 것을 특징으로 하는 절연게이트 전계효과 트랜지스터 제조방법.
  4. 제1,2 또는 3항에 있어서, 접촉창 개방단계는 가늘고 긴 접촉창을 개방시키는 단계를 포함하며, 각각의 마스킹 영역은 접촉창의 폭을 완전 가로질러 연장되지만 접촉창의 길이를 부분적으로 가로질러 연장되도록 절연층 위에 제공되는 것을 특징으로 하는 절연게이트 전계효과 트랜지스터 제조방법.
  5. 제3항에 있어서, 접촉창은 가늘고 긴 접촉창을 개방시키는 단계를 포함하고, 마스킹 영역은 제공단계는 접촉창에 소스영역의 다수 간격을 둔 노출된 면적을 규정하기 위하여 접촉창을 완전히 가로질러 다수의 마스킹 영역을 제공하는 단계를 포함하는 것을 특징으로 하는 절연게이트 전계효과 트랜지스터 제조방법.
  6. 제5항에 있어서, 접촉창 위로 연장되는 마스킹 영역은 접촉창의 길이 방향으로 균일하게 간격이 떨어져 있는 것을 특징으로 하는 절연게이트 전계효과 트랜지스터 제조방법.
  7. 제4,5 또는 6항에 있어서, 각각의 마스킹 영역은 마스킹층 내에 형성된 개구에 의해 규정되고, 각 개구의 폭은 접촉창이 폭보다 큰 것을 특징으로 하는 절연게이트 전계효과 트랜지스터 제조방법.
  8. 제1 내지 7항에 있어서, 마스킹 영역은 소스영역의 각 노출된 면적이 면적에 있어서 마스킹 영역에 의해 덮혀 있는 소스영역의 각 면적과 동일한 것을 특징으로 하는 절연게이트 트랜지스터 제조방법.
  9. 제1 내지 8항에 있어서, 첩촉창내에 금속을 제공하기 전에 노출된 바디영역의 표면 도우핑이 증가되도록 바디영역의 아래에 있는 면적을 노출시키기 위해 에칭한 후 마스킹 영역 제거전에 접촉창을 통하여 반대의전도형 불순물을 더 주입시키는 단계를 더 포함하는 것을 특징으로 하는 절연게이트 트랜지스터 제조방법.
  10. 제1 내지 9항에 있어서, 불순물은 반도체 바디에 주입되어, 각각의 바디영역의 일부가 게이트 영역의 연합측면 아래에 있는 각각의 채널 면적을 형성하도록 게이트 영역의 두개의 반대편 각각에서 연합바디 영역에서 각각의 소스영역이 제공되며, 각각의 소스영역을 선행항중임의 한 항에서 청구된 것과 같은 연합바디 영역에 쇼트되며, 각각의 접촉창은 각각의 소스영역 위에서 개방되는것을 특징으로 하는 절연게이트 전계효과 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870008614A 1986-08-08 1987-08-06 절연 게이트 전계효과 트랜지스터 제조방법 KR950011780B1 (ko)

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Application Number Priority Date Filing Date Title
GB8619426 1986-08-08
GB08619426A GB2193597A (en) 1986-08-08 1986-08-08 Method of manufacturing a vertical DMOS transistor
GB08630814A GB2199694A (en) 1986-12-23 1986-12-23 A method of manufacturing a semiconductor device
GB8630814 1986-12-23

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KR880003440A true KR880003440A (ko) 1988-05-17
KR950011780B1 KR950011780B1 (ko) 1995-10-10

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DE (1) DE3788470T2 (ko)

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JPH01270359A (ja) * 1988-04-22 1989-10-27 Nec Corp 縦型電界効果トランジスタの製造方法
US5034346A (en) * 1988-08-25 1991-07-23 Micrel Inc. Method for forming shorting contact for semiconductor which allows for relaxed alignment tolerance
JPH0834312B2 (ja) * 1988-12-06 1996-03-29 富士電機株式会社 縦形電界効果トランジスタ
US5798550A (en) * 1990-10-01 1998-08-25 Nippondenso Co. Ltd. Vertical type semiconductor device and gate structure
JP2751612B2 (ja) * 1990-10-01 1998-05-18 株式会社デンソー 縦型パワートランジスタ及びその製造方法
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KR950011780B1 (ko) 1995-10-10
EP0255970A2 (en) 1988-02-17
EP0255970A3 (en) 1990-07-18
EP0255970B1 (en) 1993-12-15
DE3788470T2 (de) 1994-06-09
JPH07120671B2 (ja) 1995-12-20
DE3788470D1 (de) 1994-01-27
JPS6343376A (ja) 1988-02-24
US4920064A (en) 1990-04-24

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