KR870010635A - Vlsi기술을 이용한 최적의 cmos-fet를 제조하기 위한 공정 - Google Patents
Vlsi기술을 이용한 최적의 cmos-fet를 제조하기 위한 공정 Download PDFInfo
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- KR870010635A KR870010635A KR870003329A KR870003329A KR870010635A KR 870010635 A KR870010635 A KR 870010635A KR 870003329 A KR870003329 A KR 870003329A KR 870003329 A KR870003329 A KR 870003329A KR 870010635 A KR870010635 A KR 870010635A
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- 238000000034 method Methods 0.000 title claims abstract 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract 7
- 125000006850 spacer group Chemical group 0.000 claims abstract 3
- 238000009792 diffusion process Methods 0.000 claims abstract 2
- 230000000873 masking effect Effects 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims 5
- 238000005468 ion implantation Methods 0.000 claims 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 5
- 238000002347 injection Methods 0.000 claims 4
- 239000007924 injection Substances 0.000 claims 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- -1 phosphorus ions Chemical class 0.000 claims 3
- 229910052710 silicon Inorganic materials 0.000 claims 3
- 239000010703 silicon Substances 0.000 claims 3
- 238000007740 vapor deposition Methods 0.000 claims 3
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 2
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 claims 2
- 229910052796 boron Inorganic materials 0.000 claims 2
- 230000000295 complement effect Effects 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 2
- 239000007943 implant Substances 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 2
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- 230000000694 effects Effects 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 238000001465 metallisation Methods 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 - 6 도는 반도체기판의 부분적인 개략측 단면도.
Claims (14)
- VLSI-기술을 이용하여 최적의 상보형 MOS-전계효과 트랜지스터(CMOS-회로)를 제조하기위한 공정에 관한 것으로, 각 회로에 n 및 p-챈널 트랜지스터를 공급하기 위해 p 및 n-도우프된 트로프가 실리콘 기판에 제공되고, 여러트랜지스터의 스타트 전압을 설정하기 위해 위의 트로프속에 적당한 불순물 원자가 다중 이온주입에 의해 삽입되며, 각각의 이온 주입단계를 위한 마스킹은 포토레지스트 구조 및 또는 실리콘 산화물 또는 실리콘 절화물 구조를 사용하여 수행되고, 또한 케이트 표면밑에 주입된 소오스 드레인 존으로부터 확산을 감소하기 위해 게이트 전극은 측벽 산화물층(스페이서 산화물)을 갖고 있으며, 그리고 소오스 드레인 존과 게이트존의 제조, 중간 산화물 및 절연산화물층의 제조 그리고 접촉 금속레벨의 제조는 MOS-기술의 공정단계를 사용하여 수행되고, 상기 공정이 다음의 공정단계들 ;a) n 및 p-도우프된 트로프, 액티브 트랜지스터존을 분리하는 필드 산화물 영역, n 및 p-챈널 트랜지스터를 위한 챈널주입 그리고 트랜지스터의 게이트존이 이미 공지된 방법에 의해 완성된 p 또는 n-도우프된 실리콘 기판위에 제조될 p-챈널 트랜지스터의 게이트의 측벽산화물층의 폭에 상응하는 두께로 첫번째 SiO2층을 증착하는 단계 :b) SiO2층위에 실리콘 질화물층을 증착하는 단계 :c) 포토-레지스트 마스크를 형성하고, 잔류 p-챈널 존이 SiO2/실리콘질화물의 이중층에 의해 덮혀지도록 이중층을 구조화하는 단계 :d) 포토-레지스트마스크의 제거후 열산화를 수행하는 단계 :e) n-챈널 트랜지스터를 위한 터미널주입단계를 수행하는 단계 :f) 두번째 SiO2층의 증착되고, n-챈널 게이트 전극의 측벽에 산화물존이 잔류하는 방법으로 상기 두번째 SiO2층을 제거하는 이방성 에칭단계 :g) n-챈널 트랜지스터를 제조하기위한 소오스/드레인 이온 주입단계를 수행하고, 주입된 불순물을 드라이빙-인 하는 단계 :h) SiO2/실리콘 질화물의 이중층으로 덮혀지지않는 n-챈널 존에 포토-레지스트 마스크를 가하고, p-챈널 존에 남아있는 두번째 SiO2층의 잔류물을 제거하는 단계 :i) 실리콘 질화물층을 제거하는 단계 :j) p-챈널 존에있는 게이트 전극의 측벽에 산화물존이 남고, 액티브 트랜지스터 존위에 50nm 이하의 두께로 잔류 산화물층을 남도록 첫번째 SiO2층을 제거하는 이방성 에칭단계 :k) p-챈널 트랜지스터를 제조하는 소오스/드레인 이온주입 단계를 수행하고, n-챈널 존위에 있는 포토-레지스트 마스크를 제거하는 단계 :l) 중간절연산화물, 접촉구멍 존 그리고 금속배선을 공지된 방법으로 제조하는 단계로 구성되는 것을 특징으로하는 최적의 상보형 MOS-FET를 제조하기위한 공정.
- 제 1 항에 있어서,첫번째 SiO2층이 가스단계로부터 증착(화학증착(CVD))에 의해 a)에서 제조되고, 이것의 두께가 적어도 100nm가 되는 것을 특징으로 하는 제조공정.
- 제 1 항에 있어서,실리콘 질화물층이 가스단계로부터 증착(CVD)에 의해 공정단계 b)에서 제조되고, 이것의 두께범위가 50∼100nm가 되는 것을 특징으로 하는 제조공정.
- 제 1 항에 있어서,두번째 SiO2층이 가스단계로부터 증착(CVD)에 의해 공정단계 f)에서 제조되고, 이것의 두께범위가 150∼300nm가 되는 것을 특징으로 하는 제조공정.
- 제 1 항에 있어서,30-50㎚의 두께로 SiO2층이 형성되는 방법으로 열산화가 공정단계 d)에서 행해지는 것을 특징으로 하는 제조공정.
- 제 1 항에 있어서,n-챈널 트랜지스터를 위한 터미널주입이 80keV의 에너지에서 5×1012-1×1013cm-2의 인 이온을 사용하여 공정단계 e)에서 수행되는 것을 특징으로하는 제조공정.
- 제 1 항에 있어서,n-챈널 트랜지스터를 위한 소오스/드레인 주입이 80keV의 에너지에서 3×1015-8×1015cm-2의 비소 이온을 사용하여 공정단계 g)에서 수행되는 것을 특징으로 하는 제조공정.
- 제 7 항에 있어서,주입전에, 분산된 산화물층이 30-50㎚ 범위의 두께로 가해지는 것을 특징으로하는 제조공정.
- 제 1 항에 있어서,공정단계 j)에서 형성된 잔류 산화물층의 두께가 약 50㎚인 것을 특징으로하는 제조공정.
- 제 1 항에 있어서,p-챈널 트랜지스터를 위한 소오스/드레인 주임이 25keV의 에너지에서 5×1015cm-2의 붕소이온을 사용하여 수행되는 것을 특징으로하는 제조공정.
- 제 1 항 또는 제 2 항 또는 제 3 항에 있어서,공정단계 b)가 생략되고, 두번째 SiO2층 대신에 도우프 되지않은 폴리실리콘층이 0.2-0.4㎛의 두께로 공정단계 f)에서 가해지는 것을 특징으로하는 제조공정.
- 제 1 항에 있어서,공정단계 a)에서 첫번째 SiO2층을 가하기전에 25-50keV의 에너지와 1012cm-2의 량을 갖는 붕소이온 주입이 전표면위에서 수행되는 것을 특징으로하는 제조공정.
- 제 1 항에 있어서,공정단계 j)가 생략되고 그리고 소오스/드레인 도우핑이 게이트 전극 바로 밑으로 뻗는 것과 같이 되도록 첫번째 SiO2층의 두께, 공정단계 k)에서 소오스/드레인 주입에 대한 주입에너지, 그리고 그 온도공정이 설정되는 것을 특징으로하는 제조공정.
- 제 1 항을 특징으로하는 공정에 의해 제조되는 최적의 CMOS-FET.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3611797 | 1986-04-08 | ||
| DE3611797.8 | 1986-04-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870010635A true KR870010635A (ko) | 1987-11-30 |
| KR950011781B1 KR950011781B1 (ko) | 1995-10-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019870003329A KR950011781B1 (ko) | 1986-04-08 | 1987-04-08 | Vlsi기술을 이용한 최적의 cm0s-fet의 제조방법 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US4760033A (ko) |
| EP (1) | EP0244607B1 (ko) |
| JP (1) | JPH0783057B2 (ko) |
| KR (1) | KR950011781B1 (ko) |
| AT (1) | ATE90477T1 (ko) |
| CA (1) | CA1268862A (ko) |
| DE (1) | DE3786111D1 (ko) |
| HK (1) | HK47895A (ko) |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5247199A (en) * | 1986-01-15 | 1993-09-21 | Harris Corporation | Process for forming twin well CMOS integrated circuits |
| US5024960A (en) * | 1987-06-16 | 1991-06-18 | Texas Instruments Incorporated | Dual LDD submicron CMOS process for making low and high voltage transistors with common gate |
| US5173760A (en) * | 1987-11-03 | 1992-12-22 | Samsung Electronics Co., Ltd. | BiCMOS semiconductor device |
| KR900005353B1 (ko) * | 1987-11-03 | 1990-07-27 | 삼성전자 주식회사 | 반도체 장치의 제조방법 |
| IT1223571B (it) * | 1987-12-21 | 1990-09-19 | Sgs Thomson Microelectronics | Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte |
| US5286998A (en) * | 1989-05-31 | 1994-02-15 | Fujitsu Limited | Semiconductor device having two transistors forming a memory cell and a peripheral circuit, wherein the impurity region of the first transistor is not subjected to an etching atmosphere |
| FR2648622B1 (fr) * | 1989-06-14 | 1991-08-30 | Commissariat Energie Atomique | Procede de fabrication d'un circuit integre comportant un transistor a effet de champ a double implantation |
| US5024959A (en) * | 1989-09-25 | 1991-06-18 | Motorola, Inc. | CMOS process using doped glass layer |
| GB2237445B (en) * | 1989-10-04 | 1994-01-12 | Seagate Microelectron Ltd | A semiconductor device fabrication process |
| US5102816A (en) * | 1990-03-27 | 1992-04-07 | Sematech, Inc. | Staircase sidewall spacer for improved source/drain architecture |
| KR950000141B1 (ko) * | 1990-04-03 | 1995-01-10 | 미쓰비시 뎅끼 가부시끼가이샤 | 반도체 장치 및 그 제조방법 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7604986A (nl) * | 1976-05-11 | 1977-11-15 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleider- inrichting, en inrichting vervaardigd door toe- passing van de werkwijze. |
| DE3149185A1 (de) * | 1981-12-11 | 1983-06-23 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
| US4590663A (en) * | 1982-02-01 | 1986-05-27 | Texas Instruments Incorporated | High voltage CMOS technology with N-channel source/drain extensions |
| DE3314450A1 (de) * | 1983-04-21 | 1984-10-25 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
| US4577391A (en) * | 1984-07-27 | 1986-03-25 | Monolithic Memories, Inc. | Method of manufacturing CMOS devices |
| US4642878A (en) * | 1984-08-28 | 1987-02-17 | Kabushiki Kaisha Toshiba | Method of making MOS device by sequentially depositing an oxidizable layer and a masking second layer over gated device regions |
| US4701423A (en) * | 1985-12-20 | 1987-10-20 | Ncr Corporation | Totally self-aligned CMOS process |
| US4703551A (en) * | 1986-01-24 | 1987-11-03 | Ncr Corporation | Process for forming LDD MOS/CMOS structures |
-
1987
- 1987-03-04 US US07/021,795 patent/US4760033A/en not_active Expired - Lifetime
- 1987-03-19 DE DE8787104024T patent/DE3786111D1/de not_active Expired - Lifetime
- 1987-03-19 EP EP87104024A patent/EP0244607B1/de not_active Expired - Lifetime
- 1987-03-19 AT AT87104024T patent/ATE90477T1/de not_active IP Right Cessation
- 1987-04-03 JP JP62082759A patent/JPH0783057B2/ja not_active Expired - Lifetime
- 1987-04-06 CA CA000533891A patent/CA1268862A/en not_active Expired - Lifetime
- 1987-04-08 KR KR1019870003329A patent/KR950011781B1/ko not_active IP Right Cessation
-
1995
- 1995-03-30 HK HK47895A patent/HK47895A/xx not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| HK47895A (en) | 1995-04-07 |
| EP0244607A1 (de) | 1987-11-11 |
| KR950011781B1 (ko) | 1995-10-10 |
| EP0244607B1 (de) | 1993-06-09 |
| DE3786111D1 (de) | 1993-07-15 |
| JPS62242358A (ja) | 1987-10-22 |
| CA1268862A (en) | 1990-05-08 |
| ATE90477T1 (de) | 1993-06-15 |
| US4760033A (en) | 1988-07-26 |
| JPH0783057B2 (ja) | 1995-09-06 |
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