HK47895A - Method of producing optimized cmos field effect transistors of the vlsi technique - Google Patents
Method of producing optimized cmos field effect transistors of the vlsi techniqueInfo
- Publication number
- HK47895A HK47895A HK47895A HK47895A HK47895A HK 47895 A HK47895 A HK 47895A HK 47895 A HK47895 A HK 47895A HK 47895 A HK47895 A HK 47895A HK 47895 A HK47895 A HK 47895A
- Authority
- HK
- Hong Kong
- Prior art keywords
- channel
- field effect
- effect transistors
- cmos field
- manufacture
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 4
- 230000005669 field effect Effects 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3611797 | 1986-04-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
HK47895A true HK47895A (en) | 1995-04-07 |
Family
ID=6298231
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HK47895A HK47895A (en) | 1986-04-08 | 1995-03-30 | Method of producing optimized cmos field effect transistors of the vlsi technique |
Country Status (8)
Country | Link |
---|---|
US (1) | US4760033A (xx) |
EP (1) | EP0244607B1 (xx) |
JP (1) | JPH0783057B2 (xx) |
KR (1) | KR950011781B1 (xx) |
AT (1) | ATE90477T1 (xx) |
CA (1) | CA1268862A (xx) |
DE (1) | DE3786111D1 (xx) |
HK (1) | HK47895A (xx) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5247199A (en) * | 1986-01-15 | 1993-09-21 | Harris Corporation | Process for forming twin well CMOS integrated circuits |
US5024960A (en) * | 1987-06-16 | 1991-06-18 | Texas Instruments Incorporated | Dual LDD submicron CMOS process for making low and high voltage transistors with common gate |
KR900005353B1 (ko) * | 1987-11-03 | 1990-07-27 | 삼성전자 주식회사 | 반도체 장치의 제조방법 |
US5173760A (en) * | 1987-11-03 | 1992-12-22 | Samsung Electronics Co., Ltd. | BiCMOS semiconductor device |
IT1223571B (it) * | 1987-12-21 | 1990-09-19 | Sgs Thomson Microelectronics | Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte |
US5286998A (en) * | 1989-05-31 | 1994-02-15 | Fujitsu Limited | Semiconductor device having two transistors forming a memory cell and a peripheral circuit, wherein the impurity region of the first transistor is not subjected to an etching atmosphere |
FR2648622B1 (fr) * | 1989-06-14 | 1991-08-30 | Commissariat Energie Atomique | Procede de fabrication d'un circuit integre comportant un transistor a effet de champ a double implantation |
US5024959A (en) * | 1989-09-25 | 1991-06-18 | Motorola, Inc. | CMOS process using doped glass layer |
GB2237445B (en) * | 1989-10-04 | 1994-01-12 | Seagate Microelectron Ltd | A semiconductor device fabrication process |
US5102816A (en) * | 1990-03-27 | 1992-04-07 | Sematech, Inc. | Staircase sidewall spacer for improved source/drain architecture |
KR950000141B1 (ko) * | 1990-04-03 | 1995-01-10 | 미쓰비시 뎅끼 가부시끼가이샤 | 반도체 장치 및 그 제조방법 |
US6078079A (en) * | 1990-04-03 | 2000-06-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
DE69132695T2 (de) * | 1990-05-11 | 2002-06-13 | Koninklijke Philips Electronics N.V., Eindhoven | CMOS-Verfahren mit Verwendung von zeitweilig angebrachten Siliciumnitrid-Spacern zum Herstellen von Transistoren (LDD) mit leicht dotiertem Drain |
JPH0434968A (ja) * | 1990-05-30 | 1992-02-05 | Mitsubishi Electric Corp | 相補型電界効果トランジスタおよびその製造方法 |
US5045486A (en) * | 1990-06-26 | 1991-09-03 | At&T Bell Laboratories | Transistor fabrication method |
US5166087A (en) * | 1991-01-16 | 1992-11-24 | Sharp Kabushiki Kaisha | Method of fabricating semiconductor element having lightly doped drain (ldd) without using sidewalls |
JP2625602B2 (ja) * | 1991-01-18 | 1997-07-02 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 集積回路デバイスの製造プロセス |
JP2982383B2 (ja) * | 1991-06-25 | 1999-11-22 | 日本電気株式会社 | Cmosトランジスタの製造方法 |
KR940005802B1 (ko) * | 1991-07-09 | 1994-06-23 | 삼성전자 주식회사 | Cmos 반도체장치 및 그 제조방법 |
US6489209B1 (en) * | 1991-08-22 | 2002-12-03 | Ngb Corporation | Manufacturing method of LDD-type MOSFET |
US5268324A (en) * | 1992-05-27 | 1993-12-07 | International Business Machines Corporation | Modified silicon CMOS process having selectively deposited Si/SiGe FETS |
US6432759B1 (en) * | 1992-11-24 | 2002-08-13 | Lsi Logic Corporation | Method of forming source and drain regions for CMOS devices |
US5460998A (en) * | 1995-03-17 | 1995-10-24 | Taiwan Semiconductor Manufacturing Company | Integrated P+ implant sequence in DPDM process for suppression of GIDL |
US5460993A (en) * | 1995-04-03 | 1995-10-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers |
US5770498A (en) * | 1996-01-31 | 1998-06-23 | Micron Technology, Inc. | Process for forming a diffusion barrier using an insulating spacer layer |
US6346439B1 (en) * | 1996-07-09 | 2002-02-12 | Micron Technology, Inc. | Semiconductor transistor devices and methods for forming semiconductor transistor devices |
US5899747A (en) * | 1997-01-27 | 1999-05-04 | Vanguard International Semiconductor Corporation | Method for forming a tapered spacer |
WO2000039858A2 (en) | 1998-12-28 | 2000-07-06 | Fairchild Semiconductor Corporation | Metal gate double diffusion mosfet with improved switching speed and reduced gate tunnel leakage |
US6461923B1 (en) * | 1999-08-18 | 2002-10-08 | Advanced Micro Devices, Inc. | Sidewall spacer etch process for improved silicide formation |
US6303421B1 (en) * | 2000-07-17 | 2001-10-16 | United Microelectronics Corp. | Method of manufacturing CMOS sensor |
US7078296B2 (en) | 2002-01-16 | 2006-07-18 | Fairchild Semiconductor Corporation | Self-aligned trench MOSFETs and methods for making the same |
US7541234B2 (en) | 2005-11-03 | 2009-06-02 | Samsung Electronics Co., Ltd. | Methods of fabricating integrated circuit transistors by simultaneously removing a photoresist layer and a carbon-containing layer on different active areas |
US20080023776A1 (en) * | 2006-07-25 | 2008-01-31 | Micrel, Incorporated | Metal oxide semiconductor device with improved threshold voltage and drain junction breakdown voltage and method for fabricating same |
US20130078774A1 (en) * | 2011-09-22 | 2013-03-28 | Nanya Technology Corporation | Method for forming dope regions with rapid thermal process |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL7604986A (nl) * | 1976-05-11 | 1977-11-15 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleider- inrichting, en inrichting vervaardigd door toe- passing van de werkwijze. |
DE3149185A1 (de) * | 1981-12-11 | 1983-06-23 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
US4590663A (en) * | 1982-02-01 | 1986-05-27 | Texas Instruments Incorporated | High voltage CMOS technology with N-channel source/drain extensions |
DE3314450A1 (de) * | 1983-04-21 | 1984-10-25 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
US4577391A (en) * | 1984-07-27 | 1986-03-25 | Monolithic Memories, Inc. | Method of manufacturing CMOS devices |
EP0173953B1 (en) * | 1984-08-28 | 1991-07-17 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having a gate electrode |
US4701423A (en) * | 1985-12-20 | 1987-10-20 | Ncr Corporation | Totally self-aligned CMOS process |
US4703551A (en) * | 1986-01-24 | 1987-11-03 | Ncr Corporation | Process for forming LDD MOS/CMOS structures |
-
1987
- 1987-03-04 US US07/021,795 patent/US4760033A/en not_active Expired - Lifetime
- 1987-03-19 EP EP87104024A patent/EP0244607B1/de not_active Expired - Lifetime
- 1987-03-19 AT AT87104024T patent/ATE90477T1/de not_active IP Right Cessation
- 1987-03-19 DE DE8787104024T patent/DE3786111D1/de not_active Expired - Lifetime
- 1987-04-03 JP JP62082759A patent/JPH0783057B2/ja not_active Expired - Lifetime
- 1987-04-06 CA CA000533891A patent/CA1268862A/en not_active Expired - Lifetime
- 1987-04-08 KR KR1019870003329A patent/KR950011781B1/ko not_active IP Right Cessation
-
1995
- 1995-03-30 HK HK47895A patent/HK47895A/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US4760033A (en) | 1988-07-26 |
CA1268862A (en) | 1990-05-08 |
DE3786111D1 (de) | 1993-07-15 |
ATE90477T1 (de) | 1993-06-15 |
JPS62242358A (ja) | 1987-10-22 |
EP0244607A1 (de) | 1987-11-11 |
KR950011781B1 (ko) | 1995-10-10 |
EP0244607B1 (de) | 1993-06-09 |
JPH0783057B2 (ja) | 1995-09-06 |
KR870010635A (ko) | 1987-11-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PF | Patent in force | ||
PE | Patent expired |
Effective date: 20070318 |