KR870009487A - 개량된 집적회로 - Google Patents

개량된 집적회로 Download PDF

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Publication number
KR870009487A
KR870009487A KR870001814A KR870001814A KR870009487A KR 870009487 A KR870009487 A KR 870009487A KR 870001814 A KR870001814 A KR 870001814A KR 870001814 A KR870001814 A KR 870001814A KR 870009487 A KR870009487 A KR 870009487A
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KR
South Korea
Prior art keywords
substrate
dope
well
base
implanted
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KR870001814A
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English (en)
Inventor
지오프레이 헌트 로우랜드
Original Assignee
마아크 차알즈 데니스
에쓰피씨 피엘씨
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=10595315&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR870009487(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 마아크 차알즈 데니스, 에쓰피씨 피엘씨 filed Critical 마아크 차알즈 데니스
Publication of KR870009487A publication Critical patent/KR870009487A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/919—Compensation doping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

개량된 집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도―제2도는 반도체 기질내에 도프웰(doped well)의 조립상태의 연속단계를 보여주는 도면.
제8도는 제1도―제2도의 웰내에서의 쌍극성 트랜지스터 조립을 설명하는 도면.

Claims (9)

  1. 반도체 기질의 주표면에 도프된 웰(doped well)을 형성하는 방법에 있어서, 제1도프제(dopant)를 웰구역에 주입하고 제1도프제 반대전도성(opposite conductivity type)의 제2도프제를 웰구역의 표면에 유입시키어, 전술한 도프제들의 부분적 보상(partlai compensation)의 영향을 받아 정미 최대 농춘(net maximum concentration)이 표면 아래에 배열됨을 포함하는 방법.
  2. 제1항에 있어서, 전술한 제1 및 제2도프제가 각기 이온착상제(ion impiant)를 포함하는 방법.
  3. 제2항에 있어서, 전술한 제1도프제가 비소와 인으로 구성된 그룹으로부터 선택되는 방법.
  4. 제2항에 있어서, 전술한 제2도프제가 보론인 방법.
  5. 제1항 제2항 혹은 제3항에 있어서, 정미 표면 도프제준위(net surface dopant level)가 1.5×1015－1.5×1016cm－3인 방법.
  6. 제5항에 있어서, 최대 정미 도프제준위(maximum net dopant level)가 4.5×1015－4.5×1016cm－3인 방법.
  7. 제6항에 있어서, 최대 정미 도프제준위가 반도체 표면과 2－3미크론의 깊이인 방법.
  8. 규소기질의 주표면에 도프된 웰을 형성하는 방법에 있어서, 인이온을 웰구역내의 기질속으로 착상(implant)시키고 기질을 가열하여 착상상태로 유도하고 보론이온을 웰구역내로 착상하고 기질을 가열하여 보론이온 착상으로 유도하고, 여기서 두 이온의 상호착상된 도우스(implant doses)가 웰구역내에서 영향을 받음을 포함하는 방법.
  9. 쌍극성 폴리실리콘 에미터 트랜지스터를 제조하는 방법에 있어서, 기질에 정미 최대 도프제 농축이 반도체 표면 아래에 배열된 도프된 웰을 구비하고, 베이스구역을 형성하며, 베이스구역과 접촉하는 폴리실리콘 에미터를 구비하며, 베이스구역에 인접한 베이스접촉구역을 착상하고, 전술한 에미터는 착상이 정렬된 마스크를 구비하고 콜렉터접촉구역을 구비하며, 콜렉터접촉구역과 베이스 및 에미터에 접촉하는 금속접점을 공급함을 포함하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR870001814A 1986-03-26 1987-03-02 개량된 집적회로 KR870009487A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8607593 1986-03-26
GB8607593A GB2188478B (en) 1986-03-26 1986-03-26 Forming doped wells in sillicon subtstrates

Publications (1)

Publication Number Publication Date
KR870009487A true KR870009487A (ko) 1987-10-27

Family

ID=10595315

Family Applications (1)

Application Number Title Priority Date Filing Date
KR870001814A KR870009487A (ko) 1986-03-26 1987-03-02 개량된 집적회로

Country Status (6)

Country Link
US (1) US4873199A (ko)
EP (1) EP0239217B1 (ko)
JP (1) JPS62235781A (ko)
KR (1) KR870009487A (ko)
DE (1) DE3766397D1 (ko)
GB (2) GB2188478B (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146304A (en) * 1988-12-22 1992-09-08 Honeywell Inc. Self-aligned semiconductor device
US5141882A (en) * 1989-04-05 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor
US4983531A (en) * 1990-02-12 1991-01-08 Motorola, Inc. Method of fabricating a single polysilicon bipolar transistor which is compatible with a method of fabricating CMOS transistors
US5187109A (en) * 1991-07-19 1993-02-16 International Business Machines Corporation Lateral bipolar transistor and method of making the same
EP0645821B1 (en) * 1993-09-27 2001-09-26 STMicroelectronics S.r.l. Low noise bipolar transistor
US6894366B2 (en) * 2000-10-10 2005-05-17 Texas Instruments Incorporated Bipolar junction transistor with a counterdoped collector region

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2006729C3 (de) * 1970-02-13 1980-02-14 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer Halbleiterdiode
DE2554426C3 (de) * 1975-12-03 1979-06-21 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Erzeugung einer lokal hohen inversen Stromverstärkung bei einem Planartransistor sowie nach diesem Verfahren hergestellter invers betriebener Transistor
JPS543479A (en) * 1977-06-09 1979-01-11 Toshiba Corp Semiconductor device and its manufacture
US4151009A (en) * 1978-01-13 1979-04-24 Bell Telephone Laboratories, Incorporated Fabrication of high speed transistors by compensation implant near collector-base junction
DE2835121A1 (de) * 1978-08-10 1980-02-14 Fraunhofer Ges Forschung Verfahren und vorrichtung zum dotieren von halbleitern mittels ionenimplantation
FR2445617A1 (fr) * 1978-12-28 1980-07-25 Ibm France Resistance a tension de claquage amelioree obtenue par une double implantation ionique dans un substrat semi-conducteur et son procede de fabrication
JPS5852817A (ja) * 1981-09-25 1983-03-29 Hitachi Ltd 半導体装置及びその製造方法
US4573064A (en) * 1981-11-02 1986-02-25 Texas Instruments Incorporated GaAs/GaAlAs Heterojunction bipolar integrated circuit devices
GB2135118B (en) * 1983-02-09 1986-10-08 Westinghouse Brake & Signal Thyristors

Also Published As

Publication number Publication date
GB2188478A (en) 1987-09-30
JPS62235781A (ja) 1987-10-15
EP0239217A2 (en) 1987-09-30
GB2188478B (en) 1989-11-22
GB2212327A (en) 1989-07-19
DE3766397D1 (de) 1991-01-10
GB2212327B (en) 1989-12-06
GB8607593D0 (en) 1986-04-30
EP0239217B1 (en) 1990-11-28
GB8905393D0 (en) 1989-04-19
US4873199A (en) 1989-10-10
EP0239217A3 (en) 1988-08-17

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