KR870009449A - 유전체 에칭 중지 물질과의 비프례임식 바이어 상호 연결방법 - Google Patents

유전체 에칭 중지 물질과의 비프례임식 바이어 상호 연결방법 Download PDF

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KR870009449A
KR870009449A KR870002590A KR870002590A KR870009449A KR 870009449 A KR870009449 A KR 870009449A KR 870002590 A KR870002590 A KR 870002590A KR 870002590 A KR870002590 A KR 870002590A KR 870009449 A KR870009449 A KR 870009449A
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metal oxide
layer
via opening
insulating metal
dielectric layer
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제롬 김 만진
프레드릭 그리핑 브루스
윌리암스 켈리 대비드
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아더 엠·킹
제너럴 일렉트릭 컴패니
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
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    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Abstract

내용 없음

Description

유전체 에칭 중지 물질과의 비프레임식 바이어 상호 연결방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1―3도는 본 발명의 방법에 따라서 2개의 바이어 개구 형성과정을 개략적으로 예시한 일련의 횡단면도.

Claims (21)

  1. 특히, 전기 집적회로장치 제조시, 바이어 개구 형성방법에 있어서,
    유전체층을 그 안에서 바이어 개구를 구성하도록 에칭하고, 상기 에칭이 상기 유전체층 아래에 놓인 절연 금속 산화물 층의 아래까지 발생하여 상기 절연 금속 산화물을 상기 개구를 통하여 노출시키는 단계와,
    상기 절연 금속 산화물층을 상기 유전체내의 상기 개구를 통하여 도전물질층의 아래까지 에칭하여 상기 도전층이 상기 유전체내 및 절연 금속 산화물층 내의 상기 개구를 통하여 노출되는 단계를 구비하는 바이어 개구 형성방법.
  2. 제1항에 있어서,
    상기 절연 금속 산화물이 알루미늄 산화물을 구비하는 바이어 개구 형성방법.
  3. 제1항에 있어서,
    상기 절연 금속 산화물이 마그네슘 산화물을 구비하는 바이어 개구 형성방법.
  4. 제1항에 있어서,
    상기 유전체층이 실리콘 산화물을 구비하는 바이어 개구 형성방법.
  5. 제1항에 있어서,
    상기 도전물질이 금속을 구비하는 바이어 개구 형성방법.
  6. 제1항에 있어서,
    상기 유전체층의 에칭이 반응 이온 에칭으로 수행되는 바이어 개구 형성방법.
  7. 제6항에 있어서,
    상기 반응 이온 에칭이 NF3및 아르곤을 포함하는 대기에서 수행되는 개구 형성방법.
  8. 제4항에 있어서,
    상기 반응 이온 에칭이 CHF3및 아르곤을 포함하는 대기에서 수행되는 바이어 개구 형성방법.
  9. 제1항에 있어서,
    상기 유전체층의 에칭이 상기 알루미늄산화물에 비교하여 대략 20 대 1의 에칭 선택도를 갖는 바이어 개구 형성방법.
  10. 제1항에 있어서,
    상기 알루미늄 산화물층의 에칭이 BCI3및 산소 가스의 대기에서 수행되는 바이어 개구 형성방법.
  11. 집적된 전기회로 장치의 제조시 바이어 개구 형성방법에 있어서,
    절연 기판위에 놓인 도전층을 증착시켜 패턴화하는 단계와,
    상기 패턴화된 도전층을 카바하는 제 1 유전체층을 증착시키는 단계와,
    상기 제1유전체층을 사이 도전층 레벨의 최소 아래까지 플라나화하는 단계와,
    상기 플라나화된 기판위에 절연 금속 산화물층을 증착시키는 단계와,
    상기 절연 금속 산화물층상에 제2유전체층을 증착시켜 패턴화하고, 상기 제2유전체층 내의 개구가 상기 패턴화된 도전층의 부분위에 최소 부분적으로 구성되어 상기 절연 금속 산화물층의 아래까지 연장하는 단계와,
    상기 제2유전체층 내의 상기 개구를 통하여 노출된 절연 금속 산화물질을 제거하는 단계를 구비하는 바이어 개구 형성방법.
  12. 제11항에 있어서,
    제2도전층을 증착시켜 패턴화하여 상기 제2유전체층 및 상기 절연 금속 산화물 층 내의 상기 개구를 통하여 상기 제1도전층과의 전기 접촉이 이루어지는 단계를 아울러 포함하는 바이어 개구 형성방법.
  13. 제11항에 있어서,
    상기 절연 금속 산화물이 알루미늄 산화물, 마그네슘 산화물 및 스피넬로 이루어지는 그룹으로부터 선택되는 바이어 개구 형성방법.
  14. 반도체 기판상에 절연 금속 산화물의 얇고 균일한 층을 증착시키기 위한 방법에 있어서, 배설 챔버내에 상기 기판 및 상기 금속 또는 금속 산화물의 샘플을 배치하는 단계와,
    감소된 압력으로 산소와 불활성 가스의 혼합물을 스퍼터링을 위해 상기 챔버를 통하여 유동시키는 단계와,
    상기 샘플로부터의 상기 금속을 고주파 전자기 에너지를 사용하여 스퍼터링하는 단계를 구비하는 증착방법.
  15. 제14항에 있어서,
    상기 금속이 알루미늄, 마그네슘 및 , 그 혼합물로 이루어지는 그룹으로부터 선택되는 증착방법.
  16. 제14항에 있어서,
    상기 감소된 압력이 약 12 미크론인 증착방법.
  17. 제14항에 있어서,
    사이 혼합물의 상기 유동 속도가 약 25cc/분인 증착방법.
  18. 제14항에 있어서,
    상기 불활성 가스가 아르곤을 구비하는 증착방법.
  19. 제14항에 있어서,
    상기 혼합물이 체적당 10%의 산소를 구비하는 증착방법.
  20. 제14항에 있어서,
    상기 고주파수가 약 500와트의 직경으로 공급되는 증착방법.
  21. 제14항에 있어서,
    상기 금속 산화물이 금속 산화물의 스퍼터링 소스로부터 증착되는 증착방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR870002590A 1986-03-27 1987-03-21 유전체 에칭 중지 물질과의 비프례임식 바이어 상호 연결방법 KR870009449A (ko)

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US845110 1986-03-27
US06/845,110 US4767724A (en) 1986-03-27 1986-03-27 Unframed via interconnection with dielectric etch stop

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KR870009449A true KR870009449A (ko) 1987-10-26

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JPS62265724A (ja) 1987-11-18
EP0241729A2 (en) 1987-10-21
US4767724A (en) 1988-08-30
EP0241729A3 (en) 1988-07-13

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