KR870008396A - 절연게이트 전계효과 트랜지스터(misfet)의 제조방법 - Google Patents
절연게이트 전계효과 트랜지스터(misfet)의 제조방법 Download PDFInfo
- Publication number
- KR870008396A KR870008396A KR870001294A KR870001294A KR870008396A KR 870008396 A KR870008396 A KR 870008396A KR 870001294 A KR870001294 A KR 870001294A KR 870001294 A KR870001294 A KR 870001294A KR 870008396 A KR870008396 A KR 870008396A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating material
- gate electrode
- forming
- manufacturing
- reflowed
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 230000005669 field effect Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims 12
- 239000000758 substrate Substances 0.000 claims 4
- 238000000151 deposition Methods 0.000 claims 2
- 239000005368 silicate glass Substances 0.000 claims 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/044—Edge diffusion under mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/157—Special diffusion and profiles
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/161—Tapered edges
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/919—Elements of similar construction connected in series or parallel to average out manufacturing variations in characteristics
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/965—Shaped junction formation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 5 도는 내지 제 9 도는 본 발명에 의한 MIS FET제조공정 단계의 횡단면도로서, 게이트 전극의 양측면상의 리후로우 (reflow)되는 측벽을 형성하는 제 1 방법을 나타내는 도면.
Claims (6)
- (1) 실리콘 기판상에 게이트 절연막과 게이트 전극을 형성하는 단계와.(2) 상기 게이트 전국 양측면상에 리후로우되는 절연층의 측벽을 형성하는 단계와,(30 마스크로서 상기 게이트 전극과 상기 측벽들을 사용하여 상기 MISFET의 소오스와 드레인 영역들을 형성하도록 상기 기판내로 불순물 이온들을 주입시키는 단계를 포함하는,MIS FET의 제조방법.
- 제 1 항에서, 상기 리후로우되는 절연재의 측벽을 형성하는 상기 단계(2)는 :(4) 상기 기판과 상기 게이트 전극상에 절연재를 증착시키는 부차단계와,(5) 상기 절연재를 리후로우하는 부차단계와,(6) 상기 게이트 전극의 표면이 노출되는 한편 상기 절연재의 구배진 측벽이 게이트 전극의 양측면들상에 남아있을 때까지 상기 리후로우되는 절연재를 시각하는 부차단계를 포함하는 MISFET의 제조방법.
- 제 1 항에서, 리후로우되는 절연재의 측벽을 형성하는 상기 단계(2)는 :(7) 상기 기판과 상기 게이트 전극상에 절연재를 증착시키는 부차단계와,(8) 상기 게이트 전극의 표면이 노출되는 한편 상기 절연재의 측벽부분이 게이트전극의 양측면들상에 남아있을 때까지 상기 절연재를 비등방성으로 시각하는 부차단계와, 그리고(9) 상기 절연재를 리후로우하는 부차단계를 포함하는,MISFET의 제조방법.
- 제 1,2 또는 3 항에서, 단계(2)(4) 또는 (7)의 상기 절연재는 1100℃이하의 리후로우 온도를 갖는 도우프된 규산염 유리인 것이 특징인 MISFET의 제조방법.
- 제 4 항에서, 상기 규산염 유리는 인(P), 붕소(B) 또는 비소(As)또는 그의 조합으로 된 산화물로서 도우프되는 MISFET의 제조방법.
- 제 2 항에서, 상기 식각단계(6)는 상기 게이트 전극의 표면이 노출되고 또한 그의 표면연부가 부분적으로 더 제거되는 한편 상기 절연재의 구배진 측벽이 게이트 전극의 양측면들상에 남아서 연속된 곡면을 형성할 때까지 수행되는 MISFET의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33236 | 1986-02-17 | ||
JP3323786A JPS62208673A (ja) | 1986-02-17 | 1986-02-17 | 半導体装置の製造方法 |
JP33237 | 1986-02-17 | ||
JP3323686A JPS62208672A (ja) | 1986-02-17 | 1986-02-17 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR870008396A true KR870008396A (ko) | 1987-09-26 |
KR900003840B1 KR900003840B1 (en) | 1990-06-02 |
Family
ID=26371913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR8701294A KR900003840B1 (en) | 1986-02-17 | 1987-02-17 | Insulation gate field effect transistor manufacturing method |
Country Status (3)
Country | Link |
---|---|
US (1) | US4755479A (ko) |
EP (1) | EP0233823A3 (ko) |
KR (1) | KR900003840B1 (ko) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0831602B2 (ja) * | 1986-06-30 | 1996-03-27 | 沖電気工業株式会社 | Mis型電界効果トランジスタの製造方法 |
JPS63224240A (ja) * | 1987-03-12 | 1988-09-19 | Fuji Xerox Co Ltd | 半導体集積回路装置 |
JPH0626219B2 (ja) * | 1987-11-05 | 1994-04-06 | シャープ株式会社 | イオン注入方法 |
JPH01123417A (ja) * | 1987-11-07 | 1989-05-16 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
FR2625608B1 (fr) * | 1988-01-04 | 1990-06-15 | Sgs Thomson Microelectronics | Procede de fabrication d'un circuit integre comprenant des elements a deux niveaux de grille |
JP2513023B2 (ja) * | 1988-10-24 | 1996-07-03 | 三菱電機株式会社 | 電界効果型半導体装置およびその製造方法 |
DE69029046T2 (de) * | 1989-03-16 | 1997-03-06 | Sgs Thomson Microelectronics | Kontakte für Halbleiter-Vorrichtungen |
JPH0316123A (ja) * | 1989-03-29 | 1991-01-24 | Mitsubishi Electric Corp | イオン注入方法およびそれにより製造される半導体装置 |
US5202276A (en) * | 1990-08-20 | 1993-04-13 | Texas Instruments Incorporated | Method of forming a low on-resistance DMOS vertical transistor structure |
US5196360A (en) * | 1990-10-02 | 1993-03-23 | Micron Technologies, Inc. | Methods for inhibiting outgrowth of silicide in self-aligned silicide process |
US5234852A (en) * | 1990-10-10 | 1993-08-10 | Sgs-Thomson Microelectronics, Inc. | Sloped spacer for MOS field effect devices comprising reflowable glass layer |
US5424571A (en) * | 1992-03-30 | 1995-06-13 | Sgs-Thomson Microelectronics, Inc. | Sloped spacer for mos field effect devices |
KR970003838B1 (en) * | 1993-12-16 | 1997-03-22 | Lg Semicon Co Ltd | Fabrication method of ldd mosfet |
US5395781A (en) * | 1994-02-16 | 1995-03-07 | Micron Technology, Inc. | Method of making a semiconductor device using photoresist flow |
US5439831A (en) * | 1994-03-09 | 1995-08-08 | Siemens Aktiengesellschaft | Low junction leakage MOSFETs |
US5501997A (en) * | 1994-05-03 | 1996-03-26 | United Microelectronics Corp. | Process of fabricating semiconductor devices having lightly-doped drain |
US5576230A (en) * | 1994-09-02 | 1996-11-19 | Texas Instruments Incorporated | Method of fabrication of a semiconductor device having a tapered implanted region |
US5877530A (en) * | 1996-07-31 | 1999-03-02 | Lsi Logic Corporation | Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation |
US5923991A (en) * | 1996-11-05 | 1999-07-13 | International Business Machines Corporation | Methods to prevent divot formation in shallow trench isolation areas |
US6054356A (en) * | 1996-12-10 | 2000-04-25 | Advanced Micro Devices, Inc. | Transistor and process of making a transistor having an improved LDD masking material |
US5960315A (en) * | 1997-07-10 | 1999-09-28 | International Business Machines Corporation | Tapered via using sidewall spacer reflow |
US6063679A (en) * | 1997-12-09 | 2000-05-16 | Advanced Micro Devices, Inc. | Spacer formation for graded dopant profile having a triangular geometry |
US6117719A (en) * | 1997-12-18 | 2000-09-12 | Advanced Micro Devices, Inc. | Oxide spacers as solid sources for gallium dopant introduction |
US5811342A (en) * | 1998-01-26 | 1998-09-22 | Texas Instruments - Acer Incorporated | Method for forming a semiconductor device with a graded lightly-doped drain structure |
US6346449B1 (en) * | 1999-05-17 | 2002-02-12 | Taiwan Semiconductor Manufacturing Company | Non-distort spacer profile during subsequent processing |
JP2006237453A (ja) * | 2005-02-28 | 2006-09-07 | Toshiba Corp | 半導体装置及びその製造方法 |
CN101796616A (zh) * | 2007-09-05 | 2010-08-04 | Nxp股份有限公司 | 晶体管及其制造方法 |
WO2009031085A1 (en) * | 2007-09-05 | 2009-03-12 | Nxp B.V. | A transistor and a method of manufacturing the same |
US11682721B2 (en) | 2021-01-20 | 2023-06-20 | Raytheon Company | Asymmetrically angled gate structure and method for making same |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5693367A (en) * | 1979-12-20 | 1981-07-28 | Fujitsu Ltd | Manufacture of semiconductor device |
US4356623A (en) * | 1980-09-15 | 1982-11-02 | Texas Instruments Incorporated | Fabrication of submicron semiconductor devices |
JPS57126147A (en) * | 1981-01-28 | 1982-08-05 | Fujitsu Ltd | Manufacture of semiconductor device |
US4349584A (en) * | 1981-04-28 | 1982-09-14 | Rca Corporation | Process for tapering openings in ternary glass coatings |
US4419809A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
US4507853A (en) * | 1982-08-23 | 1985-04-02 | Texas Instruments Incorporated | Metallization process for integrated circuits |
JPS5947769A (ja) * | 1982-09-13 | 1984-03-17 | Hitachi Ltd | 半導体装置の製造方法 |
JPS5992573A (ja) * | 1982-11-17 | 1984-05-28 | Matsushita Electronics Corp | 絶縁ゲ−ト形電界効果トランジスタの製造方法 |
JPS59208784A (ja) * | 1983-05-12 | 1984-11-27 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS604264A (ja) * | 1983-06-22 | 1985-01-10 | Nec Corp | 絶縁ゲ−ト型電解効果トランジスタ |
FR2549293B1 (fr) * | 1983-07-13 | 1986-10-10 | Silicium Semiconducteur Ssc | Transistor bipolaire haute frequence et son procede de fabrication |
JPS6038879A (ja) * | 1983-08-12 | 1985-02-28 | Hitachi Ltd | 半導体装置の製造方法 |
FR2555365B1 (fr) * | 1983-11-22 | 1986-08-29 | Efcis | Procede de fabrication de circuit integre avec connexions de siliciure de tantale et circuit integre realise selon ce procede |
US4603472A (en) * | 1984-04-19 | 1986-08-05 | Siemens Aktiengesellschaft | Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation |
JPS615580A (ja) * | 1984-06-19 | 1986-01-11 | Toshiba Corp | 半導体装置の製造方法 |
DE3425531A1 (de) * | 1984-07-11 | 1986-01-16 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum verfliessenlassen von dotierten sio(pfeil abwaerts)2(pfeil abwaerts)-schichten bei der herstellung von integrierten mos-halbleiterschaltungen |
US4641420A (en) * | 1984-08-30 | 1987-02-10 | At&T Bell Laboratories | Metalization process for headless contact using deposited smoothing material |
-
1987
- 1987-02-04 US US07/010,667 patent/US4755479A/en not_active Expired - Fee Related
- 1987-02-17 EP EP87400346A patent/EP0233823A3/en not_active Withdrawn
- 1987-02-17 KR KR8701294A patent/KR900003840B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US4755479A (en) | 1988-07-05 |
KR900003840B1 (en) | 1990-06-02 |
EP0233823A2 (en) | 1987-08-26 |
EP0233823A3 (en) | 1988-08-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR870008396A (ko) | 절연게이트 전계효과 트랜지스터(misfet)의 제조방법 | |
KR950021525A (ko) | 얕은 접합의 소오스/드레인 영역과 실리사이드를 갖는 모스트랜지스터의 제조방법 | |
KR950034624A (ko) | 반도체장치의 제조방법 | |
EP0085916A3 (en) | Method of fabricating field effect transistors | |
JPS57196573A (en) | Manufacture of mos type semiconductor device | |
DE3561680D1 (en) | Method of producing highly integrated mos field-effect transistors | |
KR920018972A (ko) | 모오스 fet 제조방법 및 구조 | |
JPS5650535A (en) | Manufacture of semiconductor device | |
KR960019769A (ko) | 박막트랜지스터 및 그 제조방법 | |
JPS56107552A (en) | Manufacture of semiconductor device | |
JPS5585073A (en) | Manufacture of insulation gate type electric field effect transistor | |
JPS55107229A (en) | Method of manufacturing semiconductor device | |
JPS5694671A (en) | Manufacture of mis field-effect semiconductor device | |
JPS5654071A (en) | Insulated gate field-effect transistor | |
JPS62245674A (ja) | 半導体装置の製造方法 | |
JP2570292B2 (ja) | 半導体装置の製造方法 | |
JPH05235337A (ja) | Mis型半導体装置 | |
KR950009978A (ko) | 모스트랜지스터의 제조방법 | |
JPS5670669A (en) | Longitudinal semiconductor device | |
KR970003682A (ko) | 저도핑 드레인 구조의 모스 트랜지스터 제조 방법 | |
JPS5678157A (en) | Semiconductor device | |
KR930015081A (ko) | 얕은 접합 모스패트 제조방법 | |
KR950012645A (ko) | 반도체 장치의 박막 트랜지스터 제조방법 | |
KR880008421A (ko) | 다결정 실리콘 산화막 성장억제 방법 | |
KR920013765A (ko) | Mosfet 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19930512 Year of fee payment: 4 |
|
LAPS | Lapse due to unpaid annual fee |