KR870008396A - 절연게이트 전계효과 트랜지스터(misfet)의 제조방법 - Google Patents

절연게이트 전계효과 트랜지스터(misfet)의 제조방법 Download PDF

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KR870008396A
KR870008396A KR870001294A KR870001294A KR870008396A KR 870008396 A KR870008396 A KR 870008396A KR 870001294 A KR870001294 A KR 870001294A KR 870001294 A KR870001294 A KR 870001294A KR 870008396 A KR870008396 A KR 870008396A
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insulating material
gate electrode
forming
manufacturing
reflowed
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KR900003840B1 (en
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다까오 미우라
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야마모도 다꾸마
후지쓰 가부시끼가이샤
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Priority claimed from JP3323686A external-priority patent/JPS62208672A/ja
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0843Source or drain regions of field-effect devices
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
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    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S257/90MOSFET type gate sidewall insulating spacer
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Abstract

내용 없음

Description

절연게이트 전계효과 트랜지스터(MISFET)의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 5 도는 내지 제 9 도는 본 발명에 의한 MIS FET제조공정 단계의 횡단면도로서, 게이트 전극의 양측면상의 리후로우 (reflow)되는 측벽을 형성하는 제 1 방법을 나타내는 도면.

Claims (6)

  1. (1) 실리콘 기판상에 게이트 절연막과 게이트 전극을 형성하는 단계와.
    (2) 상기 게이트 전국 양측면상에 리후로우되는 절연층의 측벽을 형성하는 단계와,
    (30 마스크로서 상기 게이트 전극과 상기 측벽들을 사용하여 상기 MISFET의 소오스와 드레인 영역들을 형성하도록 상기 기판내로 불순물 이온들을 주입시키는 단계를 포함하는,
    MIS FET의 제조방법.
  2. 제 1 항에서, 상기 리후로우되는 절연재의 측벽을 형성하는 상기 단계(2)는 :
    (4) 상기 기판과 상기 게이트 전극상에 절연재를 증착시키는 부차단계와,
    (5) 상기 절연재를 리후로우하는 부차단계와,
    (6) 상기 게이트 전극의 표면이 노출되는 한편 상기 절연재의 구배진 측벽이 게이트 전극의 양측면들상에 남아있을 때까지 상기 리후로우되는 절연재를 시각하는 부차단계를 포함하는 MISFET의 제조방법.
  3. 제 1 항에서, 리후로우되는 절연재의 측벽을 형성하는 상기 단계(2)는 :
    (7) 상기 기판과 상기 게이트 전극상에 절연재를 증착시키는 부차단계와,
    (8) 상기 게이트 전극의 표면이 노출되는 한편 상기 절연재의 측벽부분이 게이트전극의 양측면들상에 남아있을 때까지 상기 절연재를 비등방성으로 시각하는 부차단계와, 그리고
    (9) 상기 절연재를 리후로우하는 부차단계를 포함하는,
    MISFET의 제조방법.
  4. 제 1,2 또는 3 항에서, 단계(2)(4) 또는 (7)의 상기 절연재는 1100℃이하의 리후로우 온도를 갖는 도우프된 규산염 유리인 것이 특징인 MISFET의 제조방법.
  5. 제 4 항에서, 상기 규산염 유리는 인(P), 붕소(B) 또는 비소(As)또는 그의 조합으로 된 산화물로서 도우프되는 MISFET의 제조방법.
  6. 제 2 항에서, 상기 식각단계(6)는 상기 게이트 전극의 표면이 노출되고 또한 그의 표면연부가 부분적으로 더 제거되는 한편 상기 절연재의 구배진 측벽이 게이트 전극의 양측면들상에 남아서 연속된 곡면을 형성할 때까지 수행되는 MISFET의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR8701294A 1986-02-17 1987-02-17 Insulation gate field effect transistor manufacturing method KR900003840B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP33236 1986-02-17
JP3323786A JPS62208673A (ja) 1986-02-17 1986-02-17 半導体装置の製造方法
JP33237 1986-02-17
JP3323686A JPS62208672A (ja) 1986-02-17 1986-02-17 半導体装置およびその製造方法

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KR870008396A true KR870008396A (ko) 1987-09-26
KR900003840B1 KR900003840B1 (en) 1990-06-02

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JPS5992573A (ja) * 1982-11-17 1984-05-28 Matsushita Electronics Corp 絶縁ゲ−ト形電界効果トランジスタの製造方法
JPS59208784A (ja) * 1983-05-12 1984-11-27 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS604264A (ja) * 1983-06-22 1985-01-10 Nec Corp 絶縁ゲ−ト型電解効果トランジスタ
FR2549293B1 (fr) * 1983-07-13 1986-10-10 Silicium Semiconducteur Ssc Transistor bipolaire haute frequence et son procede de fabrication
JPS6038879A (ja) * 1983-08-12 1985-02-28 Hitachi Ltd 半導体装置の製造方法
FR2555365B1 (fr) * 1983-11-22 1986-08-29 Efcis Procede de fabrication de circuit integre avec connexions de siliciure de tantale et circuit integre realise selon ce procede
US4603472A (en) * 1984-04-19 1986-08-05 Siemens Aktiengesellschaft Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation
JPS615580A (ja) * 1984-06-19 1986-01-11 Toshiba Corp 半導体装置の製造方法
DE3425531A1 (de) * 1984-07-11 1986-01-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zum verfliessenlassen von dotierten sio(pfeil abwaerts)2(pfeil abwaerts)-schichten bei der herstellung von integrierten mos-halbleiterschaltungen
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material

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US4755479A (en) 1988-07-05
KR900003840B1 (en) 1990-06-02
EP0233823A2 (en) 1987-08-26
EP0233823A3 (en) 1988-08-03

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