JPS5654071A - Insulated gate field-effect transistor - Google Patents

Insulated gate field-effect transistor

Info

Publication number
JPS5654071A
JPS5654071A JP13014379A JP13014379A JPS5654071A JP S5654071 A JPS5654071 A JP S5654071A JP 13014379 A JP13014379 A JP 13014379A JP 13014379 A JP13014379 A JP 13014379A JP S5654071 A JPS5654071 A JP S5654071A
Authority
JP
Japan
Prior art keywords
region
type
layer
diffusion
surrounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13014379A
Other languages
Japanese (ja)
Other versions
JPS6241427B2 (en
Inventor
Hiroshi Sakuma
Toshiyuki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13014379A priority Critical patent/JPS5654071A/en
Priority to US06/195,683 priority patent/US4394674A/en
Publication of JPS5654071A publication Critical patent/JPS5654071A/en
Publication of JPS6241427B2 publication Critical patent/JPS6241427B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To control a parasitic bipolar effect by a method wherein a source region is surrounded by a highly concentrated impurities region of the same conduction type as a semiconductor substrate, which is connected with the source region, while excluding a channel region in IGFET having an offset gate structure. CONSTITUTION:P<+> type region 12 corresponded to a source forming region of P<-> type semiconductor substrate 1 is diffusion-formed; a thin P type layer 16 is made epitaxial growth over the whole surface including the above mentioned region and situated at an outer end of a region 12 to ground the substrate 1 and to form P<+> type region 12' for taking out an electrode of the region 12 by making contact with the region 12 within the layer 16. Subsequently, an N type source region 3 touching to the region 12' is diffusion-formed within the layer 16 provided on the region 12, the region 3 is put in the state that it is surrounded by the regions 12 and 12' while excluding the channel 9, an N type drain region 2 which is opposed to the region 3 surrounded and comes from the layer 16 into the substrate 1 is diffusion-formed, and a shallow N<-> type offset gate region 6 is provided directing to the region 9 from the region 2. Thereafter, a gate electrode 4 buried in an insulating film 5 is formed on the layer 16 between the regions 3 and 6.
JP13014379A 1979-10-09 1979-10-09 Insulated gate field-effect transistor Granted JPS5654071A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP13014379A JPS5654071A (en) 1979-10-09 1979-10-09 Insulated gate field-effect transistor
US06/195,683 US4394674A (en) 1979-10-09 1980-10-09 Insulated gate field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13014379A JPS5654071A (en) 1979-10-09 1979-10-09 Insulated gate field-effect transistor

Publications (2)

Publication Number Publication Date
JPS5654071A true JPS5654071A (en) 1981-05-13
JPS6241427B2 JPS6241427B2 (en) 1987-09-02

Family

ID=15026991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13014379A Granted JPS5654071A (en) 1979-10-09 1979-10-09 Insulated gate field-effect transistor

Country Status (1)

Country Link
JP (1) JPS5654071A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0121096A2 (en) * 1983-03-31 1984-10-10 International Business Machines Corporation Semiconductor contact structure
US5229633A (en) * 1987-06-08 1993-07-20 U.S. Philips Corporation High voltage lateral enhancement IGFET
US5304827A (en) * 1991-10-15 1994-04-19 Texas Instruments Incorporated Performance lateral double-diffused MOS transistor
JP2012253230A (en) * 2011-06-03 2012-12-20 Fujitsu Semiconductor Ltd Semiconductor device and method of manufacturing semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0121096A2 (en) * 1983-03-31 1984-10-10 International Business Machines Corporation Semiconductor contact structure
EP0121096A3 (en) * 1983-03-31 1986-02-12 International Business Machines Corporation Semiconductor contact structure
US5229633A (en) * 1987-06-08 1993-07-20 U.S. Philips Corporation High voltage lateral enhancement IGFET
US5304827A (en) * 1991-10-15 1994-04-19 Texas Instruments Incorporated Performance lateral double-diffused MOS transistor
US5382535A (en) * 1991-10-15 1995-01-17 Texas Instruments Incorporated Method of fabricating performance lateral double-diffused MOS transistor
JP2012253230A (en) * 2011-06-03 2012-12-20 Fujitsu Semiconductor Ltd Semiconductor device and method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS6241427B2 (en) 1987-09-02

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