KR850006646A - 적층홈이 없는 단일 결정성 반도체장치 제조방법 - Google Patents
적층홈이 없는 단일 결정성 반도체장치 제조방법Info
- Publication number
- KR850006646A KR850006646A KR1019850002066A KR850002066A KR850006646A KR 850006646 A KR850006646 A KR 850006646A KR 1019850002066 A KR1019850002066 A KR 1019850002066A KR 850002066 A KR850002066 A KR 850002066A KR 850006646 A KR850006646 A KR 850006646A
- Authority
- KR
- South Korea
- Prior art keywords
- manufacturing
- semiconductor device
- single crystal
- crystal semiconductor
- stacked groove
- Prior art date
Links
- 239000013078 crystal Substances 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/017—Clean surfaces
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/025—Deposition multi-step
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/15—Silicon on sapphire SOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59060403A JPS60202952A (ja) | 1984-03-28 | 1984-03-28 | 半導体装置の製造方法 |
JP59-60403 | 1984-03-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR850006646A true KR850006646A (ko) | 1985-10-14 |
KR900000203B1 KR900000203B1 (ko) | 1990-01-23 |
Family
ID=13141166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019850002066A KR900000203B1 (ko) | 1984-03-28 | 1985-03-28 | 적층홈이 없는 단일 결정성 반도체장치 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5037774A (ko) |
EP (1) | EP0159252B1 (ko) |
JP (1) | JPS60202952A (ko) |
KR (1) | KR900000203B1 (ko) |
DE (1) | DE3587377T2 (ko) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4752590A (en) * | 1986-08-20 | 1988-06-21 | Bell Telephone Laboratories, Incorporated | Method of producing SOI devices |
JPH01244608A (ja) * | 1988-03-26 | 1989-09-29 | Fujitsu Ltd | 半導体結晶の成長方法 |
JPH01289108A (ja) * | 1988-05-17 | 1989-11-21 | Fujitsu Ltd | ヘテロエピタキシャル成長方法 |
US5310696A (en) * | 1989-06-16 | 1994-05-10 | Massachusetts Institute Of Technology | Chemical method for the modification of a substrate surface to accomplish heteroepitaxial crystal growth |
US5444302A (en) | 1992-12-25 | 1995-08-22 | Hitachi, Ltd. | Semiconductor device including multi-layer conductive thin film of polycrystalline material |
US5843225A (en) * | 1993-02-03 | 1998-12-01 | Semiconductor Energy Laboratory Co., Ltd. | Process for fabricating semiconductor and process for fabricating semiconductor device |
JP3497198B2 (ja) * | 1993-02-03 | 2004-02-16 | 株式会社半導体エネルギー研究所 | 半導体装置および薄膜トランジスタの作製方法 |
US5639698A (en) * | 1993-02-15 | 1997-06-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor, semiconductor device, and method for fabricating the same |
US6997985B1 (en) | 1993-02-15 | 2006-02-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor, semiconductor device, and method for fabricating the same |
JPH0794420A (ja) * | 1993-09-20 | 1995-04-07 | Fujitsu Ltd | 化合物半導体結晶基板の製造方法 |
US5402749A (en) * | 1994-05-03 | 1995-04-04 | The United States Of America As Represented By The Secretary Of The Navy | Ultra-high vacuum/chemical vapor deposition of epitaxial silicon-on-sapphire |
US5915174A (en) * | 1994-09-30 | 1999-06-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for producing the same |
US5893948A (en) * | 1996-04-05 | 1999-04-13 | Xerox Corporation | Method for forming single silicon crystals using nucleation sites |
US5733641A (en) * | 1996-05-31 | 1998-03-31 | Xerox Corporation | Buffered substrate for semiconductor devices |
US6501094B1 (en) * | 1997-06-11 | 2002-12-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising a bottom gate type thin film transistor |
US6037199A (en) * | 1999-08-16 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | SOI device for DRAM cells beyond gigabit generation and method for making the same |
DE10025871A1 (de) * | 2000-05-25 | 2001-12-06 | Wacker Siltronic Halbleitermat | Epitaxierte Halbleiterscheibe und Verfahren zu ihrer Herstellung |
US6852575B2 (en) * | 2001-07-05 | 2005-02-08 | International Business Machines Corporation | Method of forming lattice-matched structure on silicon and structure formed thereby |
US6933566B2 (en) * | 2001-07-05 | 2005-08-23 | International Business Machines Corporation | Method of forming lattice-matched structure on silicon and structure formed thereby |
US6787433B2 (en) * | 2001-09-19 | 2004-09-07 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
KR101023034B1 (ko) * | 2002-05-07 | 2011-03-24 | 에이에스엠 아메리카, 인코포레이티드 | 절연체상 실리콘 구조 및 방법 |
JP2004165351A (ja) * | 2002-11-12 | 2004-06-10 | Fujitsu Ltd | 半導体装置の製造方法 |
DE102005009725A1 (de) * | 2005-03-03 | 2006-09-07 | Atmel Germany Gmbh | Verfahren zur Integration von zwei Bipolartransistoren in einen Halbleiterkörper, Halbleiteranordnung in einem Halbleiterkörper und Kaskodenschaltung |
EP2206808B1 (en) * | 2008-12-23 | 2017-07-12 | Imec | Method for manufacturing a mono-crystalline semiconductor layer on a substrate |
US8592294B2 (en) * | 2010-02-22 | 2013-11-26 | Asm International N.V. | High temperature atomic layer deposition of dielectric oxides |
US10002780B2 (en) * | 2016-05-17 | 2018-06-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of manufacturing a semiconductor structure |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1597033A (ko) * | 1968-06-19 | 1970-06-22 | ||
US3862859A (en) * | 1972-01-10 | 1975-01-28 | Rca Corp | Method of making a semiconductor device |
US4177321A (en) * | 1972-07-25 | 1979-12-04 | Semiconductor Research Foundation | Single crystal of semiconductive material on crystal of insulating material |
US4046618A (en) * | 1972-12-29 | 1977-09-06 | International Business Machines Corporation | Method for preparing large single crystal thin films |
US4147584A (en) * | 1977-12-27 | 1979-04-03 | Burroughs Corporation | Method for providing low cost wafers for use as substrates for integrated circuits |
JPS5541709A (en) * | 1978-09-16 | 1980-03-24 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Sos semiconductor base |
US4381201A (en) * | 1980-03-11 | 1983-04-26 | Fujitsu Limited | Method for production of semiconductor devices |
US4279688A (en) * | 1980-03-17 | 1981-07-21 | Rca Corporation | Method of improving silicon crystal perfection in silicon on sapphire devices |
US4358326A (en) * | 1980-11-03 | 1982-11-09 | International Business Machines Corporation | Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing |
US4448632A (en) * | 1981-05-25 | 1984-05-15 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor devices |
-
1984
- 1984-03-28 JP JP59060403A patent/JPS60202952A/ja active Granted
-
1985
- 1985-03-28 DE DE8585400604T patent/DE3587377T2/de not_active Expired - Lifetime
- 1985-03-28 KR KR1019850002066A patent/KR900000203B1/ko not_active IP Right Cessation
- 1985-03-28 EP EP85400604A patent/EP0159252B1/en not_active Expired - Lifetime
-
1987
- 1987-07-15 US US07/073,839 patent/US5037774A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR900000203B1 (ko) | 1990-01-23 |
DE3587377D1 (de) | 1993-07-08 |
JPS60202952A (ja) | 1985-10-14 |
EP0159252A2 (en) | 1985-10-23 |
US5037774A (en) | 1991-08-06 |
EP0159252B1 (en) | 1993-06-02 |
JPH0542824B2 (ko) | 1993-06-29 |
DE3587377T2 (de) | 1993-09-23 |
EP0159252A3 (en) | 1988-09-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20050110 Year of fee payment: 16 |
|
EXPY | Expiration of term |