KR20220103973A - 컴퓨터 시스템 및 정보 처리 장치의 동작 방법 - Google Patents

컴퓨터 시스템 및 정보 처리 장치의 동작 방법 Download PDF

Info

Publication number
KR20220103973A
KR20220103973A KR1020227018723A KR20227018723A KR20220103973A KR 20220103973 A KR20220103973 A KR 20220103973A KR 1020227018723 A KR1020227018723 A KR 1020227018723A KR 20227018723 A KR20227018723 A KR 20227018723A KR 20220103973 A KR20220103973 A KR 20220103973A
Authority
KR
South Korea
Prior art keywords
transistor
wiring
memory
memory cell
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020227018723A
Other languages
English (en)
Korean (ko)
Inventor
순페이 야마자키
타카유키 이케다
히토시 쿠니타케
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 한도오따이 에네루기 켄큐쇼 filed Critical 가부시키가이샤 한도오따이 에네루기 켄큐쇼
Publication of KR20220103973A publication Critical patent/KR20220103973A/ko
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C14/00Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0063Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H01L27/108
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6728Vertical TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • G11C11/4087Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0403Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
KR1020227018723A 2019-11-22 2020-11-09 컴퓨터 시스템 및 정보 처리 장치의 동작 방법 Pending KR20220103973A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JPJP-P-2019-211795 2019-11-22
JP2019211795 2019-11-22
JPJP-P-2019-220177 2019-12-05
JP2019220177 2019-12-05
PCT/IB2020/060503 WO2021099879A1 (ja) 2019-11-22 2020-11-09 コンピュータシステム、及び情報処理装置の動作方法

Publications (1)

Publication Number Publication Date
KR20220103973A true KR20220103973A (ko) 2022-07-25

Family

ID=75981168

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020227018723A Pending KR20220103973A (ko) 2019-11-22 2020-11-09 컴퓨터 시스템 및 정보 처리 장치의 동작 방법

Country Status (5)

Country Link
US (2) US12475948B2 (https=)
JP (3) JPWO2021099879A1 (https=)
KR (1) KR20220103973A (https=)
CN (1) CN114730582A (https=)
WO (1) WO2021099879A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230074757A (ko) 2020-10-02 2023-05-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US12218244B2 (en) * 2021-07-08 2025-02-04 Tokyo Electron Limited Vertical transistor structures and methods utilizing selective formation
US12262522B2 (en) * 2022-02-25 2025-03-25 Changxin Memory Technologies, Inc. Method for fabricating semiconductor structure, semiconductor structure, and memory
JP2024043940A (ja) * 2022-09-20 2024-04-02 キオクシア株式会社 半導体記憶装置および半導体記憶装置の製造方法

Family Cites Families (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0834257B2 (ja) 1990-04-20 1996-03-29 株式会社東芝 半導体メモリセル
KR100387529B1 (ko) 2001-06-11 2003-06-18 삼성전자주식회사 랜덤 억세스 가능한 메모리 셀 어레이를 갖는 불휘발성반도체 메모리 장치
JP5138869B2 (ja) 2002-11-28 2013-02-06 ルネサスエレクトロニクス株式会社 メモリモジュール及びメモリシステム
JP4805696B2 (ja) 2006-03-09 2011-11-02 株式会社東芝 半導体集積回路装置およびそのデータ記録方式
US8649554B2 (en) 2009-05-01 2014-02-11 Microsoft Corporation Method to control perspective for a camera-controlled computer
KR101870119B1 (ko) 2009-12-25 2018-06-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2011187794A (ja) 2010-03-10 2011-09-22 Toshiba Corp 半導体記憶装置及びその製造方法
KR101884031B1 (ko) 2010-04-07 2018-07-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기억 장치
JP5709197B2 (ja) 2010-05-21 2015-04-30 国立大学法人 東京大学 集積回路装置
KR101853516B1 (ko) 2010-07-27 2018-04-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR101258327B1 (ko) 2010-10-13 2013-04-25 주식회사 팬택 플렉서블 디스플레이부를 구비한 장치 및 그 디스플레이 방법
JP2012146861A (ja) 2011-01-13 2012-08-02 Toshiba Corp 半導体記憶装置
KR20130011138A (ko) 2011-07-20 2013-01-30 삼성전자주식회사 모노 랭크와 멀티 랭크로 호환 가능한 메모리 장치
WO2013080985A1 (ja) 2011-11-30 2013-06-06 シャープ株式会社 制御ユニット、該制御ユニットを含む表示装置、及び、制御方法
JP5842602B2 (ja) 2011-12-26 2016-01-13 株式会社Joled 曲面ディスプレイ
JP5926655B2 (ja) * 2012-08-30 2016-05-25 ルネサスエレクトロニクス株式会社 中央処理装置および演算装置
KR102033618B1 (ko) 2012-12-18 2019-10-17 엘지디스플레이 주식회사 표시장치와 이의 구동방법
KR102071573B1 (ko) 2013-06-13 2020-03-02 삼성전자주식회사 외부 클락 신호를 이용하여 오실레이터의 주파수를 조절할 수 있는 디스플레이 드라이버 ic, 이를 포함하는 장치, 및 이들의 동작 방법
JP2015056642A (ja) 2013-09-13 2015-03-23 株式会社東芝 半導体記憶装置
US9973692B2 (en) 2013-10-03 2018-05-15 Flir Systems, Inc. Situational awareness by compressed display of panoramic views
JP2015075516A (ja) 2013-10-07 2015-04-20 ソニー株式会社 画像処理装置、画像処理方法、および表示装置
US20150155039A1 (en) 2013-12-02 2015-06-04 Silicon Storage Technology, Inc. Three-Dimensional Flash NOR Memory System With Configurable Pins
KR102172980B1 (ko) 2014-04-07 2020-11-02 삼성전자주식회사 타일드 디스플레이 시스템 및 그 화상 처리 방법
US9544994B2 (en) 2014-08-30 2017-01-10 Lg Display Co., Ltd. Flexible display device with side crack protection structure and manufacturing method for the same
US9543370B2 (en) 2014-09-24 2017-01-10 Apple Inc. Silicon and semiconducting oxide thin-film transistor displays
US9634097B2 (en) 2014-11-25 2017-04-25 Sandisk Technologies Llc 3D NAND with oxide semiconductor channel
US9761732B2 (en) 2015-02-25 2017-09-12 Snaptrack Inc. Tunnel thin film transistor with hetero-junction structure
JP6343256B2 (ja) 2015-05-29 2018-06-13 東芝メモリ株式会社 半導体装置及びその製造方法
KR102491624B1 (ko) * 2015-07-27 2023-01-25 삼성전자주식회사 데이터 저장 장치의 작동 방법과 상기 데이터 저장 장치를 포함하는 시스템의 작동 방법
JP6400536B2 (ja) 2015-08-04 2018-10-03 東芝メモリ株式会社 半導体記憶装置
US10410599B2 (en) 2015-08-13 2019-09-10 Samsung Electronics Co., Ltd. Source driver integrated circuit for ompensating for display fan-out and display system including the same
JP6545587B2 (ja) 2015-09-15 2019-07-17 東芝メモリ株式会社 半導体装置
WO2017068478A1 (en) * 2015-10-22 2017-04-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device or memory device including the semiconductor device
KR20180081732A (ko) 2015-11-13 2018-07-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 전자 부품, 및 전자 기기
US10475370B2 (en) 2016-02-17 2019-11-12 Google Llc Foveally-rendered display
JP2017207747A (ja) 2016-05-17 2017-11-24 株式会社半導体エネルギー研究所 表示システムおよび移動体
US10210915B2 (en) 2016-06-10 2019-02-19 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device including the same
KR102696801B1 (ko) 2016-07-27 2024-08-20 삼성전자주식회사 수직형 메모리 소자 및 이의 제조방법
WO2018029820A1 (ja) 2016-08-10 2018-02-15 株式会社日立製作所 計算機システム
WO2018047035A1 (en) 2016-09-12 2018-03-15 Semiconductor Energy Laboratory Co., Ltd. Memory device, driving method thereof, semiconductor device, electronic component, and electronic device
US10593693B2 (en) 2017-06-16 2020-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
JP7195068B2 (ja) 2017-06-26 2022-12-23 株式会社半導体エネルギー研究所 半導体装置、電子機器
US11682667B2 (en) 2017-06-27 2023-06-20 Semiconductor Energy Laboratory Co., Ltd. Memory cell including cell transistor including control gate and charge accumulation layer
JP7234110B2 (ja) 2017-07-06 2023-03-07 株式会社半導体エネルギー研究所 メモリセル及び半導体装置
CN110291586B (zh) * 2019-05-17 2020-10-30 长江存储科技有限责任公司 具有静态随机存取存储器的三维存储器件的高速缓存程序操作
TW202602212A (zh) 2019-10-31 2026-01-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置
JP2022027240A (ja) * 2020-07-31 2022-02-10 ソニーセミコンダクタソリューションズ株式会社 情報処理装置および情報処理方法
US11720261B2 (en) * 2020-08-10 2023-08-08 Micron Technology, Inc. Transferring memory system data to a host system

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
N.Sakimura et al., ISSCC Dig.Tech.Papers, pp.184-185, 2014.
S.Bartling et al., ISSCC Dig.Tech.Papers, pp.432-434, 2013.
T.Ishizu et al., Int. Memory Workshop, 2014, pp.106-103.
VK.Singhal et al., ISSCC Dig.Tech.Papers, pp.148-149, 2015.

Also Published As

Publication number Publication date
WO2021099879A1 (ja) 2021-05-27
US20260045302A1 (en) 2026-02-12
JP7769824B2 (ja) 2025-11-13
JPWO2021099879A1 (https=) 2021-05-27
CN114730582A (zh) 2022-07-08
JP2025069268A (ja) 2025-04-30
US20220375521A1 (en) 2022-11-24
JP2026021464A (ja) 2026-02-10
US12475948B2 (en) 2025-11-18

Similar Documents

Publication Publication Date Title
US12396215B2 (en) Semiconductor device and electronic device
JP7769824B2 (ja) 演算処理装置の動作方法
US20250166713A1 (en) Memory Device, Operation Method of Memory Device, Data Processing Device, Data Processing System, and Electronic Device
US20240298447A1 (en) Semiconductor device, driving method of semiconductor device, and electronic device
US20260122891A1 (en) Semiconductor device and electronic device
KR20240052666A (ko) 반도체 장치
JP2025185071A (ja) 半導体装置
JP7711280B2 (ja) 情報処理装置の動作方法
WO2023144652A1 (ja) 記憶装置
WO2023144653A1 (ja) 記憶装置

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D21 Rejection of application intended

Free format text: ST27 STATUS EVENT CODE: A-1-2-D10-D21-EXM-PE0902 (AS PROVIDED BY THE NATIONAL OFFICE)

PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11 Administrative time limit extension requested

Free format text: ST27 STATUS EVENT CODE: U-3-3-T10-T11-OTH-X000 (AS PROVIDED BY THE NATIONAL OFFICE)

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000