JPWO2021099879A1 - - Google Patents
Info
- Publication number
- JPWO2021099879A1 JPWO2021099879A1 JP2021558028A JP2021558028A JPWO2021099879A1 JP WO2021099879 A1 JPWO2021099879 A1 JP WO2021099879A1 JP 2021558028 A JP2021558028 A JP 2021558028A JP 2021558028 A JP2021558028 A JP 2021558028A JP WO2021099879 A1 JPWO2021099879 A1 JP WO2021099879A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0063—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6728—Vertical TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0403—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2025012741A JP7769824B2 (ja) | 2019-11-22 | 2025-01-29 | 演算処理装置の動作方法 |
| JP2025184125A JP2026021464A (ja) | 2019-11-22 | 2025-10-31 | 情報処理装置の動作方法 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019211795 | 2019-11-22 | ||
| JP2019220177 | 2019-12-05 | ||
| PCT/IB2020/060503 WO2021099879A1 (ja) | 2019-11-22 | 2020-11-09 | コンピュータシステム、及び情報処理装置の動作方法 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025012741A Division JP7769824B2 (ja) | 2019-11-22 | 2025-01-29 | 演算処理装置の動作方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2021099879A1 true JPWO2021099879A1 (https=) | 2021-05-27 |
| JPWO2021099879A5 JPWO2021099879A5 (https=) | 2023-11-07 |
Family
ID=75981168
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021558028A Withdrawn JPWO2021099879A1 (https=) | 2019-11-22 | 2020-11-09 | |
| JP2025012741A Active JP7769824B2 (ja) | 2019-11-22 | 2025-01-29 | 演算処理装置の動作方法 |
| JP2025184125A Pending JP2026021464A (ja) | 2019-11-22 | 2025-10-31 | 情報処理装置の動作方法 |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025012741A Active JP7769824B2 (ja) | 2019-11-22 | 2025-01-29 | 演算処理装置の動作方法 |
| JP2025184125A Pending JP2026021464A (ja) | 2019-11-22 | 2025-10-31 | 情報処理装置の動作方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US12475948B2 (https=) |
| JP (3) | JPWO2021099879A1 (https=) |
| KR (1) | KR20220103973A (https=) |
| CN (1) | CN114730582A (https=) |
| WO (1) | WO2021099879A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230074757A (ko) | 2020-10-02 | 2023-05-31 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
| US12218244B2 (en) * | 2021-07-08 | 2025-02-04 | Tokyo Electron Limited | Vertical transistor structures and methods utilizing selective formation |
| US12262522B2 (en) * | 2022-02-25 | 2025-03-25 | Changxin Memory Technologies, Inc. | Method for fabricating semiconductor structure, semiconductor structure, and memory |
| JP2024043940A (ja) * | 2022-09-20 | 2024-04-02 | キオクシア株式会社 | 半導体記憶装置および半導体記憶装置の製造方法 |
Citations (4)
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| WO2018029820A1 (ja) * | 2016-08-10 | 2018-02-15 | 株式会社日立製作所 | 計算機システム |
| JP2018152152A (ja) * | 2016-09-12 | 2018-09-27 | 株式会社半導体エネルギー研究所 | 記憶装置とその動作方法、並びに半導体装置、電子部品および電子機器 |
| WO2019008483A1 (ja) * | 2017-07-06 | 2019-01-10 | 株式会社半導体エネルギー研究所 | 半導体装置及び半導体装置の駆動方法 |
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-
2020
- 2020-11-09 KR KR1020227018723A patent/KR20220103973A/ko active Pending
- 2020-11-09 JP JP2021558028A patent/JPWO2021099879A1/ja not_active Withdrawn
- 2020-11-09 US US17/773,887 patent/US12475948B2/en active Active
- 2020-11-09 WO PCT/IB2020/060503 patent/WO2021099879A1/ja not_active Ceased
- 2020-11-09 CN CN202080079582.0A patent/CN114730582A/zh active Pending
-
2025
- 2025-01-29 JP JP2025012741A patent/JP7769824B2/ja active Active
- 2025-10-21 US US19/363,828 patent/US20260045302A1/en active Pending
- 2025-10-31 JP JP2025184125A patent/JP2026021464A/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017224377A (ja) * | 2016-06-10 | 2017-12-21 | 株式会社半導体エネルギー研究所 | メモリ装置、およびそれを有する半導体装置 |
| WO2018029820A1 (ja) * | 2016-08-10 | 2018-02-15 | 株式会社日立製作所 | 計算機システム |
| JP2018152152A (ja) * | 2016-09-12 | 2018-09-27 | 株式会社半導体エネルギー研究所 | 記憶装置とその動作方法、並びに半導体装置、電子部品および電子機器 |
| WO2019008483A1 (ja) * | 2017-07-06 | 2019-01-10 | 株式会社半導体エネルギー研究所 | 半導体装置及び半導体装置の駆動方法 |
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| WO2021099879A1 (ja) | 2021-05-27 |
| US20260045302A1 (en) | 2026-02-12 |
| JP7769824B2 (ja) | 2025-11-13 |
| CN114730582A (zh) | 2022-07-08 |
| JP2025069268A (ja) | 2025-04-30 |
| US20220375521A1 (en) | 2022-11-24 |
| JP2026021464A (ja) | 2026-02-10 |
| KR20220103973A (ko) | 2022-07-25 |
| US12475948B2 (en) | 2025-11-18 |
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