KR20160145801A - 관통-유리 비아의 제조를 위한 본딩 재료의 엣칭 백 공정 - Google Patents

관통-유리 비아의 제조를 위한 본딩 재료의 엣칭 백 공정 Download PDF

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Publication number
KR20160145801A
KR20160145801A KR1020167032591A KR20167032591A KR20160145801A KR 20160145801 A KR20160145801 A KR 20160145801A KR 1020167032591 A KR1020167032591 A KR 1020167032591A KR 20167032591 A KR20167032591 A KR 20167032591A KR 20160145801 A KR20160145801 A KR 20160145801A
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KR
South Korea
Prior art keywords
substrate
bonding layer
holes
vias
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020167032591A
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English (en)
Korean (ko)
Inventor
치-웨이 차이
보르 카이 왕
Original Assignee
코닝 인코포레이티드
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Application filed by 코닝 인코포레이티드 filed Critical 코닝 인코포레이티드
Publication of KR20160145801A publication Critical patent/KR20160145801A/ko
Withdrawn legal-status Critical Current

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    • H01L21/486—
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C15/00—Surface treatment of glass, not in the form of fibres or filaments, by etching
    • H01L21/6835—
    • H01L23/15—
    • H01L23/49827—
    • H01L23/49838—
    • H01L23/49866—
    • H01L23/49894—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H01L2221/68345—
    • H01L2221/68359—
    • H01L2221/68381—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geochemistry & Mineralogy (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Surface Treatment Of Glass (AREA)
  • Ceramic Engineering (AREA)
KR1020167032591A 2014-04-30 2015-04-29 관통-유리 비아의 제조를 위한 본딩 재료의 엣칭 백 공정 Withdrawn KR20160145801A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201461986370P 2014-04-30 2014-04-30
US61/986,370 2014-04-30
PCT/US2015/028200 WO2015168236A1 (en) 2014-04-30 2015-04-29 Etch back processes of bonding material for the manufacture of through-glass vias

Publications (1)

Publication Number Publication Date
KR20160145801A true KR20160145801A (ko) 2016-12-20

Family

ID=53177892

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167032591A Withdrawn KR20160145801A (ko) 2014-04-30 2015-04-29 관통-유리 비아의 제조를 위한 본딩 재료의 엣칭 백 공정

Country Status (7)

Country Link
US (2) US9263300B2 (enExample)
EP (1) EP3138120B1 (enExample)
JP (1) JP2017520906A (enExample)
KR (1) KR20160145801A (enExample)
CN (1) CN106470953B (enExample)
TW (1) TWI659002B (enExample)
WO (1) WO2015168236A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017520906A (ja) * 2014-04-30 2017-07-27 コーニング インコーポレイテッド 貫通ガラスバイアの作製のための接合材料のエッチバックプロセス
US10410883B2 (en) 2016-06-01 2019-09-10 Corning Incorporated Articles and methods of forming vias in substrates
US10794679B2 (en) 2016-06-29 2020-10-06 Corning Incorporated Method and system for measuring geometric parameters of through holes
US10134657B2 (en) 2016-06-29 2018-11-20 Corning Incorporated Inorganic wafer having through-holes attached to semiconductor wafer
EP3542395A4 (en) * 2016-11-18 2020-06-17 Samtec, Inc. Filling materials and methods of filling through holes of a substrate
CN108231646A (zh) * 2016-12-13 2018-06-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US11078112B2 (en) 2017-05-25 2021-08-03 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same
US10580725B2 (en) 2017-05-25 2020-03-03 Corning Incorporated Articles having vias with geometry attributes and methods for fabricating the same
US12180108B2 (en) 2017-12-19 2024-12-31 Corning Incorporated Methods for etching vias in glass-based articles employing positive charge organic molecules
US11554984B2 (en) 2018-02-22 2023-01-17 Corning Incorporated Alkali-free borosilicate glasses with low post-HF etch roughness
US12009225B2 (en) 2018-03-30 2024-06-11 Samtec, Inc. Electrically conductive vias and methods for producing same
US11148935B2 (en) 2019-02-22 2021-10-19 Menlo Microsystems, Inc. Full symmetric multi-throw switch using conformal pinched through via
WO2021167787A1 (en) * 2020-02-18 2021-08-26 Corning Incorporated Etching of glass surfaces to reduce electrostatic charging during processing
US11856711B2 (en) * 2020-10-28 2023-12-26 Infineon Technologies Austria Ag Rogowski coil integrated in glass substrate
CN117747504B (zh) * 2023-12-20 2024-07-19 西安赛富乐斯半导体科技有限公司 粘合胶层厚度调整方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006161124A (ja) * 2004-12-09 2006-06-22 Canon Inc 貫通電極の形成方法
US7425507B2 (en) 2005-06-28 2008-09-16 Micron Technology, Inc. Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
JP4889974B2 (ja) * 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
US7429529B2 (en) * 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
JP2007067031A (ja) * 2005-08-30 2007-03-15 Tdk Corp 配線基板の製造方法
US8455357B2 (en) * 2008-10-10 2013-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method of plating through wafer vias in a wafer for 3D packaging
JP5201048B2 (ja) * 2009-03-25 2013-06-05 富士通株式会社 半導体装置とその製造方法
US20110229687A1 (en) 2010-03-19 2011-09-22 Qualcomm Incorporated Through Glass Via Manufacturing Process
US8411459B2 (en) 2010-06-10 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd Interposer-on-glass package structures
JP5729932B2 (ja) 2010-07-22 2015-06-03 キヤノン株式会社 基板貫通孔内への金属充填方法
US9278886B2 (en) 2010-11-30 2016-03-08 Corning Incorporated Methods of forming high-density arrays of holes in glass
TWI547454B (zh) 2011-05-31 2016-09-01 康寧公司 於玻璃中高速製造微孔洞的方法
WO2013008344A1 (ja) * 2011-07-14 2013-01-17 株式会社島津製作所 プラズマ処理装置
WO2014038326A1 (ja) 2012-09-07 2014-03-13 旭硝子株式会社 インターポーザ用の中間品を製造する方法およびインターポーザ用の中間品
EP2925482A1 (en) 2012-11-29 2015-10-07 Corning Incorporated Sacrificial cover layers for laser drilling substrates and methods thereof
US9425125B2 (en) * 2014-02-20 2016-08-23 Altera Corporation Silicon-glass hybrid interposer circuitry
JP2017520906A (ja) * 2014-04-30 2017-07-27 コーニング インコーポレイテッド 貫通ガラスバイアの作製のための接合材料のエッチバックプロセス

Also Published As

Publication number Publication date
EP3138120B1 (en) 2018-04-18
US20160155696A1 (en) 2016-06-02
TWI659002B (zh) 2019-05-11
CN106470953A (zh) 2017-03-01
WO2015168236A1 (en) 2015-11-05
US9263300B2 (en) 2016-02-16
EP3138120A1 (en) 2017-03-08
CN106470953B (zh) 2019-03-12
JP2017520906A (ja) 2017-07-27
TW201600484A (zh) 2016-01-01
US20150318187A1 (en) 2015-11-05

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